uint64_t fw_l1p_readCrossCore( uint64_t address ) {
int retries = 1000;
uint64_t result = 0, esr = 0;
while ( ( --retries ) > 0 ) {
result = in64( (void *) address );
esr = in64( (void*)L1P_ESR_DCR(ProcessorCoreID() ) );
if ( ( esr & L1P_ESR_err_lu_dcr_abort ) == 0 ) {
return result;
}
out64_sync( (void*)L1P_ESR_DCR(ProcessorCoreID()), L1P_ESR_err_lu_dcr_abort );
}
FW_Error( "Could not perform cross-core L1P register read addr=%X esr=%X.", address, esr );
return -1;
}
int main(int argc, char * argv[])
{
num_threads = (argc>1) ? atoi(argv[1]) : 1;
printf("L2 counter test using %d threads \n", num_threads );
//printf("sizeof(BGQ_Atomic64_t) = %zu \n", sizeof(BGQ_Atomic64_t) );
/* this "activates" the L2 atomic data structures */
Kernel_L2AtomicsAllocate(&counter, sizeof(BGQ_Atomic64_t) );
L2_AtomicStore(&(counter.atom), 0);
out64_sync(&(counter.atom), 0);
pool = (pthread_t *) malloc( num_threads * sizeof(pthread_t) );
assert(pool!=NULL);
/**************************************************/
for (int i=0; i<num_threads; i++) {
int rc = pthread_create(&(pool[i]), NULL, &fight, NULL);
if (rc!=0) {
printf("pthread error \n");
fflush(stdout);
sleep(1);
}
assert(rc==0);
}
if (debug) {
printf("threads created \n");
fflush(stdout);
}
for (int i=0; i<num_threads; i++) {
void * junk;
int rc = pthread_join(pool[i], &junk);
if (rc!=0) {
printf("pthread error \n");
fflush(stdout);
sleep(1);
}
assert(rc==0);
}
if (debug) {
printf("threads joined \n");
fflush(stdout);
}
uint64_t rval = L2_AtomicLoad(&(counter.atom));
printf("final value of counter is %llu \n", rval);
/**************************************************/
for (int i=0; i<num_threads; i++) {
int rc = pthread_create(&(pool[i]), NULL, &slowfight, NULL);
if (rc!=0) {
printf("pthread error \n");
fflush(stdout);
sleep(1);
}
assert(rc==0);
}
printf("threads created \n");
fflush(stdout);
for (int i=0; i<num_threads; i++) {
void * junk;
int rc = pthread_join(pool[i], &junk);
if (rc!=0) {
printf("pthread error \n");
fflush(stdout);
sleep(1);
}
assert(rc==0);
}
printf("threads joined \n");
fflush(stdout);
rval = in64(&(slowcounter.atom));
printf("final value of slowcounter is %llu \n", rval);
/**************************************************/
free(pool);
return 0;
}
int fw_l1p_machineCheckHandler( uint64_t mappedStatus[] ) {
uint64_t core, pass;
fw_uint64_t details[17*2*6];
unsigned n = 0;
int rc = 0; // unless set otherwise below
uint64_t correctableMask = FW_L1P_CORRECTABLE_MASK;
// +--------------------------------------------------------------------+
// | HW Issue 1596 workaround: Disable DCR Arbiter Timeouts |
// +--------------------------------------------------------------------+
uint64_t dcr_arbiter_ctrl_low = DCRReadPriv(DC_ARBITER_DCR( INT_REG_CONTROL_LOW));
DCRWritePriv( DC_ARBITER_DCR( INT_REG_CONTROL_LOW), dcr_arbiter_ctrl_low & ~DC_ARBITER_DCR__INT_REG_CONTROL_LOW__NO_ACK_AFTER_REQ_set(-1) );
for ( pass = 0; pass < 2; pass++ ) {
n = 0;
uint64_t statusMask = GEA_DCR__GEA_MAPPED_INTERRUPT_STATUS0_0__L1P0_RT_INT_set(1);
for (core = 0; core < 17; core++, statusMask >>= 1 ) {
// +---------------------------------------------------------------------------------------+
// | HW Issue 1596 : Only perform a cross-core ESR access if the mapped status indicates |
// | that it is interesting to do so. This reduces the exposure to the |
// | hardware bug documented in that issue. |
// +---------------------------------------------------------------------------------------+
if ( ( mappedStatus[0] & statusMask ) != 0 ) {
uint64_t status, error;
status = fw_l1p_readCrossCore( L1P_ESR_DCR(core) );
status &= ( ( pass == 0 ) ? correctableMask : ~correctableMask );
if ( status == 0 )
continue;
if ( pass == 0 ) {
fw_l1p_handleCorrectable( status, core );
// +------------------------------------------------------------------------------------------+
// | This funky little sequence seems to be required to clean up the A2 machine check bit |
// | (bit 0) of the ESR. It came from Krishnan and does the following: |
// | |
// | o masks interrupts |
// | o clears the MCSR[EXT] bit |
// | o clears the L1P_ESR[0] bit |
// | o re-enables interrupts |
// | |
// +------------------------------------------------------------------------------------------+
uint64_t thisCore = ProcessorCoreID();
uint64_t esrMask = in64( (void*)L1P_ESR_GEA_DCR(thisCore));
out64_sync( (void*)L1P_ESR_GEA_DCR(thisCore), 0 );
mtspr( SPRN_MCSR, mfspr(SPRN_MCSR) & ~MCSR_EXT );
out64_sync( (void*)L1P_ESR_DCR(thisCore), L1P_ESR_a2_machine_check );
out64_sync( (void*)L1P_ESR_GEA_DCR(thisCore), esrMask );
}
else {
details[n++] = L1P_ESR_DCR(core);
details[n++] = status;
status = L1P_DCR_PRIV_PTR(core)->interrupt_state_a__machine_check;
error = L1P_DCR_PRIV_PTR(core)->interrupt_internal_error__machine_check;
if ( status != 0 ) {
details[n++] = L1P_DCR( core,INTERRUPT_STATE_A__MACHINE_CHECK);
details[n++] = status;
}
if ( error != 0 ) {
details[n++] = L1P_DCR(core,INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH);
details[n++] = error;
}
rc = -1;
}
}
}
if ( n > 0 ) {
fw_machineCheckRas( FW_RAS_L1P_MACHINE_CHECK, details, n, __FILE__, __LINE__ );
}
}
// +--------------------------------------------------------------------------+
// | HW Issue 1596 workaround: Force-clear any DCR timeouts and restore the |
// | control register. |
// +--------------------------------------------------------------------------+
DCRWritePriv( DC_ARBITER_DCR( INT_REG__STATE ), DC_ARBITER_DCR__INT_REG__NO_ACK_AFTER_REQ_set(1) );
ppc_msync();
DCRWritePriv( DC_ARBITER_DCR( INT_REG_CONTROL_LOW), dcr_arbiter_ctrl_low );
return rc;
}
int fw_l1p_init( void ) {
TRACE_ENTRY(TRACE_L1P);
uint64_t cfg_spec = L1P_CFG_SPEC_l1_hit_fwd_l2;
uint64_t cfg_pf_usr = L1P_CFG_PF_USR_dfetch_depth(2)
| L1P_CFG_PF_USR_dfetch_max_footprint(7)
| L1P_CFG_PF_USR_ifetch_depth(0)
| L1P_CFG_PF_USR_ifetch_max_footprint(2)
| L1P_CFG_PF_USR_pf_stream_est_on_dcbt
// [DISABLED] | L1P_CFG_PF_USR_pf_stream_optimistic
| L1P_CFG_PF_USR_pf_stream_prefetch_enable
| L1P_CFG_PF_USR_pf_stream_establish_enable
| L1P_CFG_PF_USR_pf_adaptive_enable
| L1P_CFG_PF_USR_pf_adaptive_throttle(0xF) ;
/* UNUSED | L1P_CFG_PF_USR_pf_list_enable */
uint64_t cfg_pf_sys =
L1P_CFG_PF_SYS_msync_timer(7+3)
| L1P_CFG_PF_SYS_pfhint_enable
| L1P_CFG_PF_SYS_whint_evict_enable
| L1P_CFG_PF_SYS_whint_cracked_enable
| L1P_CFG_PF_SYS_lock_prefetch
| L1P_CFG_PF_SYS_dcbfl_discard
| L1P_CFG_PF_SYS_pf_adaptive_total_depth(24)
| L1P_CFG_PF_SYS_pf_hit_enable
| L1P_CFG_PF_SYS_pf_stream_l2_op_immediate ;
if(!FW_DD1_WORKAROUNDS_ENABLED())
{
cfg_pf_sys |= L1P_CFG_PF_SYS_wrap_bug_dd2_bhv;
}
uint64_t cfg_wc = L1P_CFG_WC_wc_enable
| L1P_CFG_WC_wc_suppress_if_all_be
| L1P_CFG_WC_wc_aging ;
uint64_t cfg_to = L1P_CFG_TO_to_en
| L1P_CFG_TO_to_reload_en
| L1P_CFG_TO_to_duration(0x3) ;
uint64_t cfg_upc = L1P_CFG_UPC_ENABLE
| L1P_CFG_UPC_STREAM;
out64_sync((void *)L1P_CFG_SPEC,cfg_spec);
out64_sync((void *)L1P_CFG_PF_USR,cfg_pf_usr);
out64_sync((void *)L1P_CFG_PF_SYS,L1P_CFG_PF_SYS_pf_adaptive_reset|cfg_pf_sys);
out64_sync((void *)L1P_CFG_PF_SYS,cfg_pf_sys);
out64_sync((void *)L1P_CFG_WC,cfg_wc);
out64_sync((void *)L1P_CFG_TO,cfg_to);
out64_sync((void *)L1P_CFG_UPC,cfg_upc);
/* Enable L1p hardware error interrupts */
uint64_t esr_gea =
// [disabled] L1P_ESR_int_list_0 |
// [disabled] L1P_ESR_int_list_1 |
// [disabled] L1P_ESR_int_list_2 |
// [disabled] L1P_ESR_int_list_3 |
// [disabled] L1P_ESR_int_list_4 |
// [disabled] L1P_ESR_int_speculation_0 |
// [disabled] L1P_ESR_int_speculation_1 |
// [disabled] L1P_ESR_int_speculation_2 |
// [disabled] L1P_ESR_int_speculation_3 |
// [disabled] L1P_ESR_err_valid_timeout | [see bqcbugs #1612]
L1P_ESR_err_luq_ovfl |
L1P_ESR_err_sr_p |
L1P_ESR_err_sr_rd_valid_p |
L1P_ESR_err_sw_p |
L1P_ESR_err_si_ecc_ue |
L1P_ESR_err_si_p |
L1P_ESR_err_sda_p_ue |
L1P_ESR_err_rqra_p |
L1P_ESR_err_reload_ecc_ue_x2 |
L1P_ESR_err_rira_p |
L1P_ESR_err_gctr_p |
L1P_ESR_err_lu_state_p |
L1P_ESR_err_lu_ttype |
// [5470] L1P_ESR_err_lu_dcr_abort |
L1P_ESR_err_mmio_async |
L1P_ESR_err_mmio_state_p |
L1P_ESR_err_mmio_timeout |
L1P_ESR_err_mmio_priv |
L1P_ESR_err_mmio_rdata_p |
L1P_ESR_err_mmio_wdata_p |
L1P_ESR_err_mmio_dcrs_timeout |
L1P_ESR_err_mmio_dcrs_priv |
L1P_ESR_err_mmio_dcrs_par |
L1P_ESR_err_dcrm_crit |
L1P_ESR_err_dcrm_noncrit |
// [5470] L1P_ESR_err_dcrm_mc |
L1P_ESR_err_tag_timeout |
L1P_ESR_err_hold_timeout |
L1P_ESR_err_ditc_req_x2 |
L1P_ESR_err_pfd_addr_p |
L1P_ESR_err_pfd_avalid_p |
L1P_ESR_err_pfd_fill_pnd_p |
L1P_ESR_err_pfd_hit_pnd_p |
L1P_ESR_err_pfd_stream_p |
L1P_ESR_err_pfd_depth_p |
L1P_ESR_err_pfd_clone_p |
L1P_ESR_err_hitq_p |
L1P_ESR_err_sd_p |
L1P_ESR_err_pf2dfc_p |
L1P_ESR_err_wccm_p_x2 |
L1P_ESR_err_wccm_wcd_p_x2 |
L1P_ESR_err_lu_wcd_p |
L1P_ESR_err_lu_current_p |
L1P_ESR_err_l2cmd |
L1P_ESR_err_lu_dcr_dbus_p |
L1P_ESR_err_luq_p |
L1P_ESR_err_sda_phase_p |
L1P_ESR_slice_sel_ctrl_perr |
L1P_ESR_redun_ctrl_perr
;
// +------------------------------------------------------------------------------------------+
// | NOTE: For production environments, we mask L1P correctables during the early part of the |
// | boot. The TakeCPU hook is what allows us to unmask. |
// +------------------------------------------------------------------------------------------+
if ( ! PERS_ENABLED(PERS_ENABLE_TakeCPU) ) {
esr_gea |=
L1P_ESR_err_si_ecc |
L1P_ESR_err_reload_ecc_x2 |
L1P_ESR_err_sda_p
;
}
out64_sync(
(void *)L1P_ESR_GEA,
esr_gea
);
#ifndef FW_PREINSTALLED_GEA_HANDLERS
uint64_t mask[3] = { L1P_GEA_MASK_0, L1P_GEA_MASK_1, L1P_GEA_MASK2 };
fw_installGeaHandler( fw_l1p_machineCheckHandler, mask );
#endif
unsigned core = ProcessorCoreID();
DCRWritePriv( L1P_DCR(core,INTERRUPT_STATE_A_CONTROL_HIGH),
L1P_DCR__INTERRUPT_STATE_A_CONTROL_HIGH__LOCAL_RING_set(1) | // Global Interrupt
0 );
DCRWritePriv( L1P_DCR(core,INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH),
// [5470] L1P_DCR__INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH__BAD_ADDRESS_set(1) |
// [5470] L1P_DCR__INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH__BAD_PRIV_set(1) |
L1P_DCR__INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH__BAD_DATA_PARITY_set(1) |
L1P_DCR__INTERRUPT_INTERNAL_ERROR_CONTROL_HIGH__BAD_ADDRESS_PARITY_set(1) |
0 );
if(A2_isDD1())
{
*(volatile uint64_t*)L1P_CFG_CLK_GATE = _B1(61,1);
}
else
{
*(volatile uint64_t*)L1P_CFG_CLK_GATE = L1P_CFG_CLK_GATE_clk_on_sw_req;
}
if(!FW_DD1_WORKAROUNDS_ENABLED())
{
*(volatile uint64_t*)L1P_CFG_CHICKEN |= L1P_CFG_CHICKEN_DD2;
}
fw_l1p_resetCEThresholds();
#if 0
if ( ProcessorCoreID() == 2 ) {
// DO NOT INTEGRATE THIS CODE!!!!!!!!!!!
uint64_t inject =
L1P_ESR_err_reload_ecc_x2 |
//L1P_ESR_err_si_ecc |
//L1P_ESR_err_reload_ecc_ue_x2 |
0 ;
out64_sync((void *)L1P_ESR_INJ_DCR(ProcessorCoreID()), inject );
ppc_msync();
out64_sync((void *)L1P_ESR_INJ_DCR(ProcessorCoreID()), 0 );
ppc_msync();
}
#endif
TRACE_EXIT(TRACE_L1P);
return( 0 );
}
int test_main( void ) {
int N = BgGetNumThreads();
int irritatorThread = 1;
int iterations = 1;
char* irritator = fwext_getenv("IRRITATOR");
char* testId = fwext_getenv("TEST");
char* itersStr = fwext_getenv("ITERATIONS");
if ( irritator != 0 ) {
irritatorThread = fwext_strtoul( irritator, 0, 0 );
}
if ( itersStr != 0 ) {
iterations = fwext_strtoul( itersStr, 0, 0 );
}
fwext_barrier( &barrier, N );
if ( ProcessorID() == irritatorThread ) {
char* l2Slice = fwext_getenv("L2SLICE");
char* mc = fwext_getenv("MC");
int mci = 0;
if ( mc != 0 ) {
mci = fwext_strtoul( mc, 0, 0 );
}
int i;
for ( i = 0; i < iterations; i++ ) {
if ( i > 0 ) {
fwext_udelay( 250 * 1000 );
}
printf("Test: %s L2Slice:%s MC:%s NumThreads:%d Iter:%d\n", testId, l2Slice, mc ? mc : "?", N, i );
if ( fwext_strcmp("BeDRAM",testId) == 0 ) {
printf("Injecting ...\n");
uint64_t inject = BEDRAM_DCR__BEDRAM_INTERRUPT_STATUS__BEDRAM_EDRAM_ECC_set(1);
DCRWritePriv( BEDRAM_DCR( BEDRAM_INTERRUPT_STATUS__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("ClkStopUnit",testId) == 0 ) {
uint64_t inject = CS_DCR__CLOCKSTOP_INTERRUPT_STATE__STOPPED_set(1);
DCRWritePriv( CS_DCR( CLOCKSTOP_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("DrArbiter",testId) == 0 ) {
uint64_t inject = DC_ARBITER_DCR__INT_REG__RING_NOT_CLEAN_set(1);
DCRWritePriv( DC_ARBITER_DCR( INT_REG__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("DDR",testId) == 0 ) {
DCRWritePriv( _DDR_MC_MCFIRS(mci), MCFIR_POWERBUS_READ_BUFFER_SUE );
uint64_t inject = DR_ARB_DCR__L2_INTERRUPT_STATE__XSTOP_set(1);
DCRWritePriv( DR_ARB_DCR(mci, L2_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("DDR_MARKING_STORE",testId) == 0 ) {
DCRWritePriv( _DDR_MC_MCFIRS(mci), MCFIR_MEMORY_ECC_MARKING_STORE_UPDATED );
uint64_t inject = DR_ARB_DCR__L2_INTERRUPT_STATE__RECOV_ERR_set(1);
DCRWritePriv( DR_ARB_DCR(mci, L2_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("DDR_Correctable",testId) == 0 ) {
//DCRWritePriv( _DDR_MC_MCFIRS(mci), MCFIR_POWERBUS_WRITE_BUFFER_CE);
//DCRWritePriv( _DDR_MC_MCFIRS(mci), MCFIR_MEMORY_CE );
DCRWritePriv( _DDR_MC_MCFIRS(mci), MCFIR_POWERBUS_READ_BUFFER_SUE );
//uint64_t inject = DR_ARB_DCR__L2_INTERRUPT_STATE__RECOV_ERR_set(1);
//DCRWritePriv( DR_ARB_DCR(mci, L2_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("DDR_Threshold",testId) == 0 ) {
DCRWritePriv( _DDR_MC_MCFIRS(mci), MCFIR_ECC_ERROR_COUNTER_THRESHOLD_REACHED );
uint64_t inject = DR_ARB_DCR__L2_INTERRUPT_STATE__RECOV_ERR_set(1);
DCRWritePriv( DR_ARB_DCR(mci, L2_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("DevBus",testId) == 0 ) {
uint64_t inject = DEVBUS_DCR__DB_INTERRUPT_STATE__SLAVE_FIFO_PARITY_set(1);
DCRWritePriv( DEVBUS_DCR( DB_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("EnvMon",testId) == 0 ) {
uint64_t inject = EN_DCR__ENVMON_INTERRUPT_STATE__FSM_CHECKSUM_FAIL_set(1);
DCRWritePriv( EN_DCR( ENVMON_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("GEA",testId) == 0 ) {
uint64_t inject = GEA_DCR__GEA_INTERRUPT_STATE__DEVBUS_CTL_PERR_set(1);
DCRWritePriv( GEA_DCR( GEA_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
#if 0
{
uint64_t inject = L1P_DCR__INTERRUPT_INTERNAL_ERROR__BAD_DATA_PARITY_set(1);
DCRWritePriv( L1P_DCR(0, INTERRUPT_INTERNAL_ERROR__FORCE ), inject );
ppc_msync();
}
#endif
if ( fwext_strcmp("L1P",testId) == 0 ) {
//printf("Irritating L1 on core %d ...\n", irritatorThread);
#if 0
BIC_InsertInterruptMap( 0, BIC_MAP_L1P_LANE(0), BIC_MACHINE_CHECK );
BIC_InsertInterruptMap( 0, BIC_MAP_L1P_LANE(1), BIC_MACHINE_CHECK );
BIC_InsertInterruptMap( 0, BIC_MAP_L1P_LANE(2), BIC_MACHINE_CHECK );
BIC_InsertInterruptMap( 0, BIC_MAP_L1P_LANE(3), BIC_MACHINE_CHECK );
#endif
int64_t NN ;
printf("INJECTING!\n");
for ( NN = 0; NN < 10000000ull; NN++ ) {
uint64_t inject =
L1P_ESR_err_reload_ecc_x2 |
//L1P_ESR_err_si_ecc |
//L1P_ESR_err_reload_ecc_ue_x2 |
0 ;
out64_sync((void *)L1P_ESR_INJ_DCR(ProcessorCoreID()), inject );
ppc_msync();
out64_sync((void *)L1P_ESR_INJ_DCR(ProcessorCoreID()), 0 );
ppc_msync();
}
printf( "*********************************** Injected %ld CEs into L1P ***********************************************\n", NN);
//printf("L1P_ESR --> %lx\n", in64( (uint64_t*)L1P_ESR));
}
if ( fwext_strcmp("L1PBug",testId) == 0 ) {
printf("Waiting for 2 seconds ...\n");
uint64_t end = GetTimeBase() + 1600ull * 1000ull * 1000ull * 2;
while ( GetTimeBase() < end );
printf("Irritating L1 on core %d ...\n", irritatorThread);
uint64_t inject =
L1P_ESR_err_reload_ecc_x2 |
//L1P_ESR_err_si_ecc |
//L1P_ESR_err_reload_ecc_ue_x2 |
0 ;
printf("injecting %lx\n", inject);
out64_sync((void *)L1P_ESR_INJ_DCR(ProcessorCoreID()), inject );
ppc_msync();
out64_sync((void *)L1P_ESR_INJ_DCR(ProcessorCoreID()), 0 );
ppc_msync();
}
if ( fwext_strcmp("L2",testId) == 0 ) {
uint64_t inject = L2_DCR__L2_INTERRUPT_STATE__DIRB_UE_set(1);
unsigned slice = fwext_strtoul( l2Slice, 0, 0 );
DCRWritePriv( L2_DCR( slice, L2_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("L2_Correctable",testId) == 0 ) {
int II;
for ( II=0; II < 111101; II++ ) {
//uint64_t inject = L2_DCR__L2_INTERRUPT_STATE__DIRB_CE_set(1);
uint64_t inject = L2_DCR__L2_INTERRUPT_STATE__EDR_CE_set(1);
unsigned slice = fwext_strtoul( l2Slice, 0, 0 );
DCRWritePriv( L2_DCR( slice, L2_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
DCRWritePriv( L2_DCR( slice, L2_INTERRUPT_STATE__FORCE ), 0 );
ppc_msync();
}
printf("Issued %d L2 CEs!\n", II);
}
if ( fwext_strcmp("L2CTR",testId) == 0 ) {
uint64_t inject = L2_COUNTER_DCR__L2_INTERRUPT_STATE__BDRY_PAR_ERR_set(1);
unsigned counter = fwext_strtoul( l2Slice, 0, 0 );
DCRWritePriv( L2_COUNTER_DCR( counter, L2_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("L2Central",testId) == 0 ) {
uint64_t inject = L2_CENTRAL_DCR__L2_INTERRUPT_STATE__ECC_UE_set(1);
DCRWritePriv( L2_CENTRAL_DCR( L2_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("Msgc",testId) == 0 ) {
uint64_t inject = MS_GENCT_DCR__L2_INTERRUPT_STATE__TIMEOUT_E_set(1);
DCRWritePriv( MS_GENCT_DCR( L2_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("MU",testId) == 0 ) {
// A fatal with simple intinfo:
uint64_t inject = MU_DCR__RME_INTERRUPTS0__RME_ERR7_set(1);
DCRWritePriv( MU_DCR( RME_INTERRUPTS0__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("MU_Correctable",testId) == 0 ) {
// Force a correctable error
uint64_t inject = MU_DCR__IMU_ECC_INTERRUPTS__IMU_ECC_CE1_set(1);
DCRWritePriv( MU_DCR( IMU_ECC_INTERRUPTS__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("ND",testId) == 0 ) {
// A fatal with simple intinfo:
uint64_t inject = ND_RESE_DCR__RESE_INTERRUPTS__LOCAL_RING_set(1);
DCRWritePriv( ND_RESE_DCR( 7, RESE_INTERRUPTS__FORCE ), inject );
ppc_msync();
//fwext_getFwInterface()->deprecated.backdoorTest(0);
}
if ( fwext_strcmp("PCIe",testId) == 0 ) {
ppc_msync();
uint64_t inject = PE_DCR__PCIE_INTERRUPT_STATE__CFG_PERR_set(1);
DCRWritePriv( PE_DCR( PCIE_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("SerDes0",testId) == 0 ) {
uint64_t inject = SERDES_LEFT_DCR__SERDES_INTERRUPT_STATE__A_PLLA_LOCK_LOST_set(1);
DCRWritePriv( SERDES_LEFT_DCR( SERDES_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("SerDes1",testId) == 0 ) {
#if 0
// simulation of issue 1811
DCRWritePriv( SERDES_RIGHT_DCR(SERDES_INTERRUPT_STATE_CONTROL_HIGH), SERDES_RIGHT_DCR__SERDES_INTERRUPT_STATE_CONTROL_HIGH__D_PLLA_LOCK_LOST_set(2) );
ppc_msync();
#endif
uint64_t inject = SERDES_RIGHT_DCR__SERDES_INTERRUPT_STATE__D_PLLA_LOCK_LOST_set(1);
printf("inject->%016lX\n", inject);
DCRWritePriv( SERDES_RIGHT_DCR( SERDES_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
if ( fwext_strcmp("TestInt",testId) == 0 ) {
uint64_t inject = TESTINT_DCR__TI_INTERRUPT_STATE__INT_PARITY_ERROR_set(1);
DCRWritePriv( TESTINT_DCR( TI_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
#ifdef TESTUPC
#define UPC_C_MMIO ((upc_c_dcr_t*)(PHYMAP_MINADDR_UPC | PHYMAP_PRIVILEGEDOFFSET))
{
UPC_C_MMIO->upc_c_interrupt_state__force =
UPC_C_DCR__UPC_C_INTERRUPT_STATE__PRING_ERROR_set(1); // An error was detected on the Processor/L2 UPC Daisy Chain
ppc_msync();
}
#endif
#ifdef TESTWakeup
{
uint64_t inject = _DCR__CLOCKSTOP_INTERRUPT_STATE__STOPPED_set(1);
DCRWritePriv( _DCR( CLOCKSTOP_INTERRUPT_STATE__FORCE ), inject );
ppc_msync();
}
#endif
}
}
else {
if ( fwext_strcmp("L1PBug",testId) == 0 ) {
if ( ( ProcessorID() % 4 ) == 0 ) {
uint64_t end = GetTimeBase() + 1600ull * 1000ull * 1000ull * 10;
while ( GetTimeBase() < end ) {
uint64_t esr = in64( (uint64_t*)L1P_ESR );
out64_sync((void *)L1P_ESR, ~esr );
}
//printf( "shutting down ...\n");
}
}
}
fwext_barrier( &barrier, N );
fwext_barrier( &barrier, N );
exit(0);
}
