void pci_read_config(bdf_addr_t address, uint32_t *confmem)
{
unsigned loop;
if (!confmem) {
return;
}
address &= PCI_CONFIG_BDF_MASK;
address |= (1<<31);
out_dword(PCI_CONFIG_ADDRESS, address);
confmem[0] = in_dword(PCI_CONFIG_DATA);
/*
* there is no such thing as a VendorID equal to 0xFFFF,
* nor a DeviceID equal to 0xFFFF.
* So it means the device is not present.
* fill the buffer with 0xFF to stay on the safe side.
*/
if (0xFFFFFFFFUL == confmem[0]) {
memset(confmem + 1, 0xFF, sizeof(confmem)-4);
return;
}
address += 4;
for (loop = 1; loop < PCI_HEADER_SIZE_REGS; loop++, address+=4) {
out_dword(PCI_CONFIG_ADDRESS, address);
confmem[loop] = in_dword(PCI_CONFIG_DATA);
}
}
static void start_io_operation(const struct dma_io_data *data)
{
uint8_t cmd = data->cmd;
uint8_t bm_cmd = data->bm_cmd;
uint16_t count = data->sector_count;
uint64_t start = data->start_sector;
struct drive *d = &drives[data->drive];
struct prd_entry *prdt_address = &prdt[d->bus];
/* Prepare PRDT */
prdt_address->physical_addr = data->buffer;
prdt_address->size = data->size;
prdt_address->reserved = 0x8000; /* Set it as the last PRD entry */
/* Stop DMA first, and then send command. */
out_byte(d->bm_reg + IDE_BUS_MASTER_CMD, 0x0);
out_dword(d->bm_reg + IDE_BUS_MASTER_PRDT, CAST_VIRTUAL_TO_PHYSICAL(prdt_address));
out_byte(d->bm_reg + IDE_BUS_MASTER_CMD, bm_cmd | 0x1);
if (d->lba48)
{
out_byte(d->base_reg + IDE_REGISTER_DRIVE_SELECT, 0x40 | (d->drive << 4));
out_byte(d->base_reg + IDE_REGISTER_SECTOR_COUNT, (count >> 8) & 0xff);
out_byte(d->base_reg + IDE_REGISTER_LBA_LO, (start >> 24) & 0xff);
out_byte(d->base_reg + IDE_REGISTER_LBA_MID, (start >> 32) & 0xff);
out_byte(d->base_reg + IDE_REGISTER_LBA_HI, (start >> 40) & 0xff);
out_byte(d->base_reg + IDE_REGISTER_SECTOR_COUNT, count & 0xff);
out_byte(d->base_reg + IDE_REGISTER_LBA_LO, start & 0xff);
out_byte(d->base_reg + IDE_REGISTER_LBA_MID, (start >> 8) & 0xff);
out_byte(d->base_reg + IDE_REGISTER_LBA_HI, (start >> 16) & 0xff);
}
BOOL pci_bus_check()
{
unsigned tmp;
BOOL retcode = FALSE;
out_byte(PCI_CONFIG_ADDRESS + 3, 1);
tmp = in_dword(PCI_CONFIG_ADDRESS);
out_dword(PCI_CONFIG_ADDRESS, (unsigned)(1<<31));
if (in_dword(PCI_CONFIG_ADDRESS) == (unsigned)(1<<31)) {
retcode = TRUE;
}
out_dword(PCI_CONFIG_ADDRESS, tmp);
return (retcode);
}
void pci_write_config(bdf_addr_t address, const uint32_t *confmem)
{
unsigned loop;
if (!confmem) {
return;
}
address &= PCI_CONFIG_BDF_MASK;
address |= (1<<31);
for (loop = 0; loop < 64; loop++, address+=4) {
out_dword(PCI_CONFIG_ADDRESS, address);
out_dword(PCI_CONFIG_DATA, confmem[loop]);
}
}
void pci_write_config_reg32(bdf_addr_t address,
unsigned offset,
const uint32_t value)
{
pci_config_space_set_addr(address, offset);
out_dword(PCI_CONFIG_DATA, value);
}
static inline void
pci_config_space_set_addr (bdf_addr_t address, unsigned offset)
{
address &= PCI_CONFIG_BDF_MASK;
address += ((offset & ~3) & (PCI_HEADER_SIZE_REGS -1));
address |= (1<<31);
out_dword(PCI_CONFIG_ADDRESS, address);
}
PRIVATE void init_dma()
{
PCI dma[8];
int i,j;
printl("Getting BUS :0 DEV:0 FUNC: 0\n");
u32* tmp=(u32*)&dma[0];
for(i=0;i<PCI_FUNC_NR;i++)
{
u32* tmp=(u32*)&dma[i];
for(j=0;j<PCI_REG_NR;j++)
{
out_dword(PCI_CONF_ADDR,MAKE_PCI_CONF(0,0,i,j));
tmp[j]=in_dword(PCI_CONF_DATA);
}
if(i==0)
{
//break;
if(!(dma[0].conf_head&0x80))
{
break;
}
}
}
tmp=(u32*)&dma[0];
for(i=0;i<16;i++)
{
printf("%d: %x\n",i,tmp[i]);
}
printl("BUS :0 DEV:0 FUNC: 0\n");
printl("BASE_TYPE:%x \nSUB_TYPE:%x\n",dma[0].base_type,dma[0].sub_type);
}
static __inline void CoreSightLock(uint32 virtAddr)
{
virtAddr=virtAddr+CORESIGHT_LOCK_OFFSET;
out_dword(virtAddr,0x0);
}
static __inline void HWEvent_SetReg(uint32 virtAddr,uint32 regAddr,uint32
regValue)
{
virtAddr=virtAddr+HWIO_PAGE_OFFSET(regAddr);//mapping to a 4K aligned virtual page
out_dword(virtAddr,regValue);
}
