/* mode 13h functions */
static void m13h_setmode( void )
{
int i;
uint8_t regs[] =
{
/* MISC */
0x63,
/* SEQ */
0x03, 0x01, 0x0F, 0x00, 0x0E,
/* CRTC */
0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0xBF, 0x1F,
0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x9C, 0x0E, 0x8F, 0x28, 0x40, 0x96, 0xB9, 0xA3,
0xFF,
/* GC */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
/* AC */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
};
int rg = 0;
uint8_t reg;
/* MISC */
outport_b(VGA_MSCOUTW,regs[rg]);
rg++;
/* SEQ */
for ( i=0; i<5; i++ )
setvgareg(VGA_SEQ,i,regs[rg++]);
/* need to unlock CRTC here */
reg = getvgareg(VGA_CRTC,VGA_CRTC_EHBLNK);
reg |= 0x80;
setvgareg(VGA_CRTC,VGA_CRTC_EHBLNK,reg);
reg = getvgareg(VGA_CRTC,VGA_CRTC_VTRTEN);
reg &= ~0x80;
setvgareg(VGA_CRTC,VGA_CRTC_VTRTEN,reg);
/* keep 'em unlocked */
regs[rg+VGA_CRTC_EHBLNK] |= 0x80;
regs[rg+VGA_CRTC_VTRTEN] &= ~0x80;
/* CRTC */
for ( i=0; i<25; i++ )
setvgareg(VGA_CRTC,i,regs[rg++]);
/* GC */
for ( i=0; i<9; i++ )
setvgareg(VGA_GC,i,regs[rg++]);
/* AC */
for ( i=0; i<9; i++ )
{
inport_b(VGA_INSTAT1);
outport_b(VGA_AC_I,i);
outport_b(VGA_AC_W,regs[rg++]);
}
/* unblank display and lock palette */
inport_b(VGA_INSTAT1);
outport_b(VGA_AC_I,0x20);
/* clear video memory */
memset(m13h_mem,0x00,64000);
}
/* get the value of a VGA register */
uint8_t getvgareg( uint16_t port, uint8_t index )
{
uint8_t save = inport_b(port);
outport_b(port,index);
uint8_t data = inport_b(port+1);
outport_b(port,save);
return data;
}
static void m13h_setpal( uint8_t* pal )
{
int i;
for ( i=0; i<256; i++ )
{
outport_b(VGA_DAC_ADWM,i);
outport_b(VGA_DAC_DATA,(*pal++));
outport_b(VGA_DAC_DATA,(*pal++));
outport_b(VGA_DAC_DATA,(*pal++));
}
}
static void m13h_getpal( uint8_t* pal )
{
int i;
for ( i=0; i<256; i++ )
{
outport_b(VGA_DAC_ADRM,i);
*(pal++) = inport_b(VGA_DAC_DATA);
*(pal++) = inport_b(VGA_DAC_DATA);
*(pal++) = inport_b(VGA_DAC_DATA);
}
}
static INLINE
GrColor readpixel(GrFrame *c,int x,int y)
{
char *ptr;
unsigned mask, pixval;
GRX_ENTER();
ptr = &SCRN->gc_baseaddr[0][FOFS(x,y,SCRN->gc_lineoffset)];
mask= 0x80U >> (x &= 7);
setup_far_selector(SCRN->gc_selector);
outport_w(VGA_GR_CTRL_PORT,((3 << 8) | VGA_RD_PLANE_SEL_REG));
pixval = (peek_b_f(ptr) & mask);
outport_b(VGA_GR_CTRL_DATA,2);
pixval = (peek_b_f(ptr) & mask) | (pixval << 1);
outport_b(VGA_GR_CTRL_DATA,1);
pixval = (peek_b_f(ptr) & mask) | (pixval << 1);
outport_b(VGA_GR_CTRL_DATA,0);
pixval = (peek_b_f(ptr) & mask) | (pixval << 1);
lastcolor = (-1L);
GRX_RETURN((GrColor)(pixval >> (7 - x)));
}
void serial_on( uint16_t dev )
{
outport_b(dev+1,0x00);
outport_b(dev+3,0x80);
outport_b(dev,0x03);
outport_b(dev+1,0x00);
outport_b(dev+3,0x03);
outport_b(dev+2,0xC7);
outport_b(dev+4,0x0B);
}
void serial_chr( uint16_t dev, char c )
{
while ( serial_transmit_empty(dev) == 0 );
outport_b(dev,c);
}
/* start up IDT */
static void init_idt( void )
{
idt_ptr.limit = sizeof(idt_entry_t)*256-1;
idt_ptr.base = (uint32_t)&idt_ents;
/* we have to zero everything out */
memset(&idt_ents[0],0,sizeof(idt_entry_t)*256);
irq_clearhandlers();
isr_clearhandlers();
/* remap PICs so IRQs use IDT gates 32-47 */
/* this code will look confusing, sorry for the inconvenience */
printk(" Remapping PIC (IRQs on IDT gates 32-47)\n");
outport_b(0x20,0x11);
outport_b(0xA0,0x11);
outport_b(0x21,0x20);
outport_b(0xA1,0x28);
outport_b(0x21,0x04);
outport_b(0xA1,0x02);
outport_b(0x21,0x01);
outport_b(0xA1,0x01);
outport_b(0x21,0x00);
outport_b(0xA1,0x00);
/* setting up gates */
/* ISRs */
printk(" Interrupt Service Routines\n");
idt_setgate(0,(uint32_t)isr0,0x08,0x8E);
idt_setgate(1,(uint32_t)isr1,0x08,0x8E);
idt_setgate(2,(uint32_t)isr2,0x08,0x8E);
idt_setgate(3,(uint32_t)isr3,0x08,0x8E);
idt_setgate(4,(uint32_t)isr4,0x08,0x8E);
idt_setgate(5,(uint32_t)isr5,0x08,0x8E);
idt_setgate(6,(uint32_t)isr6,0x08,0x8E);
idt_setgate(7,(uint32_t)isr7,0x08,0x8E);
idt_setgate(8,(uint32_t)isr8,0x08,0x8E);
idt_setgate(9,(uint32_t)isr9,0x08,0x8E);
idt_setgate(10,(uint32_t)isr10,0x08,0x8E);
idt_setgate(11,(uint32_t)isr11,0x08,0x8E);
idt_setgate(12,(uint32_t)isr12,0x08,0x8E);
idt_setgate(13,(uint32_t)isr13,0x08,0x8E);
idt_setgate(14,(uint32_t)isr14,0x08,0x8E);
idt_setgate(15,(uint32_t)isr15,0x08,0x8E);
idt_setgate(16,(uint32_t)isr16,0x08,0x8E);
idt_setgate(17,(uint32_t)isr17,0x08,0x8E);
idt_setgate(18,(uint32_t)isr18,0x08,0x8E);
idt_setgate(19,(uint32_t)isr19,0x08,0x8E);
idt_setgate(20,(uint32_t)isr20,0x08,0x8E);
idt_setgate(21,(uint32_t)isr21,0x08,0x8E);
idt_setgate(22,(uint32_t)isr22,0x08,0x8E);
idt_setgate(23,(uint32_t)isr23,0x08,0x8E);
idt_setgate(24,(uint32_t)isr24,0x08,0x8E);
idt_setgate(25,(uint32_t)isr25,0x08,0x8E);
idt_setgate(26,(uint32_t)isr26,0x08,0x8E);
idt_setgate(27,(uint32_t)isr27,0x08,0x8E);
idt_setgate(28,(uint32_t)isr28,0x08,0x8E);
idt_setgate(29,(uint32_t)isr29,0x08,0x8E);
idt_setgate(30,(uint32_t)isr30,0x08,0x8E);
idt_setgate(31,(uint32_t)isr31,0x08,0x8E);
/* IRQs */
printk(" Interrupt Requests\n");
idt_setgate(32,(uint32_t)irq0,0x08,0x8E);
idt_setgate(33,(uint32_t)irq1,0x08,0x8E);
idt_setgate(34,(uint32_t)irq2,0x08,0x8E);
idt_setgate(35,(uint32_t)irq3,0x08,0x8E);
idt_setgate(36,(uint32_t)irq4,0x08,0x8E);
idt_setgate(37,(uint32_t)irq5,0x08,0x8E);
idt_setgate(38,(uint32_t)irq6,0x08,0x8E);
idt_setgate(39,(uint32_t)irq7,0x08,0x8E);
idt_setgate(40,(uint32_t)irq8,0x08,0x8E);
idt_setgate(41,(uint32_t)irq9,0x08,0x8E);
idt_setgate(42,(uint32_t)irq10,0x08,0x8E);
idt_setgate(43,(uint32_t)irq11,0x08,0x8E);
idt_setgate(44,(uint32_t)irq12,0x08,0x8E);
idt_setgate(45,(uint32_t)irq13,0x08,0x8E);
idt_setgate(46,(uint32_t)irq14,0x08,0x8E);
idt_setgate(47,(uint32_t)irq15,0x08,0x8E);
/* Syscalls */
printk(" Syscalls\n");
idt_setgate(128,(uint32_t)isr128,0x08,0x8E);
/* flush~ */
printk(" Flushing IDT\n");
idt_flush((uint32_t)&idt_ptr);
}
