/*
addr: memory address
len: byte count
buf: buffer to put the read back data
*/
int usiRead(UINT32 addr, UINT32 len, UINT8 *buf)
{
int volatile i;
outpw(REG_USI_SSR, inpw(REG_USI_SSR) | 0x01); // CS0
// read command
outpw(REG_USI_Tx0, 03);
usiTxLen(0, 8);
usiActive();
// address
outpw(REG_USI_Tx0, addr);
usiTxLen(0, 24);
usiActive();
// data
for (i=0; i<len; i++)
{
outpw(REG_USI_Tx0, 0xff);
usiTxLen(0, 8);
usiActive();
*buf++ = inpw(REG_USI_Rx0) & 0xff;
}
outpw(REG_USI_SSR, inpw(REG_USI_SSR) & 0xfe); // CS0
return USI_NO_ERR;
}
VOID NEAR IORBDone (NPA npA)
{
PIORB pIORB = npA->pIORB;
/*
** If a removable media has changed then ignore any error that
** may have occured and report the changed media error.
** Report media changed only once.
*/
DISABLE
pIORB->ErrorCode = npA->IORBError;
pIORB->Status = npA->IORBStatus | IORB_DONE;
#if PCITRACER
outpw (TRPORT+2, 0x9999);
outpw (TRPORT+2, pIORB->Status);
outpw (TRPORT+2, pIORB->ErrorCode);
#endif
npA->pIORB = 0;
ENABLE
if (pIORB->RequestControl & IORB_ASYNC_POST) pIORB->NotifyAddress (pIORB);
#if PCITRACER
outpw (TRPORT, 0xDEEE);
#endif
}
/******************************************************************************
FUNCTION void alloc_task()
RETURNS None.
PARAMETERS None.
PURPOSE
Allocate channels.
WRITTEN BY
Takuji Ebinuma.
******************************************************************************/
void alloc_task()
{
int i,k,already_allocated;
static int sv = 26;//15;//22;//12;//15;//26;//0; //[Art] to reduce acquisition time!
int sv_index[2] = {27, 17};
///while (1) {
for (i=0; i<MAX_CHANNELS; i++) {
if (CH[i].prn==IDLE) {
CH[i].lock_status = NO_LOCK;
CH[i].pow_code = LossThresh;
CH[i].pow_carr = LossThresh;
CH[i].IP = 0;
CH[i].QP = 0;
CH[i].E= 0;
CH[i].Tau = 0;
CH[i].half_chip_counter = 0;
CH[i].freq_bin_counter = 0;
CH[i].pull_in_time = 0;
CH[i].carr_nco = CARR_REF + CarrSrchStep*2; //[Art] to reduce acquisition time!
CH[i].code_nco = CODE_REF;
outpw((CH[i].BASE+PRN_KEY), prntaps[sv]);
///outpw((CH[i].BASE+CARR_NCO), CH[i].carr_nco);
outpw((CH[i].BASE+CARR_NCO_LOW), (CH[i].carr_nco & 0x0000ffff));
///outpw((CH[i].BASE+CARR_NCO_HIGH), ((CH[i].carr_nco & 0xffff0000)>>16));
if (CH[i].carr_nco_sign > 0 ){
outpw((CH[i].BASE+CARR_NCO_HIGH), ( ((CH[i].carr_nco & 0xffff0000)>>16) | (1<<15) )); //[Art]. (1<<15) is the sign!
} //of the NCO freq.
else {
void capClkRatio(BOOL ratio)
{
if(ratio==TRUE)
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x00100000);
else
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xffEfffff);
}
/************************
*
* hwt_stop
*
* Stop hardware timer.
*
* void hwt_stop(
* struct s_smc *smc) ;
* In
* smc - A pointer to the SMT Context structure.
* Out
* Nothing.
*
************************/
void hwt_stop(struct s_smc *smc)
{
outpw(ADDR(B2_TI_CRTL), TIM_STOP) ;
outpw(ADDR(B2_TI_CRTL), TIM_CL_IRQ) ;
smc->hw.timer_activ = FALSE ;
}
/*----------------------------------------------------------------------------------------
函数名: icTimerInit
参数:
None
返回值:
None
描述:
对所选择的定时器进行硬件初始化
----------------------------------------------------------------------------------------*/
void icTimerInit(void)
{
#if USE_TIMER == 0
// 开定时器0
SYSCLK->CLKSEL1.TMR0_S = 4; // 选择48M计时频率
SYSCLK->APBCLK.TMR0_EN = 1; // 开时钟
outpw((uint32_t)&TIMER0->TCSR ,0 ); // 关闭定时器
TIMER0->TISR.TIF = 1; // 清除中断标志
TIMER0->TCMPR = 49152; // 计数10 频率49.152MHz 得1KHZ
TIMER0->TCSR.PRESCALE = 0;
outpw((uint32_t)&TIMER0->TCSR, (uint32_t)((1 << 30) | (1 << 29) | (1 << 27))); // 使能定时器，使能中断，模式01周期重复计数
NVIC_EnableIRQ(TMR0_IRQn);
#else
// 开定时器1
SYSCLK->CLKSEL1.TMR1_S = 0; // 选择10K计时频率
SYSCLK->APBCLK.TMR1_EN =1; // 开时钟
outpw((uint32_t)&TIMER1->TCSR ,0 ); // 关闭定时器
TIMER1->TISR.TIF = 1; // 清除中断标志
TIMER1->TCMPR = 10; // 计数10 频率10KHZ 得1KHZ
TIMER1->TCSR.PRESCALE = 0;
outpw((uint32_t)&TIMER1->TCSR, (uint32_t)((1 << 30) | (1 << 29) | (1 << 27))); // 使能定时器，使能中断，模式01周期重复计数
NVIC_EnableIRQ(TMR1_IRQn);
#endif
}
static int plc_send_bits(struct s_smc *smc, struct s_phy *phy, int len)
{
int np = phy->np ; /* PHY index */
int n ;
int i ;
SK_UNUSED(smc) ;
/* create bit vector */
for (i = len-1,n = 0 ; i >= 0 ; i--) {
n = (n<<1) | phy->t_val[phy->bitn+i] ;
}
if (inpw(PLC(np,PL_STATUS_B)) & PL_PCM_SIGNAL) {
#if 0
printf("PL_PCM_SIGNAL is set\n") ;
#endif
return 1;
}
/* write bit[n] & length = 1 to regs */
outpw(PLC(np,PL_VECTOR_LEN),len-1) ; /* len=nr-1 */
outpw(PLC(np,PL_XMIT_VECTOR),n) ;
#ifdef DEBUG
#if 1
#ifdef DEBUG_BRD
if (smc->debug.d_plc & 0x80)
#else
if (debug.d_plc & 0x80)
#endif
printf("SIGNALING bit %d .. %d\n",phy->bitn,phy->bitn+len-1) ;
#endif
#endif
return 0;
}
void init_psg(int dacAdjust )
{
#ifndef WINDOWS_NT
word indexPort, dataPort, i;
#else
PUCHAR indexPort, dataPort;
word i;
#endif
indexPort = encBaseAddr + PSG_ADDR_CTRL;
dataPort = encBaseAddr + PSG_DATA_CTRL;
for (i = 0; i < PSG_NBRE_REG - 3; i++) /* 3 for 3 registers RO */
{
outpw (indexPort, i);
#ifndef WINDOWS_NT
if (i == 0x0a) /* Ajustement dependant du DAC */
outpw (dataPort, ptrEncReg->psgReg[i] + dacAdjust);
else
outpw (dataPort, ptrEncReg->psgReg[i]);
#else
if (i == 0x0a) /* Ajustement dependant du DAC */
outpw ((PUSHORT)dataPort, (USHORT)(ptrEncReg->psgReg[i] + dacAdjust));
else
outpw ((PUSHORT)dataPort, (USHORT)(ptrEncReg->psgReg[i]));
#endif
}
}
int usiInitDevice(UINT32 clock_by_MHz)
{
int volatile rate, id;
// multi PAD control
outpw(REG_PADC0, inpw(REG_PADC0)|0x40);
/* init SPI interface */
rate = clock_by_MHz / 40; // access SPIFlash 20MHz
if (((clock_by_MHz % 40) == 0) && (rate != 1))
rate = rate - 1;
outpw(REG_USI_DIVIDER, rate);
id = usiReadID();
// sysprintf("id [0x%x]\n", id);
if (id == 0xef12)
return 1024; // 512KB, 1024 sectors(for file system, 1 sector=512 byte)
else if (id == 0xef13)
return 2048; // 1MB, 2048 sectors(for file system, 1 sector=512 byte)
else if (id == 0xef14)
return 4096; // 2MB, 4096 sectors
else if (id == 0xef15)
return 8192; // 4MB, 8192 sectors
else
return USI_ERR_DEVICE;
return USI_NO_ERR;
}
//*****************************************************************************
//
//! \brief ADC Interrupt Service Routine.According to the interrupt flags to call
//! the corresponding callback function.
//!
//! \param None
//!
//! \return None
//
//*****************************************************************************
void ADC_IRQHandler(void)
{
if(ADC->SR_BITS.ADF==1)
{
if(g_ptADCCallBack)
g_ptADCCallBack(g_pu32UserData[0]);
/* clear the A/D conversion flag */
/* "ADC->ADSR.ADF = 1;" is not recommended. It may clear CMPF0 and CMPF1. */
outpw(ADC_ADSR, (inpw(ADC_ADSR)&(~0x7))|0x1);
}
if(ADC->SR_BITS.CMPF0==1)
{
if(g_ptADCMP0CallBack)
g_ptADCMP0CallBack(g_pu32UserData[1]);
/* clear the A/D compare flag 0 */
/* "ADC->ADSR.CMPF0 = 1;" is not recommended. It may clear ADF and CMPF1. */
outpw(ADC_ADSR, (inpw(ADC_ADSR)&(~0x7))|0x2);
}
if(ADC->SR_BITS.CMPF1==1)
{
if(g_ptADCMP1CallBack)
g_ptADCMP1CallBack(g_pu32UserData[2]);
/* clear the A/D compare flag 1 */
/* "ADC->ADSR.CMPF1 = 1;" is not recommended. It may clear ADF and CMPF0. */
outpw(ADC_ADSR, (inpw(ADC_ADSR)&(~0x7))|0x4);
}
}
int usiEraseSector(UINT32 addr, UINT32 secCount)
{
int volatile i;
for (i=0; i<secCount; i++)
{
usiWriteEnable();
outpw(REG_USI_SSR, inpw(REG_USI_SSR) | 0x01); // CS0
// erase command
outpw(REG_USI_Tx0, 0xd8);
usiTxLen(0, 8);
usiActive();
// address
outpw(REG_USI_Tx0, addr+i*0x10000); // 1 sector = 64KB
usiTxLen(0, 24);
usiActive();
outpw(REG_USI_SSR, inpw(REG_USI_SSR) & 0xfe); // CS0
// check status
usiCheckBusy();
}
return USI_NO_ERR;
}
UINT16 usiReadID()
{
UINT16 volatile id;
outpw(REG_USI_SSR, inpw(REG_USI_SSR) | 0x01); // CS0
// command 8 bit
outpw(REG_USI_Tx0, 0x90);
usiTxLen(0, 8);
usiActive();
// address 24 bit
outpw(REG_USI_Tx0, 0x000000);
usiTxLen(0, 24);
usiActive();
// data 16 bit
outpw(REG_USI_Tx0, 0xffff);
usiTxLen(0, 16);
usiActive();
id = inpw(REG_USI_Rx0) & 0xffff;
outpw(REG_USI_SSR, inpw(REG_USI_SSR) & 0xfe); // CS0
return id;
}
void led_yellow_set_state( uint8_t state )
{
if (state)
outpw(P1DATA, (inpw(P1DATA) & ~0x1800) & ~0x200);
else
outpw(P1DATA, (inpw(P1DATA) & ~0x1800) | 0x200);
}
/**
* @brief This function reset the i2c interface and enable interrupt.
* @param[in] param is interface number.
* @return open status.
* @retval 0 success.
* @retval I2C_ERR_BUSY Interface already opened.
* @retval I2C_ERR_NODEV Interface number out of range.
*/
int32_t i2cOpen(PVOID param)
{
i2c_dev *dev;
if( (uint32_t)param >= I2C_NUMBER)
return I2C_ERR_NODEV;
dev = (i2c_dev *)((uint32_t)&i2c_device[(uint32_t)param] );
if( dev->openflag != 0 ) /* a card slot can open only once */
return(I2C_ERR_BUSY);
/* Enable engine clock */
if((uint32_t)param == 0)
outpw(REG_CLK_PCLKEN1, inpw(REG_CLK_PCLKEN1) | 0x1);
else
outpw(REG_CLK_PCLKEN1, inpw(REG_CLK_PCLKEN1) | 0x2);
memset(dev, 0, sizeof(i2c_dev));
dev->base = ((uint32_t)param) ? I2C1_BA : I2C0_BA;
_i2cReset(dev);
dev->openflag = 1;
return 0;
}
/*************************************************************************
module :[周波数チェック]
function :[周波数チェック]
return :[チェック結果]
common :[]
condition :[
機種 ０：ポプラＢ １：
]
comment :[]
machine :[SH7043]
language :[SHC]
keyword :[CHK]
date :[1997/06/24]
author :[山口]
*************************************************************************/
void CheckClock( UBYTE Machine ) /* 機種 */
{
UWORD tmp; /*テンポラリー*/
UWORD i; /*ループ*/
/* 周波数チェック（以下の配列定数は配列０がポプラＢ、配列１が？） */
UDWORD clock_port[] = {RTC_PORT,0xC203C0}; /* 周波数チェックポート*/
UWORD clock_CE_bit[] = {0x0001,0x0001}; /* 周波数チェックＣＥビット */
UWORD clock_IO_bit[] = {0x0004,0x0004}; /* 周波数チェックＩＯビット 0:ON(W) 1:OFF(R) */
/* UWORD clock_IO_bit[] = {IO_BIT_RTC_IO,0x0004}; /@ 周波数チェックＩＯビット 1997/11/13 By T.Yamaguchi */
/*---------------------------------------------------------------------
** SAKAKIでは、ATLANTAに対して、IO_BIT_RTC_IOの論理が逆転しています。
** チェッカー作成時には、変更が必要です。まだ変更していません。
** 1998/07/10 H.Yoshikawa
*/
/** ＣＥ，ＩＯをＬｏｗにセット */
tmp = clock_IO_bit[Machine]; /** ＣＥ，ＩＯをＯＦＦ */
outpw(clock_port[Machine],tmp); /** 周波数チェックポート出力 */
/** ＣＥ、ＩＯ制御 */
tmp |= clock_CE_bit[Machine]; /** ＣＥ ON */
outpw(clock_port[Machine],tmp); /** 周波数チェックポート出力 */
for ( i = 0; i < 1801; i++ ) {} /** ５〜６ｍｓウエイト */
for ( i = 0; i < 5; i++ ) {
tmp &= (~clock_IO_bit[Machine]);/** ＩＯ ON */
outpw(clock_port[Machine],tmp); /** 周波数チェックポート出力 */
tmp |= clock_IO_bit[Machine]; /** ＩＯ OFF */
outpw(clock_port[Machine],tmp); /** 周波数チェックポート出力 */
}
}
void i2cEnableInterrupt (BOOL bIsEnableINT)
{ UINT32 regdata;
//k09144-1 sysSetInterruptType(IRQ_FI2C, LOW_LEVEL_SENSITIVE); //k08184-1
#ifdef ECOS
if (bIsEnableINT) // enable I2C interrupt
{ cyg_interrupt_create(IRQ_FI2C, 1, 0, Int_Handler_FastI2C, NULL,
&int_handle_I2C, &int_holder_I2C);
cyg_interrupt_attach(int_handle_I2C);
cyg_interrupt_unmask(IRQ_FI2C);
}
else
{ cyg_interrupt_mask(IRQ_FI2C);
cyg_interrupt_detach(int_handle_I2C);
}
#else
sysInstallISR(IRQ_LEVEL_1, IRQ_FI2C, (PVOID)Int_Handler_FastI2C); //IRQ_FI2C=24
if (bIsEnableINT) sysEnableInterrupt(IRQ_FI2C); //k03224-1
else sysDisableInterrupt (IRQ_FI2C);
#endif
_i2c_bINT_EN=bIsEnableINT; //k07195-1
//enable sensor I2C engine's interrupt
if (bIsEnableINT)
{ regdata=inpw (REG_FastSerialBusCR)|0x02;
outpw (REG_FastSerialBusCR,regdata);
}
//To clear interrupt status
regdata=inpw (REG_FastSerialBusStatus)|0x03;
outpw (REG_FastSerialBusStatus,regdata);
/* enable I2C interrupt */
//k08204-1 sysEnableInterrupt(IRQ_FI2C); //k03224-1
}
void led_green_set_state( uint8_t state )
{
outpw(ETHPPPTR,0x114); // –егистр SelfCTL CS8900A
if(state)
outpw(ETHPPDATAL, inpw(ETHPPDATAL) | 0x4000);
else
outpw(ETHPPDATAL, inpw(ETHPPDATAL) & ~0x4000);
}
void setVisibleStart(unsigned offset)
{
visStart = offset;
outpw(CRTC_ADDR, 0x0C); /* set high byte */
outpw(CRTC_ADDR+1, visStart >> 8);
outpw(CRTC_ADDR, 0x0D); /* set low byte */
outpw(CRTC_ADDR+1, visStart & 0xff);
}
void capPacketSticker(T_CAP_SET* ptCapSet)
{
BOOL bIsPacSticker;
bIsPacSticker = ptCapSet->bIsPacSticker;
if(bIsPacSticker==TRUE)//Enable packet overlay ?
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x1000);
else
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xffffefff);
}
void capPlanarSticker(T_CAP_SET* ptCapSet)
{
BOOL bIsPlaSticker;
bIsPlaSticker = ptCapSet->bIsPlaSticker;
if(bIsPlaSticker==TRUE)//Enable plabar overlay ?
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x0800);
else
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xfffff7ff);
}
void capPlanarOut(T_CAP_SET* ptCapSet)
{
BOOL bIsPlaOut;
bIsPlaOut = ptCapSet->bIsPlaEnable;
if(bIsPlaOut)
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x00000200);
else
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xfffffdff);
}
static void mdio_write(u8_t addr, u8_t reg, u16_t val)
{
outpw(REG_EMAC1_MIID, val);
outpw(REG_EMAC1_MIIDA, (addr << 8) | reg | 0xB0000);
while (inpw(REG_EMAC1_MIIDA) & 0x20000); // wait busy flag clear
}
void capPacketOut(T_CAP_SET* ptCapSet)
{
BOOL bIsPacOut;
bIsPacOut = ptCapSet->bIsPacEnable;
if(bIsPacOut)
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x00000100);
else
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xfffffeff);
}
/**
* @brief Enter initialization mode
* @param[in] uCAN CAN channel.
* @return None
* @details This function is used to set CAN to enter initialization mode and enable access bit timing
* register. After bit timing configuration ready, user must call CAN_LeaveInitMode()
* to leave initialization mode and lock bit timing register to let new configuration
* take effect.
*/
void CAN_EnterInitMode(UINT32 uCAN)
{
UINT32 uOffset = uCAN * CAN_OFFSET;
UINT32 uRegAddress;
uRegAddress = REG_CAN0_CON + uOffset;
outpw(uRegAddress, inpw(uRegAddress)|CAN_CON_INIT_Msk);
outpw(uRegAddress, inpw(uRegAddress)|CAN_CON_CCE_Msk);
}
//*****************************************************************************
//
//! \brief Enable the interrupt function of the specified GPIO pin. Except for
//! Port3-2 and Port3-2 pins are for external interrupt used.
//!
//! \param port E_DRVGPIO_PORT, specify GPIO port. It could be E_PORT0,
//! E_PORT1, E_PORT2, E_PORT3 and E_PORT4.
//!
//! \param pin Specify pin of the GPIO port. It could be E_PIN0, E_PIN2 ... ~
//! E_PIN7. But the Port3-2 and Port3-3 are only used for external interrupt
//! 0/1.
//!
//! \param Type E_DRVGPIO_INT_TYPE, specify the interrupt trigger type. It
//! could be E_IO_RISING, E_IO_FALLING or E_IO_BOTH_EDGE and it's meaning the
//! interrupt function enable by rising egde/high level, falling edge/low level
//! or both riging edge and falling egde. If the interrupt mode is E_MODE_LEVEL
//! and interrupt type is E_BOTH_EDGE¡Athen calling this API is ignored.
//!
//! \param Mode E_DRVGPIO_INT_MODE, specify the interrupt mode. It could be
//! E_MODE_EDGE or E_MODE_LEVEL to control the interrupt is by edge trigger or
//! by level trigger. If the interrupt mode is E_MODE_LEVEL and interrupt type
//! is E_BOTH_EDGE¡Athen calling this API is ignored.
//!
//! \return E_SUCCESS Operation successful
//! E_DRVGPIO_ARGUMENT Incorrect argument
//
//*****************************************************************************
int32_t DrvGPIO_EnableInt(E_DRVGPIO_PORT port, uint32_t pin, E_DRVGPIO_INT_TYPE Type,
E_DRVGPIO_INT_MODE Mode)
{
volatile uint32_t u32Reg = (uint32_t)((uint32_t)&PORT0->IEN + (port*PORT_OFFSET));
if ((port == E_PORT3) && ((pin == E_EINT0_PIN) || (pin == E_EINT1_PIN)))
{
//
// P32 is EINT0, P33 is EINT1. Both of them can't be assigned to gereral P3
// interrupt
//
return E_DRVGPIO_ARGUMENT;
}
//
// Configure the interrupt to be rising/falling when edge trigger or high/low
// level when level trigger
//
if (Type == E_IO_RISING)
outpw(u32Reg, inpw(u32Reg) | (1<<(pin+16)));
else if (Type == E_IO_FALLING)
outpw(u32Reg , inpw(u32Reg) | (1<<pin));
else if (Type == E_IO_BOTH_EDGE)
outpw(u32Reg , inpw(u32Reg) | (1<<pin)| (1<<(pin+16)));
else
return E_DRVGPIO_ARGUMENT;
//
// Configure to be level trigger or edge trigger
//
u32Reg = (uint32_t)((uint32_t)&PORT0->IMD + (port*PORT_OFFSET));
if (Mode == E_MODE_EDGE)
outpw(u32Reg, inpw(u32Reg) & (~(1<<pin)));
else if (Mode == E_MODE_LEVEL)
outpw(u32Reg, inpw(u32Reg) | (1<<pin));
else
return E_DRVGPIO_ARGUMENT;
//
// Configure the relative interrupt of M0
//
if ((port == E_PORT0) || (port == E_PORT1))
{
NVIC_SetPriority(GPIO_P0P1_IRQn, (1<<__NVIC_PRIO_BITS) - 2);
NVIC_EnableIRQ(GPIO_P0P1_IRQn);
}
if ((port == E_PORT2) || (port == E_PORT3) || (port == E_PORT4))
{
NVIC_SetPriority(GPIO_P2P3P4_IRQn, (1<<__NVIC_PRIO_BITS) - 2);
NVIC_EnableIRQ(GPIO_P2P3P4_IRQn);
}
return E_SUCCESS;
}
void init_ctrl()
{
/* Enable filter */
#ifndef WINDOWS_NT
outpw (encBaseAddr + ENC_CTRL_OFFSET, ptrEncReg->boardCtrlReg | ENC_FILTER);
#else
outpw ((PUSHORT)(encBaseAddr + ENC_CTRL_OFFSET),
(USHORT)(ptrEncReg->boardCtrlReg | ENC_FILTER));
#endif
}
UCHAR getPixel_X(int x, int y)
{
/* Select the plane from which we must read the pixel color: */
outpw(GRAC_ADDR, 0x04);
outpw(GRAC_ADDR+1, x & 3);
return vga[(unsigned)(widthBytes * y) + (x / 4) + actStart];
}
/**
* @brief Switch the CAN into test mode.
* @param[in] uCAN CAN channel.
* @param[in] u8TestMask Specifies the configuration in test modes
* CAN_TEST_BASIC_Msk : Enable basic mode of test mode
* CAN_TESTR_SILENT_Msk : Enable silent mode of test mode
* CAN_TESTR_LBACK_Msk : Enable Loop Back Mode of test mode
* CAN_TESTR_TX0_Msk/CAN_TESTR_TX1_Msk: Control CAN_TX pin bit field
* @return None
* @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/
* LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user
* must call CAN_LeaveInitMode() to let the setting take effect.
*/
void CAN_EnterTestMode(UINT32 uCAN, uint8_t u8TestMask)
{
UINT32 uOffset = uCAN * CAN_OFFSET;
UINT32 uRegVal;
uRegVal = inpw(REG_CAN0_CON+uOffset);
uRegVal |= CAN_CON_TEST_Msk;
outpw((REG_CAN0_CON+uOffset), uRegVal);
outpw((REG_CAN0_TEST+uOffset), u8TestMask);
}
void capOnTheFly(T_CAP_SET* ptCapSet)
{
if(ptCapSet->pOTF->bIsOnTheFly==TRUE)
{
outpw(REG_CAPPlaYFB0StaAddr, ( (inpw(REG_CAPPlaYFB0StaAddr) & 0x00ffffff)|((UINT32)(ptCapSet->pOTF->eLine)<<24)) );
outpw(REG_CAPFuncEnable,(inpw(REG_CAPFuncEnable)|0x8000));
}
else
outpw(REG_CAPFuncEnable,(inpw(REG_CAPFuncEnable)&0xffff7fff));
}
static void speedo_resume(struct dev *dev) {
struct nic *sp = (struct nic *) dev->privdata;
long ioaddr = sp->iobase;
outpw(ioaddr + SCBCmd, SCBMaskAll);
// Start with a Tx threshold of 256 (0x..20.... 8 byte units)
sp->tx_threshold = 0x01208000;
// Set the segment registers to '0'
wait_for_cmd_done(ioaddr + SCBCmd);
if (inp(ioaddr + SCBCmd)) {
outpd(ioaddr + SCBPort, PortPartialReset);
udelay(10);
}
outpd(ioaddr + SCBPointer, 0);
inpd(ioaddr + SCBPointer); // Flush to PCI
udelay(10); // Bogus, but it avoids the bug
// Note: these next two operations can take a while
do_slow_command(dev, RxAddrLoad);
do_slow_command(dev, CUCmdBase);
// Load the statistics block and rx ring addresses
outpd(ioaddr + SCBPointer, virt2phys(&sp->lstats));
inpd(ioaddr + SCBPointer); // Flush to PCI
outp(ioaddr + SCBCmd, CUStatsAddr);
sp->lstats.done_marker = 0;
wait_for_cmd_done(ioaddr + SCBCmd);
outpd(ioaddr + SCBPointer, virt2phys(sp->rx_ringp[sp->cur_rx % RX_RING_SIZE]));
inpd(ioaddr + SCBPointer); // Flush to PCI
// Note: RxStart should complete instantly.
do_slow_command(dev, RxStart);
do_slow_command(dev, CUDumpStats);
// Fill the first command with our physical address
{
int entry = sp->cur_tx++ % TX_RING_SIZE;
struct descriptor *cur_cmd = (struct descriptor *) &sp->tx_ring[entry];
// Avoid a bug(?!) here by marking the command already completed
cur_cmd->cmd_status = (CmdSuspend | CmdIASetup) | 0xa000;
cur_cmd->link = virt2phys(&sp->tx_ring[sp->cur_tx % TX_RING_SIZE]);
memcpy(cur_cmd->params, sp->hwaddr.addr, 6);
if (sp->last_cmd) clear_suspend(sp->last_cmd);
sp->last_cmd = cur_cmd;
}
// Start the chip's Tx process and unmask interrupts
outpd(ioaddr + SCBPointer, virt2phys(&sp->tx_ring[sp->dirty_tx % TX_RING_SIZE]));
outpw(ioaddr + SCBCmd, CUStart);
}