unsigned int ddp_ovl_get_cur_addr(bool rdma_mode, int layerid )
{
if(rdma_mode)
return (DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR));
else
{
#ifdef OVL_CASCADE_SUPPORT
if(layerid<4
&&( ovl_get_status()==DDP_OVL1_STATUS_PRIMARY
|| ovl_get_status()==DDP_OVL1_STATUS_PRIMARY_RELEASING
|| ovl_get_status()==DDP_OVL1_STATUS_SUB_REQUESTING
)
)
{ //OVL 1
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_CTRL+DISP_OVL_INDEX_OFFSET+layerid* 0x20 ) & 0x1)
return (DISP_REG_GET(DISP_REG_OVL_L0_ADDR+DISP_OVL_INDEX_OFFSET+layerid * 0x20));
else
return 0;
}
else
{ //OVL 0
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_CTRL+(layerid%4)*0x20 ) & 0x1)
return (DISP_REG_GET(DISP_REG_OVL_L0_ADDR+(layerid%4)*0x20));
else
return 0;
}
#else
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_CTRL+layerid* 0x20 ) & 0x1)
return (DISP_REG_GET(DISP_REG_OVL_L0_ADDR+layerid * 0x20));
else
return 0;
#endif
}
}
void ovl_get_info(int idx, void *data)
{
int i = 0;
OVL_BASIC_STRUCT *pdata = (OVL_BASIC_STRUCT *) data;
unsigned int idx_offset = idx * DISP_OVL_INDEX_OFFSET;
unsigned int layer_off = 0;
unsigned int src_on = DISP_REG_GET(DISP_REG_OVL_SRC_CON + idx_offset);
OVL_BASIC_STRUCT *p = NULL;
memset(pdata, 0, sizeof(OVL_BASIC_STRUCT) * OVL_LAYER_NUM);
if (ovl_get_status() == DDP_OVL1_STATUS_SUB || ovl_get_status() == DDP_OVL1_STATUS_IDLE) { /* 4+4 mode */
/* idx=0; */
idx_offset = idx * DISP_OVL_INDEX_OFFSET;
src_on = DISP_REG_GET(DISP_REG_OVL_SRC_CON + idx_offset);
for (i = 0; i < OVL_LAYER_NUM_PER_OVL; i++) {
layer_off = (i % 4) * OVL_LAYER_OFFSET + idx_offset;
p = &pdata[i];
p->layer = i;
p->layer_en = src_on & (0x1 << i);
if (p->layer_en) {
p->fmt =
(unsigned int)
ovl_input_fmt(DISP_REG_GET_FIELD
(L_CON_FLD_CFMT, layer_off + DISP_REG_OVL_L0_CON),
DISP_REG_GET_FIELD(L_CON_FLD_BTSW,
layer_off +
DISP_REG_OVL_L0_CON));
p->addr = DISP_REG_GET(layer_off + DISP_REG_OVL_L0_ADDR);
p->src_w =
DISP_REG_GET(layer_off + DISP_REG_OVL_L0_SRC_SIZE) & 0xfff;
p->src_h =
(DISP_REG_GET(layer_off + DISP_REG_OVL_L0_SRC_SIZE) >> 16) &
0xfff;
p->src_pitch =
DISP_REG_GET(layer_off + DISP_REG_OVL_L0_PITCH) & 0xffff;
p->bpp =
ovl_input_fmt_bpp(DISP_REG_GET_FIELD
(L_CON_FLD_CFMT,
layer_off + DISP_REG_OVL_L0_CON));
}
DDPMSG("ovl_get_info:layer%d,en %d,w %d,h %d,bpp %d,addr %lu\n",
i, p->layer_en, p->src_w, p->src_h, p->bpp, p->addr);
}
void _ddp_mmp_ovl_not_raw_under_session(unsigned int session, OVL_CONFIG_STRUCT *pLayer, MMP_MetaDataBitmap_t *Bitmap)
{
if (session == 1) {
if (ovl_get_status() == DDP_OVL1_STATUS_PRIMARY ||
ovl_get_status() == DDP_OVL1_STATUS_SUB_REQUESTING) { /* 8+0 */
if (pLayer->layer < 4)
MMProfileLogMetaBitmap(DDP_MMP_Events.ovl1layer_dump[pLayer->layer],
MMProfileFlagPulse, Bitmap);
else if (pLayer->layer >= 4 && pLayer->layer < 8)
MMProfileLogMetaBitmap(DDP_MMP_Events.layer_dump[pLayer->layer % 4],
MMProfileFlagPulse, Bitmap);
} else {
MMProfileLogMetaBitmap(DDP_MMP_Events.layer_dump[pLayer->layer % 4],
MMProfileFlagPulse, Bitmap);
}
} else if (session == 2) {
MMProfileLogMetaBitmap(DDP_MMP_Events.ovl1layer_dump[pLayer->layer],
MMProfileFlagPulse, Bitmap);
}
}
static int ovl_layer_config(DISP_MODULE_ENUM module,
unsigned int layer,
unsigned int source,
DpColorFormat format,
unsigned long addr,
unsigned int src_x, /* ROI x offset*/
unsigned int src_y, /* ROI y offset*/
unsigned int src_pitch,
unsigned int dst_x, /* ROI x offset*/
unsigned int dst_y, /* ROI y offset*/
unsigned int dst_w, /* ROT width*/
unsigned int dst_h, /* ROI height*/
unsigned int key_en,
unsigned int key, /*color key*/
unsigned int aen, /* alpha enable*/
unsigned char alpha,
unsigned int sur_aen,
unsigned int src_alpha,
unsigned int dst_alpha,
unsigned int constant_color,
unsigned int yuv_range,
DISP_BUFFER_TYPE sec,
unsigned int is_engine_sec,
void *handle)
{
int idx = ovl_index(module);
unsigned int value = 0;
enum OVL_INPUT_FORMAT fmt = ovl_input_fmt_convert(format);
unsigned int bpp = ovl_input_fmt_bpp(fmt);
unsigned int input_swap = ovl_input_fmt_byte_swap(fmt);
unsigned int input_fmt = ovl_input_fmt_reg_value(fmt);
enum OVL_COLOR_SPACE space = ovl_input_fmt_color_space(fmt);
unsigned int offset = 0;
/*0100 MTX_JPEG_TO_RGB (YUV FUll TO RGB)*/
int color_matrix = 0x4;
unsigned int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
unsigned int layer_offset = idx_offset + layer * OVL_LAYER_OFFSET;
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
unsigned int bg_h, bg_w;
#endif
switch(yuv_range)
{
case 0: color_matrix = 4; break; //BT601_full
case 1: color_matrix = 6; break; //BT601
case 2: color_matrix = 7; break; //BT709
default:
DDPERR("un-recognized yuv_range=%d! \n", yuv_range);
color_matrix = 4;
}
// DDPMSG("color matrix=%d. \n", color_matrix);
ASSERT((dst_w <= OVL_MAX_WIDTH) &&
(dst_h <= OVL_MAX_HEIGHT) &&
(layer <= 3));
if (addr == 0) {
DDPERR("source from memory, but addr is 0!\n");
ASSERT(0);
}
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
DDPMSG("ovl%d, layer=%d, source=%s, off(x=%d, y=%d), dst(%d, %d, %d, %d),pitch=%d,"
"fmt=%s, addr=%lx, keyEn=%d, key=%d, aen=%d, alpha=%d,"
"sur_aen=%d,sur_alpha=0x%x, constant_color=0x%x, yuv_range=%d, sec=%d,ovlsec=%d\n",
idx, layer, (source==0)?"memory":"dim", src_x, src_y,dst_x, dst_y,
dst_w, dst_h, src_pitch, ovl_intput_format_name(fmt, input_swap),
addr, key_en, key, aen, alpha, sur_aen,
dst_alpha<<2 | src_alpha, constant_color, yuv_range, sec, is_engine_sec);
#endif
if(source==OVL_LAYER_SOURCE_RESERVED) //==1, means constant color
{
if(aen==0)
{
DDPERR("dim layer ahpha enable should be 1!\n");
}
if(fmt!=OVL_INPUT_FORMAT_RGB565 && fmt!=OVL_INPUT_FORMAT_RGB888)
{
//DDPERR("dim layer format should be RGB565");
fmt = OVL_INPUT_FORMAT_RGB888;
input_fmt = ovl_input_fmt_reg_value(fmt);
}
}
// DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_RDMA0_CTRL+layer_offset, 0x1);
value = (REG_FLD_VAL((L_CON_FLD_LARC), (source)) |
REG_FLD_VAL((L_CON_FLD_CFMT), (input_fmt)) |
REG_FLD_VAL((L_CON_FLD_AEN), (aen)) |
REG_FLD_VAL((L_CON_FLD_APHA), (alpha)) |
REG_FLD_VAL((L_CON_FLD_SKEN), (key_en)) |
REG_FLD_VAL((L_CON_FLD_BTSW), (input_swap)));
if (space == OVL_COLOR_SPACE_YUV)
value = value | REG_FLD_VAL((L_CON_FLD_MTX), (color_matrix));
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
value |= 0x600;
#endif
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_CON+layer_offset, value);
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_CLR+idx_offset+layer*4, constant_color);
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_SRC_SIZE+layer_offset,
dst_h<<16 | dst_w);
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
bg_h = DISP_REG_GET(idx_offset + DISP_REG_OVL_ROI_SIZE);
bg_w = bg_h & 0xFFFF;
bg_h = bg_h >> 16;
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_OFFSET+layer_offset, ((bg_h-dst_h-dst_y)<<16)|(bg_w-dst_w-dst_x));
#else
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_OFFSET+layer_offset,
dst_y<<16 | dst_x);
#endif
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
offset = src_pitch*(dst_h+src_y-1)+(src_x+dst_w)*bpp-1;
#else
offset = src_x*bpp+src_y*src_pitch;
#endif
if(!is_engine_sec) {
DISP_REG_SET(handle, DISP_REG_OVL_L0_ADDR+layer_offset, addr+offset);
} else {
unsigned int size;
int m4u_port;
size = (dst_h-1)*src_pitch + dst_w*bpp;
#if defined(MTK_FB_OVL1_SUPPORT)
m4u_port = idx==0 ? M4U_PORT_DISP_OVL0 : M4U_PORT_DISP_OVL1;
#else
m4u_port = M4U_PORT_DISP_OVL0;
#endif
if(sec != DISP_SECURE_BUFFER) {
/* ovl is sec but this layer is non-sec */
/* we need to tell cmdq to help map non-sec mva to sec mva */
cmdqRecWriteSecure(handle, disp_addr_convert(DISP_REG_OVL_L0_ADDR+layer_offset),
CMDQ_SAM_NMVA_2_MVA, addr+offset, 0, size, m4u_port);
} else {
/* for sec layer, addr variable stores sec handle*/
/* we need to pass this handle and offset to cmdq driver */
/* cmdq sec driver will help to convert handle to correct address */
offset = src_x*bpp+src_y*src_pitch;
cmdqRecWriteSecure(handle, disp_addr_convert(DISP_REG_OVL_L0_ADDR+layer_offset),
CMDQ_SAM_H_2_MVA, addr, offset, size, m4u_port);
}
}
if(key_en==1)
{
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_SRCKEY+layer_offset, key);
}
value = (((sur_aen & 0x1) << 15) |
((dst_alpha & 0x3) << 6) | ((dst_alpha & 0x3) << 4) |
((src_alpha & 0x3)<<2) | (src_alpha & 0x3));
value = (REG_FLD_VAL((L_PITCH_FLD_SUR_ALFA), (value)) |
REG_FLD_VAL((L_PITCH_FLD_LSP), (src_pitch)));
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_PITCH+layer_offset, value);
if(idx==0)
{
if(primary_display_is_decouple_mode()==0)
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x6070)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070);
}
else
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x50FF)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x50FF);
}
}
if(idx==1)
{
if(primary_display_is_decouple_mode()==0 && ovl_get_status()!=DDP_OVL1_STATUS_SUB)
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x6070)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070);
}
else
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x50FF)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x50FF);
}
}
return 0;
}
/**
* Represent to OVL0/0VL1 each layer's refresh rate
*/
static void ddp_inout_info_tag(unsigned int index) {
static unsigned long sLayerBufAddr[OVL_NUM][OVL_LAYER_NUM_PER_OVL];
static unsigned int sLayerBufFmt[OVL_NUM][OVL_LAYER_NUM_PER_OVL];
static unsigned int sLayerBufWidth[OVL_NUM][OVL_LAYER_NUM_PER_OVL];
static unsigned int sLayerBufHeight[OVL_NUM][OVL_LAYER_NUM_PER_OVL];
OVL_BASIC_STRUCT ovlInfo[OVL_LAYER_NUM];
unsigned int flag, i, idx, enLayerCnt, layerCnt;
unsigned int width, height, bpp, fmt;
char* fmtStr;
char tag_name[30] = { '\0' };
memset((void*)ovlInfo, 0, sizeof(ovlInfo));
ovl_get_info(index, ovlInfo);
//Any layer enable bit changes , new frame refreshes
enLayerCnt = 0;
if (ovl_get_status() == DDP_OVL1_STATUS_PRIMARY) {
layerCnt = OVL_LAYER_NUM;
} else {
layerCnt = OVL_LAYER_NUM_PER_OVL;
}
for (i = 0; i < layerCnt; i++) {
if (ovl_get_status() == DDP_OVL1_STATUS_PRIMARY) {
index = 1 - i / OVL_LAYER_NUM_PER_OVL;
}
idx = i % OVL_LAYER_NUM_PER_OVL;
fmtStr = parse_color_format(ovlInfo[i].fmt);
if (ovlInfo[i].layer_en) {
enLayerCnt++;
if (sLayerBufAddr[index][idx] != ovlInfo[i].addr) {
sLayerBufAddr[index][idx] = ovlInfo[i].addr;
sprintf(tag_name, "OVL%dL%d_InFps", index, idx);
met_tag_oneshot(DDP_IRQ_LAYER_FPS_ID, tag_name, i+1);
}
#if 0
if (sLayerBufFmt[index][idx] != ovlInfo[i].fmt) {
sLayerBufFmt[index][idx] = ovlInfo[i].fmt;
sprintf(tag_name, "OVL%dL%d_Fmt_%s", index, idx, fmtStr);
met_tag_oneshot(DDP_IRQ_LAYER_FORMAT_ID, tag_name, i+1);
}
if (sLayerBufWidth[index][idx] != ovlInfo[i].src_w) {
sLayerBufWidth[index][idx] = ovlInfo[i].src_w;
sprintf(tag_name, "OVL%dL%d_Width", index, idx);
met_tag_oneshot(DDP_IRQ_LAYER_SIZE_ID, tag_name, ovlInfo[i].src_w);
}
if (sLayerBufHeight[index][idx] != ovlInfo[i].src_h) {
sLayerBufHeight[index][idx] = ovlInfo[i].src_h;
sprintf(tag_name, "OVL%dL%d_Height", index, idx);
met_tag_oneshot(DDP_IRQ_LAYER_SIZE_ID, tag_name, ovlInfo[i].src_h);
}
#endif
} else {
sLayerBufAddr[index][idx] = 0;
sLayerBufFmt[index][idx] = 0;
sLayerBufWidth[index][idx] = 0;
sLayerBufHeight[index][idx] = 0;
}
if ( (i == (OVL_LAYER_NUM_PER_OVL-1)) || (i == (OVL_LAYER_NUM-1)) ) {
if (enLayerCnt) {
enLayerCnt = 0;
sprintf(tag_name, "OVL%d_OutFps", index);
met_tag_oneshot(DDP_IRQ_LAYER_FPS_ID, tag_name, index);
}
}
}
}
void ddp_mmp_ovl_layer(OVL_CONFIG_STRUCT* pLayer,unsigned int down_sample_x,unsigned int down_sample_y,unsigned int session/*1:primary, 2:external, 3:memory*/)
{
MMP_MetaDataBitmap_t Bitmap;
MMP_MetaData_t meta;
int raw = 0;
if(session == 1)
MMProfileLogEx(DDP_MMP_Events.layer_dump_parent,MMProfileFlagStart, pLayer->layer, pLayer->layer_en);
else if(session == 2)
MMProfileLogEx(DDP_MMP_Events.Extd_layer_dump_parent,MMProfileFlagStart, pLayer->layer, pLayer->layer_en);
if (pLayer->layer_en)
{
Bitmap.data1 = pLayer->vaddr;
Bitmap.width = pLayer->dst_w;
Bitmap.height = pLayer->dst_h;
switch (pLayer->fmt)
{
case eRGB565:
case eBGR565:
Bitmap.format = MMProfileBitmapRGB565;
Bitmap.bpp = 16;
break;
case eRGB888:
Bitmap.format = MMProfileBitmapRGB888;
Bitmap.bpp = 24;
break;
case eBGRA8888:
Bitmap.format = MMProfileBitmapBGRA8888;
Bitmap.bpp = 32;
break;
case eBGR888:
Bitmap.format = MMProfileBitmapBGR888;
Bitmap.bpp = 24;
break;
case eRGBA8888:
Bitmap.format = MMProfileBitmapRGBA8888;
Bitmap.bpp = 32;
break;
case eABGR8888:
Bitmap.format = MMProfileBitmapRGBA8888;
Bitmap.bpp = 32;
break;
default:
DDPERR("ddp_mmp_ovl_layer(), unknow fmt=0x%x, %s, dump raw\n", pLayer->fmt, disp_get_fmt_name(pLayer->fmt));
raw = 1;
}
// added for ARGB but alpha_enable=0 display
Bitmap.data2 = pLayer->aen;
if(!raw)
{
Bitmap.start_pos =0;
Bitmap.pitch = pLayer->src_pitch;
Bitmap.data_size = Bitmap.pitch * Bitmap.height;
Bitmap.down_sample_x = down_sample_x;
Bitmap.down_sample_y = down_sample_y;
if (m4u_mva_map_kernel(pLayer->addr, Bitmap.data_size,(unsigned int*)&Bitmap.pData, &Bitmap.data_size)==0)
{
if(session == 1)
{
if(ovl_get_status()==DDP_OVL1_STATUS_PRIMARY || ovl_get_status()==DDP_OVL1_STATUS_SUB_REQUESTING ) //8+0
{
if(pLayer->layer<4)
{
MMProfileLogMetaBitmap(DDP_MMP_Events.ovl1layer_dump[pLayer->layer], MMProfileFlagPulse, &Bitmap);
}
else if(pLayer->layer>=4 && pLayer->layer<8)
{
MMProfileLogMetaBitmap(DDP_MMP_Events.layer_dump[pLayer->layer%4], MMProfileFlagPulse, &Bitmap);
}
}
else
{
MMProfileLogMetaBitmap(DDP_MMP_Events.layer_dump[pLayer->layer%4], MMProfileFlagPulse, &Bitmap);
}
}
else if(session == 2)
MMProfileLogMetaBitmap(DDP_MMP_Events.ovl1layer_dump[pLayer->layer], MMProfileFlagPulse, &Bitmap);
m4u_mva_unmap_kernel(pLayer->addr, Bitmap.data_size, (unsigned long)Bitmap.pData);
}
else
{
DDPERR("ddp_mmp_ovl_layer(),fail to dump rgb(0x%x)\n", pLayer->fmt);
}
}
else
{
meta.data_type = MMProfileMetaRaw;
meta.size = pLayer->src_pitch * pLayer->src_h;
if(m4u_mva_map_kernel(pLayer->addr, meta.size, (unsigned int*)&meta.pData, &meta.size)==0)
{
if(session == 1)
{
if(ovl_get_status()==DDP_OVL1_STATUS_PRIMARY || ovl_get_status()==DDP_OVL1_STATUS_SUB_REQUESTING ) //8+0
{
if(pLayer->layer<4)
{
MMProfileLogMeta(DDP_MMP_Events.ovl1layer_dump[pLayer->layer], MMProfileFlagPulse, &meta);
}
else if(pLayer->layer>=4 && pLayer->layer<8)
{
MMProfileLogMeta(DDP_MMP_Events.layer_dump[pLayer->layer%4], MMProfileFlagPulse, &meta);
}
}
else
{
MMProfileLogMeta(DDP_MMP_Events.layer_dump[pLayer->layer%4], MMProfileFlagPulse, &meta);
}
}
else if(session == 2)
MMProfileLogMeta(DDP_MMP_Events.ovl1layer_dump[pLayer->layer], MMProfileFlagPulse, &meta);
m4u_mva_unmap_kernel(pLayer->addr, meta.size, (unsigned long)meta.pData);
}
else
{
DDPERR("ddp_mmp_ovl_layer(),fail to dump raw(0x%x)\n", pLayer->fmt);
}
}
}
if(session == 1)
MMProfileLogEx(DDP_MMP_Events.layer_dump_parent,MMProfileFlagEnd, pLayer->fmt, pLayer->addr);
else if(session == 2)
MMProfileLogEx(DDP_MMP_Events.Extd_layer_dump_parent,MMProfileFlagEnd, pLayer->fmt, pLayer->addr);
return ;
}
irqreturn_t disp_irq_handler(int irq, void *dev_id)
{
DISP_MODULE_ENUM module = DISP_MODULE_UNKNOWN;
unsigned long reg_val = 0;
unsigned int index = 0;
unsigned int mutexID = 0;
unsigned long reg_temp_val = 0;
DDPDBG("disp_irq_handler, irq=%d, module=%s \n", irq, disp_irq_module(irq));
MMProfileLogEx(ddp_mmp_get_events()->DDP_IRQ, MMProfileFlagStart, irq, 0);
//switch(irq)
{
if(irq==dispsys_irq[DISP_REG_DSI0])
{
module = DISP_MODULE_DSI0;
reg_val = (DISP_REG_GET(dsi_reg_va + 0xC) & 0xff);
if(atomic_read(&ESDCheck_byCPU) == 0)
{
reg_temp_val=reg_val&0xfffe;//rd_rdy don't clear and wait for ESD & Read LCM will clear the bit.
DISP_CPU_REG_SET(dsi_reg_va + 0xC, ~reg_temp_val);
}
else
{
DISP_CPU_REG_SET(dsi_reg_va + 0xC, ~reg_val);
}
MMProfileLogEx(ddp_mmp_get_events()->DSI_IRQ[0], MMProfileFlagPulse, reg_val, 0);
}
else if(irq==dispsys_irq[DISP_REG_OVL0] || irq==dispsys_irq[DISP_REG_OVL1])
{
index = (irq==dispsys_irq[DISP_REG_OVL0]) ? 0 : 1;
module= (irq==dispsys_irq[DISP_REG_OVL0]) ? DISP_MODULE_OVL0 : DISP_MODULE_OVL1;
reg_val = DISP_REG_GET(DISP_REG_OVL_INTSTA+index*DISP_OVL_INDEX_OFFSET);
if(reg_val&(1<<1))
{
DDPIRQ("IRQ: OVL%d frame done! \n",index);
ovl_complete_irq_cnt[index]++;
// update OVL addr
{
unsigned int i = 0;
if(index==0)
{
for(i=0;i<4;i++)
{
if(DISP_REG_GET(DISP_REG_OVL_SRC_CON)&(0x1<<i))
MMProfileLogEx(ddp_mmp_get_events()->layer[i], MMProfileFlagPulse, DISP_REG_GET(DISP_REG_OVL_L0_ADDR+i*0x20), 0);
}
}
if(index==1)
{
for(i=0;i<4;i++)
{
if(DISP_REG_GET(DISP_REG_OVL_SRC_CON+DISP_OVL_INDEX_OFFSET)&(0x1<<i))
MMProfileLogEx(ddp_mmp_get_events()->ovl1_layer[i], MMProfileFlagPulse, DISP_REG_GET(DISP_REG_OVL_L0_ADDR+DISP_OVL_INDEX_OFFSET+i*0x20), 0);
}
}
}
}
if(reg_val&(1<<2))
{
//DDPERR("IRQ: OVL%d frame underrun! cnt=%d \n",index, cnt_ovl_underflow[index]++);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<3))
{
DDPIRQ("IRQ: OVL%d sw reset done\n",index);
}
if(reg_val&(1<<4))
{
DDPIRQ("IRQ: OVL%d hw reset done\n",index);
}
if(reg_val&(1<<5))
{
DDPERR("IRQ: OVL%d-L0 not complete untill EOF!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<6))
{
DDPERR("IRQ: OVL%d-L1 not complete untill EOF!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<7))
{
DDPERR("IRQ: OVL%d-L2 not complete untill EOF!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<8))
{
DDPERR("IRQ: OVL%d-L3 not complete untill EOF!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<9))
{
//DDPERR("IRQ: OVL%d-L0 fifo underflow!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<10))
{
//DDPERR("IRQ: OVL%d-L1 fifo underflow!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<11))
{
//DDPERR("IRQ: OVL%d-L2 fifo underflow!\n",index);
//disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<12))
{
//DDPERR("IRQ: OVL%d-L3 fifo underflow!\n",index);
//disp_irq_log_module |= 1<<module;
}
//clear intr
if(reg_val&(0xf<<5))
{
ddp_dump_analysis(DISP_MODULE_CONFIG);
if(index==0)
{
ddp_dump_analysis(DISP_MODULE_OVL1);
ddp_dump_analysis(DISP_MODULE_OVL0);
ddp_dump_analysis(DISP_MODULE_COLOR0);
ddp_dump_analysis(DISP_MODULE_AAL);
ddp_dump_analysis(DISP_MODULE_RDMA0);
}
else
{
ddp_dump_analysis(DISP_MODULE_OVL1);
ddp_dump_analysis(DISP_MODULE_RDMA1);
ddp_dump_reg(DISP_MODULE_CONFIG);
}
}
DISP_CPU_REG_SET(DISP_REG_OVL_INTSTA+index*DISP_OVL_INDEX_OFFSET, ~reg_val);
MMProfileLogEx(ddp_mmp_get_events()->OVL_IRQ[index], MMProfileFlagPulse, reg_val, 0);
if(reg_val&0x1e0)
{
MMProfileLogEx(ddp_mmp_get_events()->ddp_abnormal_irq, MMProfileFlagPulse, (index<<16)|reg_val, module<<24);
}
}
else if(irq==dispsys_irq[DISP_REG_WDMA0] || irq==dispsys_irq[DISP_REG_WDMA1])
{
index = (irq==dispsys_irq[DISP_REG_WDMA0]) ? 0 : 1;
module =(irq==dispsys_irq[DISP_REG_WDMA0]) ? DISP_MODULE_WDMA0 : DISP_MODULE_WDMA1;
reg_val = DISP_REG_GET(DISP_REG_WDMA_INTSTA+index*DISP_WDMA_INDEX_OFFSET);
if(reg_val&(1<<0))
{
DDPIRQ("IRQ: WDMA%d frame done!\n",index);
}
if(reg_val&(1<<1))
{
DDPERR("IRQ: WDMA%d underrun! cnt=%d\n",index,cnt_wdma_underflow[index]++);
disp_irq_log_module |= 1<<module;
}
//clear intr
DISP_CPU_REG_SET(DISP_REG_WDMA_INTSTA+index*DISP_WDMA_INDEX_OFFSET,~reg_val);
MMProfileLogEx(ddp_mmp_get_events()->WDMA_IRQ[index], MMProfileFlagPulse, reg_val, DISP_REG_GET(DISP_REG_WDMA_CLIP_SIZE));
if(reg_val&0x2)
{
MMProfileLogEx(ddp_mmp_get_events()->ddp_abnormal_irq, MMProfileFlagPulse, (index<<16)|reg_val, cnt_wdma_underflow[index]|(module<<24));
}
}
else if(irq==dispsys_irq[DISP_REG_RDMA0] || irq==dispsys_irq[DISP_REG_RDMA1])
{
if(dispsys_irq[DISP_REG_RDMA0]==irq)
{
index = 0;
module = DISP_MODULE_RDMA0;
}
else if(dispsys_irq[DISP_REG_RDMA1]==irq)
{
index = 1;
module = DISP_MODULE_RDMA1;
}
reg_val = DISP_REG_GET(DISP_REG_RDMA_INT_STATUS+index*DISP_RDMA_INDEX_OFFSET);
if(reg_val&(1<<0))
{
DDPIRQ("IRQ: RDMA%d reg update done! \n",index);
}
if(reg_val&(1<<1))
{
MMProfileLogEx(ddp_mmp_get_events()->SCREEN_UPDATE[index], MMProfileFlagStart, reg_val, DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR));
rdma_start_time[index]= sched_clock();
DDPIRQ("IRQ: RDMA%d frame start! \n",index);
rdma_start_irq_cnt[index]++;
// rdma start/end irq should equal, else need reset ovl
if(gResetRDMAEnable == 1 &&
is_hwc_enabled == 1 &&
index ==0 &&
primary_display_is_video_mode()==1 &&
rdma_start_irq_cnt[0] > rdma_done_irq_cnt[0]+3)
{
ovl_reset(DISP_MODULE_OVL0, NULL);
if(ovl_get_status()!=DDP_OVL1_STATUS_SUB)
{
ovl_reset(DISP_MODULE_OVL1, NULL);
}
rdma_done_irq_cnt[0] = rdma_start_irq_cnt[0];
DDPERR("warning: reset ovl!\n");
}
#ifdef CONFIG_MTK_SEGMENT_TEST
if(record_rdma_end_interval == 1)
{
if(rdma_end_begin_time == 0)
{
rdma_end_begin_time = sched_clock();
//printk("[display_test]====RDMA frame end time1:%lld\n",rdma_end_begin_time);
}
else
{
unsigned long long time_now = sched_clock();
//printk("[display_test]====RDMA frame end time2:%lld\n",time_now);
//printk("[display_test]====RDMA frame end time3:this=%lld,max=%lld,min=%lld\n",time_now - rdma_end_begin_time,rdma_end_max_interval,rdma_end_min_interval);
if((time_now - rdma_end_begin_time) > rdma_end_max_interval)
{
rdma_end_max_interval = time_now - rdma_end_begin_time;
}
if((time_now - rdma_end_begin_time) < rdma_end_min_interval)
{
rdma_end_min_interval = time_now - rdma_end_begin_time;
}
rdma_end_begin_time = time_now;
}
}
#endif
}
if(reg_val&(1<<2))
{
MMProfileLogEx(ddp_mmp_get_events()->SCREEN_UPDATE[index], MMProfileFlagEnd, reg_val, 0);
rdma_end_time[index]= sched_clock();
DDPIRQ("IRQ: RDMA%d frame done! \n",index);
//rdma_done_irq_cnt[index] ++;
rdma_done_irq_cnt[index] = rdma_start_irq_cnt[index];
}
if(reg_val&(1<<3))
{
DDPERR("IRQ: RDMA%d abnormal! cnt=%d \n",index, cnt_rdma_abnormal[index]++);
disp_irq_log_module |= 1<<module;
}
if(reg_val&(1<<4))
{
DDPERR("IRQ: RDMA%d underflow! cnt=%d \n",index, cnt_rdma_underflow[index]++);
disp_irq_log_module |= 1<<module;
rdma_underflow_irq_cnt[index]++;
}
if(reg_val&(1<<5))
{
DDPIRQ("IRQ: RDMA%d target line! \n",index);
rdma_targetline_irq_cnt[index]++;
}
//clear intr
DISP_CPU_REG_SET(DISP_REG_RDMA_INT_STATUS+index*DISP_RDMA_INDEX_OFFSET,~reg_val);
MMProfileLogEx(ddp_mmp_get_events()->RDMA_IRQ[index], MMProfileFlagPulse, reg_val, 0);
if(reg_val&0x18)
{
MMProfileLogEx(ddp_mmp_get_events()->ddp_abnormal_irq, MMProfileFlagPulse, (index<<16)|reg_val, rdma_underflow_irq_cnt[index]|(cnt_rdma_abnormal[index]<<8)||(module<<24));
}
}
else if(irq==dispsys_irq[DISP_REG_COLOR])
{
}
else if(irq==dispsys_irq[DISP_REG_MUTEX])
{
// mutex0: perimary disp
// mutex1: sub disp
// mutex2: aal
module = DISP_MODULE_MUTEX;
reg_val = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTSTA) & 0x7C1F;
for(mutexID = 0; mutexID<5; mutexID++)
{
if(reg_val & (0x1<<mutexID))
{
DDPIRQ("IRQ: mutex%d sof!\n",mutexID);
MMProfileLogEx(ddp_mmp_get_events()->MUTEX_IRQ[mutexID], MMProfileFlagPulse, reg_val, 0);
}
if(reg_val & (0x1<<(mutexID+DISP_MUTEX_TOTAL)))
{
DDPIRQ("IRQ: mutex%d eof!\n",mutexID);
MMProfileLogEx(ddp_mmp_get_events()->MUTEX_IRQ[mutexID], MMProfileFlagPulse, reg_val, 1);
}
}
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTSTA, ~reg_val);
}
else if(irq==dispsys_irq[DISP_REG_AAL])
{
module = DISP_MODULE_AAL;
reg_val = DISP_REG_GET(DISP_AAL_INTSTA);
disp_aal_on_end_of_frame();
}
else if(irq==dispsys_irq[DISP_REG_CONFIG]) // MMSYS error intr
{
reg_val = DISP_REG_GET(DISP_REG_CONFIG_MMSYS_INTSTA) & 0x7;
if(reg_val&(1<<0))
{
DDPERR("MMSYS to MFG APB TX Error, MMSYS clock off but MFG clock on! \n");
}
if(reg_val&(1<<1))
{
DDPERR("MMSYS to MJC APB TX Error, MMSYS clock off but MJC clock on! \n");
}
if(reg_val&(1<<2))
{
DDPERR("PWM APB TX Error! \n");
}
DISP_CPU_REG_SET(DISP_REG_CONFIG_MMSYS_INTSTA, ~reg_val);
}
else
{
module = DISP_MODULE_UNKNOWN;
reg_val = 0;
DDPERR("invalid irq=%d \n ", irq);
}
}
disp_invoke_irq_callbacks(module, reg_val);
if(disp_irq_log_module!=0)
{
wake_up_interruptible(&disp_irq_log_wq);
}
MMProfileLogEx(ddp_mmp_get_events()->DDP_IRQ, MMProfileFlagEnd, irq, reg_val);
return IRQ_HANDLED;
}
static void process_dbg_debug(const char *opt)
{
unsigned int enable = 0;
static disp_session_config config;
char *p;
char *buf = dbg_buf + strlen(dbg_buf);
int ret;
p = (char *)opt + 6;
ret = kstrtoul(p, 10, (long unsigned int *)&enable);
if (ret)
pr_err("DISP/%s: errno %d\n", __func__, ret);
if (enable == 1) {
DDPMSG("[DDP] debug=1, trigger AEE\n");
/* aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); */
} else if (enable == 2) {
ddp_mem_test();
} else if (enable == 3) {
ddp_lcd_test();
} else if (enable == 4) {
DDPAEE("test enable=%d\n", enable);
sprintf(buf, "test enable=%d\n", enable);
} else if (enable == 5) {
if (gDDPError == 0)
gDDPError = 1;
else
gDDPError = 0;
sprintf(buf, "bypass PQ: %d\n", gDDPError);
DDPMSG("bypass PQ: %d\n", gDDPError);
} else if (enable == 6) {
unsigned int i = 0;
int *modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);
pr_debug("dump path status:");
for (i = 0; i < module_num; i++)
pr_debug("%s-", ddp_get_module_name(modules[i]));
pr_debug("\n");
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_MUTEX);
for (i = 0; i < module_num; i++)
ddp_dump_analysis(modules[i]);
if (primary_display_is_decouple_mode()) {
ddp_dump_analysis(DISP_MODULE_OVL0);
#if defined(OVL_CASCADE_SUPPORT)
ddp_dump_analysis(DISP_MODULE_OVL1);
#endif
ddp_dump_analysis(DISP_MODULE_WDMA0);
}
ddp_dump_reg(DISP_MODULE_CONFIG);
ddp_dump_reg(DISP_MODULE_MUTEX);
if (primary_display_is_decouple_mode()) {
ddp_dump_reg(DISP_MODULE_OVL0);
ddp_dump_reg(DISP_MODULE_OVL1);
ddp_dump_reg(DISP_MODULE_WDMA0);
}
for (i = 0; i < module_num; i++)
ddp_dump_reg(modules[i]);
} else if (enable == 7) {
if (dbg_log_level < 3)
dbg_log_level++;
else
dbg_log_level = 0;
pr_debug("DDP: dbg_log_level=%d\n", dbg_log_level);
sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
} else if (enable == 8) {
DDPDUMP("clock_mm setting:%u\n", DISP_REG_GET(DISP_REG_CONFIG_C11));
if ((DISP_REG_GET(DISP_REG_CONFIG_C11) & 0xff000000) != 0xff000000)
DDPDUMP("error, MM clock bit 24~bit31 should be 1, but real value=0x%x",
DISP_REG_GET(DISP_REG_CONFIG_C11));
} else if (enable == 9) {
gOVLBackground = 0xFF0000FF;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 10) {
gOVLBackground = 0xFF000000;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 11) {
unsigned int i = 0;
char *buf_temp = buf;
for (i = 0; i < DISP_REG_NUM; i++) {
DDPDUMP("i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
i, ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]);
sprintf(buf_temp, "i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n", i,
ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]);
buf_temp += strlen(buf_temp);
}
} else if (enable == 12) {
if (gUltraEnable == 0)
gUltraEnable = 1;
else
gUltraEnable = 0;
pr_debug("DDP: gUltraEnable=%d\n", gUltraEnable);
sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);
} else if (enable == 13) {
int ovl_status = ovl_get_status();
config.type = DISP_SESSION_MEMORY;
config.device_id = 0;
disp_create_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status,
ovl_get_status());
} else if (enable == 14) {
int ovl_status = ovl_get_status();
disp_destroy_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status,
ovl_get_status());
} else if (enable == 15) {
/* extern smi_dumpDebugMsg(void); */
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_RDMA0);
ddp_dump_analysis(DISP_MODULE_OVL0);
#if defined(OVL_CASCADE_SUPPORT)
ddp_dump_analysis(DISP_MODULE_OVL1);
#endif
/* dump ultra/preultra related regs */
DDPMSG("wdma_con1(2c)=0x%x, wdma_con2(0x38)=0x%x,\n",
DISP_REG_GET(DISP_REG_WDMA_BUF_CON1),
DISP_REG_GET(DISP_REG_WDMA_BUF_CON2));
DDPMSG("rdma_gmc0(30)=0x%x, rdma_gmc1(38)=0x%x, fifo_con(40)=0x%x\n",
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0),
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1),
DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
DDPMSG("ovl0_gmc: 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc: 0x%x, 0x%x, 0x%x, 0x%x,\n",
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET));
/* dump smi regs */
/* smi_dumpDebugMsg(); */
} else if (enable == 16) {
if (gDumpMemoutCmdq == 0)
gDumpMemoutCmdq = 1;
else
gDumpMemoutCmdq = 0;
pr_debug("DDP: gDumpMemoutCmdq=%d\n", gDumpMemoutCmdq);
sprintf(buf, "gDumpMemoutCmdq: %d\n", gDumpMemoutCmdq);
} else if (enable == 21) {
if (gEnableSODIControl == 0)
gEnableSODIControl = 1;
else
gEnableSODIControl = 0;
pr_debug("DDP: gEnableSODIControl=%d\n", gEnableSODIControl);
sprintf(buf, "gEnableSODIControl: %d\n", gEnableSODIControl);
} else if (enable == 22) {
if (gPrefetchControl == 0)
gPrefetchControl = 1;
else
gPrefetchControl = 0;
pr_debug("DDP: gPrefetchControl=%d\n", gPrefetchControl);
sprintf(buf, "gPrefetchControl: %d\n", gPrefetchControl);
} else if (enable == 23) {
if (disp_low_power_enlarge_blanking == 0)
disp_low_power_enlarge_blanking = 1;
else
disp_low_power_enlarge_blanking = 0;
pr_debug("DDP: disp_low_power_enlarge_blanking=%d\n",
disp_low_power_enlarge_blanking);
sprintf(buf, "disp_low_power_enlarge_blanking: %d\n",
disp_low_power_enlarge_blanking);
} else if (enable == 24) {
if (disp_low_power_disable_ddp_clock == 0)
disp_low_power_disable_ddp_clock = 1;
else
disp_low_power_disable_ddp_clock = 0;
pr_debug("DDP: disp_low_power_disable_ddp_clock=%d\n",
disp_low_power_disable_ddp_clock);
sprintf(buf, "disp_low_power_disable_ddp_clock: %d\n",
disp_low_power_disable_ddp_clock);
} else if (enable == 25) {
if (disp_low_power_disable_fence_thread == 0)
disp_low_power_disable_fence_thread = 1;
else
disp_low_power_disable_fence_thread = 0;
pr_debug("DDP: disp_low_power_disable_fence_thread=%d\n",
disp_low_power_disable_fence_thread);
sprintf(buf, "disp_low_power_disable_fence_thread: %d\n",
disp_low_power_disable_fence_thread);
} else if (enable == 26) {
if (disp_low_power_remove_ovl == 0)
disp_low_power_remove_ovl = 1;
else
disp_low_power_remove_ovl = 0;
pr_debug("DDP: disp_low_power_remove_ovl=%d\n", disp_low_power_remove_ovl);
sprintf(buf, "disp_low_power_remove_ovl: %d\n", disp_low_power_remove_ovl);
} else if (enable == 27) {
if (gSkipIdleDetect == 0)
gSkipIdleDetect = 1;
else
gSkipIdleDetect = 0;
pr_debug("DDP: gSkipIdleDetect=%d\n", gSkipIdleDetect);
sprintf(buf, "gSkipIdleDetect: %d\n", gSkipIdleDetect);
} else if (enable == 28) {
if (gDumpClockStatus == 0)
gDumpClockStatus = 1;
else
gDumpClockStatus = 0;
pr_debug("DDP: gDumpClockStatus=%d\n", gDumpClockStatus);
sprintf(buf, "gDumpClockStatus: %d\n", gDumpClockStatus);
} else if (enable == 29) {
if (gEnableUartLog == 0)
gEnableUartLog = 1;
else
gEnableUartLog = 0;
pr_debug("DDP: gEnableUartLog=%d\n", gEnableUartLog);
sprintf(buf, "gEnableUartLog: %d\n", gEnableUartLog);
} else if (enable == 30) {
if (gEnableMutexRisingEdge == 0) {
gEnableMutexRisingEdge = 1;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING,
DISP_REG_CONFIG_MUTEX0_SOF, 1);
} else {
gEnableMutexRisingEdge = 0;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING,
DISP_REG_CONFIG_MUTEX0_SOF, 0);
}
pr_debug("DDP: gEnableMutexRisingEdge=%d\n", gEnableMutexRisingEdge);
sprintf(buf, "gEnableMutexRisingEdge: %d\n", gEnableMutexRisingEdge);
} else if (enable == 31) {
if (gEnableReduceRegWrite == 0)
gEnableReduceRegWrite = 1;
else
gEnableReduceRegWrite = 0;
pr_debug("DDP: gEnableReduceRegWrite=%d\n", gEnableReduceRegWrite);
sprintf(buf, "gEnableReduceRegWrite: %d\n", gEnableReduceRegWrite);
} else if (enable == 32) {
DDPAEE("DDP: (32)gEnableReduceRegWrite=%d\n", gEnableReduceRegWrite);
} else if (enable == 33) {
if (gDumpConfigCMD == 0)
gDumpConfigCMD = 1;
else
gDumpConfigCMD = 0;
pr_debug("DDP: gDumpConfigCMD=%d\n", gDumpConfigCMD);
sprintf(buf, "gDumpConfigCMD: %d\n", gDumpConfigCMD);
} else if (enable == 34) {
if (gESDEnableSODI == 0)
gESDEnableSODI = 1;
else
gESDEnableSODI = 0;
pr_debug("DDP: gESDEnableSODI=%d\n", gESDEnableSODI);
sprintf(buf, "gESDEnableSODI: %d\n", gESDEnableSODI);
} else if (enable == 35) {
if (gEnableOVLStatusCheck == 0)
gEnableOVLStatusCheck = 1;
else
gEnableOVLStatusCheck = 0;
pr_debug("DDP: gEnableOVLStatusCheck=%d\n", gEnableOVLStatusCheck);
sprintf(buf, "gEnableOVLStatusCheck: %d\n", gEnableOVLStatusCheck);
} else if (enable == 36) {
if (gResetRDMAEnable == 0)
gResetRDMAEnable = 1;
else
gResetRDMAEnable = 0;
pr_debug("DDP: gResetRDMAEnable=%d\n", gResetRDMAEnable);
sprintf(buf, "gResetRDMAEnable: %d\n", gResetRDMAEnable);
} else if (enable == 37) {
unsigned int reg_value = 0;
if (gEnableIRQ == 0) {
gEnableIRQ = 1;
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e2);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e2);
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value | (1 << 0) | (1 << DISP_MUTEX_TOTAL));
} else {
gEnableIRQ = 0;
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e0);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e0);
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value & (~(1 << 0)) &
(~(1 << DISP_MUTEX_TOTAL)));
}
pr_debug("DDP: gEnableIRQ=%d\n", gEnableIRQ);
sprintf(buf, "gEnableIRQ: %d\n", gEnableIRQ);
} else if (enable == 38) {
if (gDisableSODIForTriggerLoop == 0)
gDisableSODIForTriggerLoop = 1;
else
gDisableSODIForTriggerLoop = 0;
pr_debug("DDP: gDisableSODIForTriggerLoop=%d\n",
gDisableSODIForTriggerLoop);
sprintf(buf, "gDisableSODIForTriggerLoop: %d\n",
gDisableSODIForTriggerLoop);
} else if (enable == 39) {
cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_STREAM_EOF);
cmdqCoreSetEvent(CMDQ_EVENT_DISP_RDMA0_EOF);
sprintf(buf, "enable=%d\n", enable);
} else if (enable == 41) {
if (gResetOVLInAALTrigger == 0)
gResetOVLInAALTrigger = 1;
else
gResetOVLInAALTrigger = 0;
pr_debug("DDP: gResetOVLInAALTrigger=%d\n", gResetOVLInAALTrigger);
sprintf(buf, "gResetOVLInAALTrigger: %d\n", gResetOVLInAALTrigger);
} else if (enable == 42) {
if (gDisableOVLTF == 0)
gDisableOVLTF = 1;
else
gDisableOVLTF = 0;
pr_debug("DDP: gDisableOVLTF=%d\n", gDisableOVLTF);
sprintf(buf, "gDisableOVLTF: %d\n", gDisableOVLTF);
} else if (enable == 43) {
if (gDumpESDCMD == 0)
gDumpESDCMD = 1;
else
gDumpESDCMD = 0;
pr_debug("DDP: gDumpESDCMD=%d\n", gDumpESDCMD);
sprintf(buf, "gDumpESDCMD: %d\n", gDumpESDCMD);
} else if (enable == 44) {
/* extern void disp_dump_emi_status(void); */
disp_dump_emi_status();
sprintf(buf, "dump emi status!\n");
} else if (enable == 40) {
sprintf(buf, "version: %d, %s\n", 7, __TIME__);
} else if (enable == 45) {
ddp_aee_print("DDP AEE DUMP!!\n");
} else if (enable == 46) {
ASSERT(0);
} else if (enable == 47) {
if (gEnableDSIStateCheck == 0)
gEnableDSIStateCheck = 1;
else
gEnableDSIStateCheck = 0;
pr_debug("DDP: gEnableDSIStateCheck=%d\n", gEnableDSIStateCheck);
sprintf(buf, "gEnableDSIStateCheck: %d\n", gEnableDSIStateCheck);
} else if (enable == 48) {
if (gMutexFreeRun == 0)
gMutexFreeRun = 1;
else
gMutexFreeRun = 0;
pr_debug("DDP: gMutexFreeRun=%d\n", gMutexFreeRun);
sprintf(buf, "gMutexFreeRun: %d\n", gMutexFreeRun);
}
}