Exemplo n.º 1
0
static void
rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd)
{
	uint64_t regval;
	uint64_t regno;

	RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)",
	    (void *)rgep, (void *)ppd));

	regno = ppd->pp_acc_offset;
	regval = ppd->pp_acc_data;

	switch (ppd->pp_acc_size) {
	case 1:
		pci_config_put8(rgep->cfg_handle, regno, regval);
		break;

	case 2:
		pci_config_put16(rgep->cfg_handle, regno, regval);
		break;

	case 4:
		pci_config_put32(rgep->cfg_handle, regno, regval);
		break;

	case 8:
		pci_config_put64(rgep->cfg_handle, regno, regval);
		break;
	}
}
Exemplo n.º 2
0
/*ARGSUSED*/
void
pmubus_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value)
{
	ddi_acc_hdl_t *hp = (ddi_acc_hdl_t *)hdlp;
	pmubus_mapreq_t *pmubus_mapreqp = hp->ah_bus_private;
	pmubus_devstate_t *softsp = pmubus_mapreqp->mapreq_softsp;
	off_t offset;
	uint32_t tmp;

	offset = pmubus_mapreqp->mapreq_addr + (uintptr_t)addr;
	offset &= PMUBUS_REGOFFSET;

	if ((pmubus_mapreqp->mapreq_flags) & MAPREQ_SHARED_BITS) {
		/*
		 * Process "bit lane" register
		 */
		DPRINTF(PMUBUS_RW_DEBUG, ("pmubus_put32: addr=%p offset=%lx "
		    "value=%x mask=%lx\n", (void *)addr, offset, value,
		    pmubus_mapreqp->mapreq_mask));

		if (addr != 0 ||
		    pmubus_mapreqp->mapreq_size != sizeof (value)) {
			cmn_err(CE_WARN, "pmubus_put32: store discarded, "
			    "incorrect access addr/size");
			return;
		}

		mutex_enter(&softsp->pmubus_reg_access_lock);
		tmp = pci_config_get32(softsp->pmubus_reghdl, offset);
		tmp &= ~pmubus_mapreqp->mapreq_mask;
		value &= pmubus_mapreqp->mapreq_mask;
		tmp |= value;
		pci_config_put32(softsp->pmubus_reghdl, offset, tmp);
		mutex_exit(&softsp->pmubus_reg_access_lock);
	} else {
		/*
		 * Process shared register
		 */
		DPRINTF(PMUBUS_RW_DEBUG, ("pmubus_put32: addr=%p offset=%lx "
		    "value=%x\n", (void *)addr, offset, value));
		pci_config_put32(softsp->pmubus_reghdl, offset, value);
	}

	/* Flush store buffers XXX Should let drivers do this. */
	tmp = pci_config_get32(softsp->pmubus_reghdl, offset);
}
Exemplo n.º 3
0
static void
agp_target_set_gartaddr(agp_target_softstate_t *softstate, uint32_t gartaddr)
{
	ASSERT(softstate->tsoft_acaptr);

	/* Disable the GTLB for Intel chipsets */
	pci_config_put16(softstate->tsoft_pcihdl,
	    softstate->tsoft_acaptr + AGP_CONF_CONTROL, 0x0000);

	pci_config_put32(softstate->tsoft_pcihdl,
	    softstate->tsoft_acaptr + AGP_CONF_ATTBASE,
	    gartaddr & AGP_ATTBASE_MASK);
}
Exemplo n.º 4
0
void
t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
{
    pci_config_put32(sc->pci_regh, reg, val);
}
Exemplo n.º 5
0
void
rge_chip_ident(rge_t *rgep)
{
	chip_id_t *chip = &rgep->chipid;
	uint32_t val32;
	uint16_t val16;

	/*
	 * Read and record MAC version
	 */
	val32 = rge_reg_get32(rgep, TX_CONFIG_REG);
	val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1;
	chip->mac_ver = val32;
	switch (chip->mac_ver) {
	case MAC_VER_8168:
	case MAC_VER_8168B_B:
	case MAC_VER_8168B_C:
	case MAC_VER_8168C:
	case MAC_VER_8101E:
	case MAC_VER_8101E_B:
		chip->is_pcie = B_TRUE;
		break;

	default:
		chip->is_pcie = B_FALSE;
		break;
	}

	/*
	 * Read and record PHY version
	 */
	val16 = rge_mii_get16(rgep, PHY_ID_REG_2);
	val16 &= PHY_VER_MASK;
	chip->phy_ver = val16;

	/* set pci latency timer */
	if (chip->mac_ver == MAC_VER_8169 ||
	    chip->mac_ver == MAC_VER_8169S_D ||
	    chip->mac_ver == MAC_VER_8169SC)
		pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40);

	if (chip->mac_ver == MAC_VER_8169SC) {
		val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG);
		val16 &= 0x0300;
		if (val16 == 0x1)	/* 66Mhz PCI */
			pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ff00ff);
		else if (val16 == 0x0) /* 33Mhz PCI */
			pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ffff00);
	}

	/*
	 * PCIE chipset require the Rx buffer start address must be
	 * 8-byte alignment and the Rx buffer size must be multiple of 8.
	 * We'll just use bcopy in receive procedure for the PCIE chipset.
	 */
	if (chip->is_pcie) {
		rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY;
		if (rgep->default_mtu > ETHERMTU) {
			rge_notice(rgep, "Jumbo packets not supported "
			    "for this PCIE chipset");
			rgep->default_mtu = ETHERMTU;
		}
	}
	if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY)
		rgep->head_room = 0;
	else
		rgep->head_room = RGE_HEADROOM;

	/*
	 * Initialize other variables.
	 */
	if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU)
		rgep->default_mtu = ETHERMTU;
	if (rgep->default_mtu > ETHERMTU) {
		rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO;
		rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO;
		rgep->ethmax_size = RGE_JUMBO_SIZE;
	} else {
		rgep->rxbuf_size = RGE_BUFF_SIZE_STD;
		rgep->txbuf_size = RGE_BUFF_SIZE_STD;
		rgep->ethmax_size = ETHERMAX;
	}
	chip->rxconfig = RX_CONFIG_DEFAULT;
	chip->txconfig = TX_CONFIG_DEFAULT;

	RGE_TRACE(("%s: MAC version = %x, PHY version = %x",
	    rgep->ifname, chip->mac_ver, chip->phy_ver));
}
Exemplo n.º 6
0
int
UM_PCI_Services(Adapter_Struc *pAd, union REGS *pregs)
{
	int func = (int)pregs->h.al;
	unsigned long regnum; /* register number */
	unsigned short vendid;
	unsigned short devid;
	unsigned long compval;

	switch (func) {
		case PCI_BIOS_PRESENT:
			/* return PCI present with rev 2.1 */
			pregs->h.ah = 0;
			pregs->h.al = 0;
			pregs->h.bh = 2;
			pregs->h.bl = 1;
			pregs->h.cl = 1;
			pregs->e.edx = 0x20494350;
			pregs->x.cflag = 0;
			break;
		case FIND_PCI_DEVICE:
			vendid = pregs->x.dx;
			devid = pregs->x.cx;
			compval = (((ulong_t)devid) << 16) | ((ulong_t)vendid);
			if (vendid == 0xffff) { /* bad vendor id */
				pregs->x.cflag = 1;
				pregs->h.ah = PCI_BAD_VENDOR_ID;
			} else {
				if (pci_config_get32(
				    (ddi_acc_handle_t)pAd->pcihandle, 0) ==
				    compval) {
					pregs->h.bh = 0; /* put 0 to fake it */
					pregs->h.bl = 0; /* put 0 to fake it */
					pregs->h.ah = PCI_SUCCESSFUL;
					pregs->x.cflag = 0;
				} else {
					pregs->h.ah = PCI_DEVICE_NOT_FOUND;
					pregs->x.cflag = 1;
				}
			}
			break;
		case PCI_READ_CONFIG_BYTE:
			regnum = (unsigned long) pregs->h.di;
			pregs->h.cl = pci_config_get8(
			    (ddi_acc_handle_t)pAd->pcihandle, regnum);
			pregs->x.cflag = 0;
			pregs->h.ah = PCI_SUCCESSFUL;
			break;
		case PCI_READ_CONFIG_WORD:
			regnum = (unsigned long)pregs->h.di;
			if (regnum & 0x1) {
				pregs->x.cflag = 1;
				pregs->h.ah = PCI_BAD_REGISTER_NUMBER;
			} else {
				pregs->x.cx = pci_config_get16(
				    (ddi_acc_handle_t)pAd->pcihandle, regnum);
				pregs->x.cflag = 0;
				pregs->h.ah = PCI_SUCCESSFUL;
			}
			break;
		case PCI_READ_CONFIG_DWORD:
			regnum = (unsigned long)pregs->h.di;
			if (regnum & 0x3) {
				pregs->x.cflag = 1;
				pregs->h.ah = PCI_BAD_REGISTER_NUMBER;
			} else {
				pregs->e.ecx = pci_config_get32(
				    (ddi_acc_handle_t)pAd->pcihandle, regnum);
				pregs->x.cflag = 0;
				pregs->h.ah = PCI_SUCCESSFUL;
			}
			break;
		case PCI_WRITE_CONFIG_BYTE:
			regnum = (unsigned long) pregs->h.di;
			pci_config_put8((ddi_acc_handle_t)pAd->pcihandle,
			    regnum, pregs->h.cl);
			pregs->x.cflag = 0;
			pregs->h.ah = PCI_SUCCESSFUL;
			break;
		case PCI_WRITE_CONFIG_WORD:
			regnum = (unsigned long)pregs->h.di;
			if (regnum & 0x1) {
				pregs->x.cflag = 1;
				pregs->h.ah = PCI_BAD_REGISTER_NUMBER;
			} else {
				pci_config_put16(
				    (ddi_acc_handle_t)pAd->pcihandle,
				    regnum, pregs->x.cx);
				pregs->x.cflag = 0;
				pregs->h.ah = PCI_SUCCESSFUL;
			}
			break;
		case PCI_WRITE_CONFIG_DWORD:
			regnum = (unsigned long)pregs->h.di;
			if (regnum & 0x1) {
				pregs->x.cflag = 1;
				pregs->h.ah = PCI_BAD_REGISTER_NUMBER;
			} else {
				pci_config_put32(
				    (ddi_acc_handle_t)pAd->pcihandle,
				    regnum, pregs->e.ecx);
				pregs->x.cflag = 0;
				pregs->h.ah = PCI_SUCCESSFUL;
			}
			break;
		default:
			pregs->x.cflag = 1;	/* set error */
			pregs->h.ah = PCI_FUNC_NOT_SUPPORTED;
			break;
	}
	return (0);
}
Exemplo n.º 7
0
/*ARGSUSED*/
static int
agp_target_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
    cred_t *cred, int *rval)
{
	int instance = DEV2INST(dev);
	agp_target_softstate_t *st;
	static char kernel_only[] =
	    "amd64_gart_ioctl: is a kernel only ioctl";

	if (!(mode & FKIOCTL)) {
		TARGETDB_PRINT2((CE_CONT, kernel_only));
		return (ENXIO);
	}
	st = GETSOFTC(instance);

	if (st == NULL)
		return (ENXIO);

	mutex_enter(&st->tsoft_lock);

	switch (cmd) {
	case CHIP_DETECT:
	{
		int type;
		switch (st->tsoft_devid & VENDOR_ID_MASK) {
		case INTEL_VENDOR_ID:
			type = CHIP_IS_INTEL;
			break;
		case AMD_VENDOR_ID:
			type = CHIP_IS_AMD;
			break;
		default:
			type = 0;
		}
		if (ddi_copyout(&type, (void *)data, sizeof (int), mode)) {
			mutex_exit(&st->tsoft_lock);
			return (EFAULT);
		}

		break;
	}
	case I8XX_GET_PREALLOC_SIZE:
	{
		size_t prealloc_size;

		if ((st->tsoft_devid & VENDOR_ID_MASK) !=
		    INTEL_VENDOR_ID) {
			mutex_exit(&st->tsoft_lock);
			return (EINVAL);
		}

		prealloc_size = i8xx_biosmem_detect(st);
		if (ddi_copyout(&prealloc_size, (void *)data,
		    sizeof (size_t), mode)) {
			mutex_exit(&st->tsoft_lock);
			return (EFAULT);
		}

		break;
	}
	case AGP_TARGET_GETINFO:
	{
		i_agp_info_t info;
		uint32_t value;
		off_t cap;

		ASSERT(st->tsoft_acaptr);

		cap = st->tsoft_acaptr;
		value = pci_config_get32(st->tsoft_pcihdl, cap);
		info.iagp_ver.agpv_major = (uint16_t)((value >> 20) & 0xf);
		info.iagp_ver.agpv_minor = (uint16_t)((value >> 16) & 0xf);
		info.iagp_devid = st->tsoft_devid;
		info.iagp_mode = pci_config_get32(st->tsoft_pcihdl,
			    cap + AGP_CONF_STATUS);
		info.iagp_aperbase = agp_target_get_apbase(st);
		info.iagp_apersize = agp_target_get_apsize(st);

		if (ddi_copyout(&info, (void *)data,
		    sizeof (i_agp_info_t), mode)) {
			mutex_exit(&st->tsoft_lock);
			return (EFAULT);
		}
		break;

	}
	/*
	 * This ioctl is only for Intel AGP chipsets.
	 * It is not necessary for the AMD8151 AGP bridge, because
	 * this register in the AMD8151 does not control any hardware.
	 * It is only provided for compatibility with an Intel AGP bridge.
	 * Please refer to the <<AMD8151 data sheet>> page 24,
	 * AGP device GART pointer.
	 */
	case AGP_TARGET_SET_GATTADDR:
	{
		uint32_t gartaddr;

		if (ddi_copyin((void *)data, &gartaddr,
		    sizeof (uint32_t), mode)) {
			mutex_exit(&st->tsoft_lock);
			return (EFAULT);
		}

		agp_target_set_gartaddr(st, gartaddr);
		break;
	}
	case AGP_TARGET_SETCMD:
	{
		uint32_t command;

		if (ddi_copyin((void *)data, &command,
		    sizeof (uint32_t), mode)) {
			mutex_exit(&st->tsoft_lock);
			return (EFAULT);
		}

		ASSERT(st->tsoft_acaptr);

		pci_config_put32(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_COMMAND,
		    command);
		break;

	}
	case AGP_TARGET_FLUSH_GTLB:
	{
		uint16_t value;

		ASSERT(st->tsoft_acaptr);

		value = pci_config_get16(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_CONTROL);
		value &= ~AGPCTRL_GTLBEN;
		pci_config_put16(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_CONTROL, value);
		value |= AGPCTRL_GTLBEN;
		pci_config_put16(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_CONTROL, value);

		break;
	}
	case AGP_TARGET_CONFIGURE:
	{
		uint8_t value;

		ASSERT(st->tsoft_acaptr);

		value = pci_config_get8(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_MISC);
		value |= AGP_MISC_APEN;
		pci_config_put8(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_MISC, value);
		break;

	}
	case AGP_TARGET_UNCONFIG:
	{
		uint32_t value1;
		uint8_t value2;

		ASSERT(st->tsoft_acaptr);

		pci_config_put16(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_CONTROL, 0x0);

		value2 = pci_config_get8(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_MISC);
		value2 &= ~AGP_MISC_APEN;
		pci_config_put8(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_MISC, value2);

		value1 = pci_config_get32(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_COMMAND);
		value1 &= ~AGPCMD_AGPEN;
		pci_config_put32(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_COMMAND,
		    value1);

		pci_config_put32(st->tsoft_pcihdl,
		    st->tsoft_acaptr + AGP_CONF_ATTBASE, 0x0);

		break;
	}

	default:
		mutex_exit(&st->tsoft_lock);
		return (ENXIO);
	} /* end switch */

	mutex_exit(&st->tsoft_lock);

	return (0);
}
Exemplo n.º 8
0
void
pciconfig_bar(void *instance, uint32_t offset, char *name)
{
    struct e1000g *Adapter = (struct e1000g *)instance;
    ddi_acc_handle_t handle = Adapter->osdep.cfg_handle;
    uint32_t base = pci_config_get32(handle, offset);
    uint16_t comm = pci_config_get16(handle, PCI_CONF_COMM);
    uint32_t size;		/* derived size of the region */
    uint32_t bits_comm;	/* command word bits to disable */
    uint32_t size_mask;	/* mask for size extraction */
    char tag_type[32];	/* tag to show memory vs. i/o */
    char tag_mem[32];	/* tag to show memory characteristiccs */

    /* base address zero, simple print */
    if (base == 0) {
        e1000g_log(Adapter, CE_CONT, "%s:\t0x%x\n", name, base);

        /* base address non-zero, get size */
    } else {
        /* i/o factors that decode from the base address */
        if (base & PCI_BASE_SPACE_IO) {
            bits_comm = PCI_COMM_IO;
            size_mask = PCI_BASE_IO_ADDR_M;
            (void) strcpy(tag_type, "i/o port size:");
            (void) strcpy(tag_mem, "");
            /* memory factors that decode from the base address */
        } else {
            bits_comm = PCI_COMM_MAE;
            size_mask = PCI_BASE_M_ADDR_M;
            (void) strcpy(tag_type, "memory size:");
            if (base & PCI_BASE_TYPE_ALL)
                (void) strcpy(tag_mem, "64bit ");
            else
                (void) strcpy(tag_mem, "32bit ");
            if (base & PCI_BASE_PREF_M)
                (void) strcat(tag_mem, "prefetchable");
            else
                (void) strcat(tag_mem, "non-prefetchable");
        }

        /* disable memory decode */
        pci_config_put16(handle, PCI_CONF_COMM, (comm & ~bits_comm));

        /* write to base register */
        pci_config_put32(handle, offset, 0xffffffff);

        /* read back & compute size */
        size = pci_config_get32(handle, offset);
        size &= size_mask;
        size = (~size) + 1;

        /* restore base register */
        pci_config_put32(handle, offset, base);

        /* re-enable memory decode */
        pci_config_put16(handle, PCI_CONF_COMM, comm);

        /* print results */
        e1000g_log(Adapter, CE_CONT, "%s:\t0x%x %s 0x%x %s\n",
                   name, base, tag_type, size, tag_mem);
    }
}