pcireg_t
ht_conf_read(void *cpv, pcitag_t tag, int offset)
{
struct ht_softc *sc = cpv;
int bus, dev, fcn;
pcireg_t reg;
uint32_t val;
val = PCITAG_OFFSET(tag);
#ifdef DEBUG
printf("ht_conf_read: tag=%x, offset=%x\n", val, offset);
#endif
pci_decompose_tag(NULL, tag, &bus, &dev, &fcn);
if (bus == 0 && dev == 0) {
val |= (offset << 2);
reg = bus_space_read_4(sc->sc_iot, sc->sc_config0_ioh, val);
reg = letoh32(reg);
} else if (bus == 0) {
/* XXX Why can we only access function 0? */
if (fcn > 0)
return ~0;
val |= offset;
reg = bus_space_read_4(sc->sc_memt, sc->sc_config0_memh, val);
} else {
val |= offset;
reg = bus_space_read_4(sc->sc_memt, sc->sc_config1_memh, val);
}
#ifdef DEBUG
printf("ht_conf_read: reg=%x\n", reg);
#endif
return reg;
}
pcireg_t
pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
{
pcireg_t data;
int bus, dev, func;
pci_decompose_tag(pc, tag, &bus, &dev, &func);
/*
* 2700 hardware wedges on accesses to device 6.
*/
if (bus == 0 && dev == 6)
return 0;
/*
* 2800 hardware wedges on accesses to device 31.
*/
if (bus == 0 && dev == 31)
return 0;
bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR,
PCICFG_ENABLE | tag | reg);
data = bus_space_read_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_DATA);
bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR, 0);
return data;
}
static pcireg_t
giopci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
{
struct giopci_softc *sc = pc->cookie;
int bus, dev, func;
pcireg_t data;
if ((unsigned int)reg >= PCI_CONF_SIZE)
return (pcireg_t) -1;
pci_decompose_tag(pc, tag, &bus, &dev, &func);
if (bus != 0 || dev != 0 || func != 0)
return (0);
/* XXX - should just use bus_space_peek */
if (reg >= sc->sc_pci_len) {
DPRINTF(("giopci_conf_read: reg 0x%x out of bounds\n", reg));
return (0);
}
DPRINTF(("giopci_conf_read: reg 0x%x = 0x", reg));
data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
DPRINTF(("%08x\n", data));
return (data);
}
void
aapic_attach(struct device *parent, struct device *self, void *aux)
{
struct pci_attach_args *pa = aux;
int bus, dev, func;
pcitag_t tag;
pcireg_t reg;
printf("\n");
#if NIOAPIC > 0
if (nioapics == 0)
return;
#else
return;
#endif
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AMD8131_IOAPIC_CTL);
reg |= AMD8131_IOAEN;
pci_conf_write(pa->pa_pc, pa->pa_tag, AMD8131_IOAPIC_CTL, reg);
pci_decompose_tag(pa->pa_pc, pa->pa_tag, &bus, &dev, &func);
func = 0;
tag = pci_make_tag(pa->pa_pc, bus, dev, func);
reg = pci_conf_read(pa->pa_pc, tag, AMD8131_PCIX_MISC);
reg &= ~AMD8131_NIOAMODE;
pci_conf_write(pa->pa_pc, tag, AMD8131_PCIX_MISC, reg);
}
void
ht_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
{
struct ht_softc *sc = cpv;
int bus, dev, fcn;
uint32_t val;
val = PCITAG_OFFSET(tag);
#ifdef DEBUG
printf("ht_conf_write: tag=%x, offset=%x, data = %x\n",
val, offset, data);
#endif
pci_decompose_tag(NULL, tag, &bus, &dev, &fcn);
if (bus == 0 && dev == 0) {
val |= (offset << 2);
data = htole32(data);
bus_space_write_4(sc->sc_iot, sc->sc_config0_ioh, val, data);
bus_space_read_4(sc->sc_iot, sc->sc_config0_ioh, val);
} else if (bus == 0) {
/* XXX Why can we only access function 0? */
if (fcn > 0)
return;
val |= offset;
bus_space_write_4(sc->sc_memt, sc->sc_config0_memh, val, data);
bus_space_read_4(sc->sc_memt, sc->sc_config0_memh, val);
} else {
val |= offset;
bus_space_write_4(sc->sc_memt, sc->sc_config1_memh, val, data);
bus_space_read_4(sc->sc_memt, sc->sc_config1_memh, val);
}
}
void
pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
{
int bus;
if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) {
pci_decompose_tag(pc, tag, &bus, NULL, NULL);
if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) {
pci_mcfg_map_bus(bus);
bus_space_write_4(pci_mcfgt, pci_mcfgh[bus],
(tag.mode1 & 0x000ff00) << 4 | reg, data);
return;
}
}
PCI_CONF_LOCK();
switch (pci_mode) {
case 1:
outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
outl(PCI_MODE1_DATA_REG, data);
outl(PCI_MODE1_ADDRESS_REG, 0);
break;
case 2:
outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
outl(tag.mode2.port | reg, data);
outb(PCI_MODE2_ENABLE_REG, 0);
break;
default:
panic("pci_conf_write: mode not configured");
}
PCI_CONF_UNLOCK();
}
static void
uninorth_conf_write_v3(void *cookie, pcitag_t tag, int reg, pcireg_t data)
{
pci_chipset_tag_t pc = cookie;
int32_t *daddr = pc->pc_data;
int bus, dev, func, s;
uint32_t x;
if ((unsigned int)reg >= PCI_CONF_SIZE)
return;
/* UniNorth seems to have a 64bit data port */
if (reg & 0x04)
daddr++;
pci_decompose_tag(pc, tag, &bus, &dev, &func);
x = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 1;
/* Set extended register bits */
x |= (reg >> 8) << 28;
s = splhigh();
out32rb(pc->pc_addr, x);
in32rb(pc->pc_addr);
out32rb(daddr, data);
out32rb(pc->pc_addr, 0);
in32rb(pc->pc_addr);
splx(s);
}
void *
pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
int (*func)(void *), void *arg, const char *what)
{
void *ret;
int bus, dev;
int l = ih.line & APIC_INT_LINE_MASK;
pci_decompose_tag(pc, ih.tag, &bus, &dev, NULL);
#if NACPIPRT > 0
acpiprt_route_interrupt(bus, dev, ih.pin);
#endif
#if NIOAPIC > 0
if (l != -1 && ih.line & APIC_INT_VIA_APIC)
return (apic_intr_establish(ih.line, IST_LEVEL, level, func,
arg, what));
#endif
if (l == 0 || l >= ICU_LEN || l == 2)
panic("pci_intr_establish: bogus handle 0x%x", l);
ret = isa_intr_establish(NULL, l, IST_LEVEL, level, func, arg, what);
#if NPCIBIOS > 0
if (ret)
pci_intr_route_link(pc, &ih);
#endif
return (ret);
}
int
socpcic_intr_map(void *cpv, pcitag_t tag, int pin, int line,
pci_intr_handle_t *ihp)
{
struct socpcic_softc *sc = cpv;
int bus, dev, func;
int reg[4];
int *map;
int len;
pci_decompose_tag(&sc->sc_pc, tag, &bus, &dev, &func);
reg[0] = (dev << 11) | (func << 8);
reg[1] = reg[2] = 0;
reg[3] = pin;
map = sc->sc_map;
len = sc->sc_map_len;
while (len >= 7 * sizeof(int)) {
if ((reg[0] & sc->sc_map_mask[0]) == map[0] &&
(reg[1] & sc->sc_map_mask[1]) == map[1] &&
(reg[2] & sc->sc_map_mask[2]) == map[2] &&
(reg[3] & sc->sc_map_mask[3]) == map[3]) {
*ihp = map[5];
return (0);
}
len -= 7 * sizeof(int);
map += 7;
}
return (1);
}
void
nforce4_mpbios_fixup(pci_chipset_tag_t pc, pcitag_t tag)
{
pcireg_t reg;
int bus, pin;
pci_decompose_tag (pc, tag, &bus, NULL, NULL);
reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ2);
pin = (reg & NFORCE4_USB2_MASK) >> NFORCE4_USB2_SHIFT;
if (pin != 0)
mpbios_pin_fixup(bus, 2, PCI_INTERRUPT_PIN_B, pin);
pin = (reg & NFORCE4_SATA1_MASK) >> NFORCE4_SATA1_SHIFT;
if (pin != 0)
mpbios_pin_fixup(bus, 7, PCI_INTERRUPT_PIN_A, pin);
pin = (reg & NFORCE4_SATA2_MASK) >> NFORCE4_SATA2_SHIFT;
if (pin != 0)
mpbios_pin_fixup(bus, 8, PCI_INTERRUPT_PIN_A, pin);
reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ3);
pin = (reg & NFORCE4_USB1_MASK) >> NFORCE4_USB1_SHIFT;
if (pin != 0)
mpbios_pin_fixup(bus, 2, PCI_INTERRUPT_PIN_A, pin);
pin = (reg & NFORCE4_LAN_MASK) >> NFORCE4_LAN_SHIFT;
if (pin != 0)
mpbios_pin_fixup(bus, 10, PCI_INTERRUPT_PIN_A, pin);
}
void *
dec_eb164_pciide_compat_intr_establish(void *v, device_t dev,
const struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg)
{
pci_chipset_tag_t pc = pa->pa_pc;
void *cookie = NULL;
int bus, irq;
char buf[64];
pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
/*
* If this isn't PCI bus #0, all bets are off.
*/
if (bus != 0)
return (NULL);
irq = PCIIDE_COMPAT_IRQ(chan);
#if NSIO
cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO,
func, arg);
if (cookie == NULL)
return (NULL);
aprint_normal_dev(dev, "%s channel interrupting at %s\n",
PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq,
buf, sizeof(buf)));
#endif
return (cookie);
}
pcireg_t
pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
{
pcireg_t data;
int bus;
KASSERT((reg & 0x3) == 0);
if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) {
pci_decompose_tag(pc, tag, &bus, NULL, NULL);
if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) {
pci_mcfg_map_bus(bus);
data = bus_space_read_4(pci_mcfgt, pci_mcfgh[bus],
(tag & 0x000ff00) << 4 | reg);
return data;
}
}
PCI_CONF_LOCK();
outl(PCI_MODE1_ADDRESS_REG, tag | reg);
data = inl(PCI_MODE1_DATA_REG);
outl(PCI_MODE1_ADDRESS_REG, 0);
PCI_CONF_UNLOCK();
return data;
}
/*
* PCI Interrupt handling
*/
int
octeon_pcibus_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
#if 0
struct octeon_pcibus_softc *sc = pa->pa_pc->pc_intr_v;
#endif
int bus, dev, fn, pin;
*ihp = (pci_intr_handle_t)-1;
if (pa->pa_intrpin == 0) /* no interrupt needed */
return 1;
#ifdef DIAGNOSTIC
if (pa->pa_intrpin > 4) {
printf("%s: bad interrupt pin %d\n", __func__, pa->pa_intrpin);
return 1;
}
#endif
pci_decompose_tag(pa->pa_pc, pa->pa_tag, &bus, &dev, &fn);
if (pa->pa_bridgetag) {
pin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, dev);
*ihp = pa->pa_bridgeih[pin - 1];
} else {
if (bus == 0)
*ihp = octeon_pcibus_intr_map(dev, fn, pa->pa_intrpin);
if (*ihp == (pci_intr_handle_t)-1)
return 1;
}
return 0;
}
void *
api_up1000_pciide_compat_intr_establish(void *icv, struct device *dev,
struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg)
{
pci_chipset_tag_t pc = pa->pa_pc;
void *cookie = NULL;
int bus, irq;
pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
/*
* If this isn't PCI bus #0, all bets are off.
*/
if (bus != 0)
return (NULL);
irq = PCIIDE_COMPAT_IRQ(chan);
#if NSIO
cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO,
func, arg, dev->dv_xname);
if (cookie == NULL)
return (NULL);
#endif
return (cookie);
}
void
empb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)
{
uint32_t bus, dev, func;
struct empb_softc *sc;
int s;
sc = pc->cookie;
pci_decompose_tag(pc, tag, &bus, &dev, &func);
PCI_CONF_LOCK(s);
empb_switch_bridge(sc, BRIDGE_CONF);
bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah,
EMPB_CONF_DEV_STRIDE*dev + EMPB_CONF_FUNC_STRIDE*func + reg, val);
#ifdef EMPB_DEBUG_CONF
aprint_normal("empb conf write va: %lx, bus: %d, dev: %d, "
"func: %d, reg: %d -w-> data %x\n",
pc->pci_conf_datah, bus, dev, func, reg, val);
#endif /* EMPB_DEBUG_CONF */
empb_switch_bridge(sc, BRIDGE_IO);
PCI_CONF_UNLOCK(s);
}
static void
print_tag(pci_chipset_tag_t pc, pcitag_t tag)
{
int bus, dev, func;
pci_decompose_tag(pc, tag, &bus, &dev, &func);
printf("PCI: bus %d, device %d, function %d: ", bus, dev, func);
}
int
iq80321_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
struct i80321_softc *sc = pa->pa_pc->pc_intr_v;
int b, d, f;
uint32_t busno;
/*
* The IQ80321's interrupts are routed like so:
*
* XINT0 i82544 Gig-E
*
* XINT1 UART
*
* XINT2 INTA# from S-PCI-X slot
*
* XINT3 INTB# from S-PCI-X slot
*/
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, &b, &d, &f);
/* No mappings for devices not on our bus. */
if (b != busno)
goto no_mapping;
switch (d) {
case 4: /* i82544 Gig-E */
if (pa->pa_intrpin == 1) {
*ihp = ICU_INT_XINT(0);
return (0);
}
goto no_mapping;
case 6: /* S-PCI-X slot */
if (pa->pa_intrpin == 1) {
*ihp = ICU_INT_XINT(2);
return (0);
}
if (pa->pa_intrpin == 2) {
*ihp = ICU_INT_XINT(3);
return (0);
}
goto no_mapping;
default:
no_mapping:
printf("iq80321_pci_intr_map: no mapping for %d/%d/%d\n",
pa->pa_bus, pa->pa_device, pa->pa_function);
return (1);
}
return (0);
}
void
via8237_mpbios_fixup(pci_chipset_tag_t pc, pcitag_t tag)
{
int bus;
pci_decompose_tag (pc, tag, &bus, NULL, NULL);
/* SATA is hardwired to APIC pin 20. */
mpbios_pin_fixup(bus, 15, 2, 20);
}
pcireg_t
ttwoga_conf_read(void *cpv, pcitag_t tag, int offset)
{
struct ttwoga_config *tcp = cpv;
pcireg_t *datap, data;
int b, d, f, ba;
paddr_t addr;
uint64_t old_hae3;
if ((unsigned int)offset >= PCI_CONF_SIZE)
return (pcireg_t) -1;
pci_decompose_tag(&tcp->tc_pc, tag, &b, &d, &f);
addr = b ? tag : ttwoga_make_type0addr(d, f);
if (addr == (paddr_t)-1)
return ((pcireg_t) -1);
TTWOGA_CONF_LOCK();
alpha_mb();
old_hae3 = T2GA(tcp, T2_HAE0_3) & ~HAE0_3_PCA;
T2GA(tcp, T2_HAE0_3) =
old_hae3 | ((b ? 1UL : 0UL) << HAE0_3_PCA_SHIFT);
alpha_mb();
alpha_mb();
datap =
(pcireg_t *)ALPHA_PHYS_TO_K0SEG(tcp->tc_sysmap->tsmap_conf_base |
addr << 5UL | /* address shift */
(offset & ~0x03) << 5UL | /* address shift */
0x3 << 3UL); /* 4-byte, size shift */
data = (pcireg_t)-1;
if (!(ba = badaddr(datap, sizeof *datap)))
data = *datap;
alpha_mb();
T2GA(tcp, T2_HAE0_3) = old_hae3;
alpha_mb();
alpha_mb();
alpha_pal_draina();
alpha_mb();
alpha_mb();
TTWOGA_CONF_UNLOCK();
#if 0
printf("ttwoga_conf_read: tag 0x%lx, reg 0x%x -> 0x%x @ %p%s\n",
tag, offset, data, datap, ba ? " (badaddr)" : "");
#endif
return (data);
}
void
pciaddr_print_devid(pci_chipset_tag_t pc, pcitag_t tag)
{
int bus, device, function;
pcireg_t id;
id = pci_conf_read(pc, tag, PCI_ID_REG);
pci_decompose_tag(pc, tag, &bus, &device, &function);
printf("%03d:%02d:%d %04x:%04x\n", bus, device, function,
PCI_VENDOR(id), PCI_PRODUCT(id));
}
pcireg_t
pci_conf_read( pci_chipset_tag_t pc, pcitag_t tag,
int reg)
{
pcireg_t data;
int s;
KASSERT((reg & 0x3) == 0);
#if defined(__i386__) && defined(XBOX)
if (arch_i386_is_xbox) {
int bus, dev, fn;
pci_decompose_tag(pc, tag, &bus, &dev, &fn);
if (bus == 0 && dev == 0 && (fn == 1 || fn == 2))
return (pcireg_t)-1;
}
#endif
#ifndef PCI_CONF_MODE
switch (pci_mode) {
case 1:
goto mode1;
case 2:
goto mode2;
default:
panic("pci_conf_read: mode not configured");
}
#endif
#if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1)
#ifndef PCI_CONF_MODE
mode1:
#endif
PCI_CONF_LOCK(s);
outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
data = inl(PCI_MODE1_DATA_REG);
outl(PCI_MODE1_ADDRESS_REG, 0);
PCI_CONF_UNLOCK(s);
return data;
#endif
#if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2)
#ifndef PCI_CONF_MODE
mode2:
#endif
PCI_CONF_LOCK(s);
outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
data = inl(tag.mode2.port | reg);
outb(PCI_MODE2_ENABLE_REG, 0);
PCI_CONF_UNLOCK(s);
return data;
#endif
}
int
pci_conf_size(pci_chipset_tag_t pc, pcitag_t tag)
{
int bus;
if (pci_mcfg_addr) {
pci_decompose_tag(pc, tag, &bus, NULL, NULL);
if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus)
return PCIE_CONFIG_SPACE_SIZE;
}
return PCI_CONFIG_SPACE_SIZE;
}
u_int32_t
mpc_gen_config_reg(void *cpv, pcitag_t tag, int offset)
{
struct pcibr_config *cp = cpv;
unsigned int bus, dev, fcn;
u_int32_t reg, val = PCITAG_OFFSET(tag);
pci_decompose_tag(cpv, tag, &bus, &dev, &fcn);
if (cp->config_type & 4) {
reg = val | offset | 1;
reg |= (offset >> 8) << 28;
} else if (cp->config_type & 1) {
int
iq80321_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
struct i80321_softc *sc = pa->pa_pc->pc_intr_v;
int b, d, f;
uint32_t busno;
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, &b, &d, &f);
/* No mappings for devices not on our bus. */
if (b != busno)
goto no_mapping;
switch (d) {
case 0: /* i82546EB Dual GigE */
/*
* This is a dual-function chip which uses INTA and INTB,
* connected to XINT0 and XINT1 respectively.
*/
if (f != 0 && f != 1)
goto no_mapping;
*ihp = ICU_INT_XINT(f);
return (0);
case 1: /* i31244 S-ATA Interface */
*ihp = ICU_INT_XINT(2);
return (0);
case 2: /* Symbios Logic 53c1010 SCSI Controllers */
case 3:
/*
* Both controllers share a single pin
*/
*ihp = ICU_INT_XINT(3);
return (0);
default:
no_mapping:
printf("iq80321_pci_intr_map: no mapping for %d/%d/%d/%c\n",
pa->pa_bus, pa->pa_device, pa->pa_function,
'@' + pa->pa_intrpin);
return (1);
}
return (0);
}
void
ttwoga_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
{
struct ttwoga_config *tcp = cpv;
pcireg_t *datap;
int b, d, f;
paddr_t addr;
uint64_t old_hae3;
if ((unsigned int)offset >= PCI_CONF_SIZE)
return;
pci_decompose_tag(&tcp->tc_pc, tag, &b, &d, &f);
addr = b ? tag : ttwoga_make_type0addr(d, f);
if (addr == (paddr_t)-1)
return;
TTWOGA_CONF_LOCK();
alpha_mb();
old_hae3 = T2GA(tcp, T2_HAE0_3) & ~HAE0_3_PCA;
T2GA(tcp, T2_HAE0_3) =
old_hae3 | ((b ? 1UL : 0UL) << HAE0_3_PCA_SHIFT);
alpha_mb();
alpha_mb();
datap =
(pcireg_t *)ALPHA_PHYS_TO_K0SEG(tcp->tc_sysmap->tsmap_conf_base |
addr << 5UL | /* address shift */
(offset & ~0x03) << 5UL | /* address shift */
0x3 << 3UL); /* 4-byte, size shift */
alpha_mb();
*datap = data;
alpha_mb();
alpha_mb();
alpha_mb();
T2GA(tcp, T2_HAE0_3) = old_hae3;
alpha_mb();
alpha_mb();
TTWOGA_CONF_UNLOCK();
#if 0
printf("ttwoga_conf_write: tag 0x%lx, reg 0x%x -> 0x%x @ %p\n",
tag, offset, data, datap);
#endif
}
int
iq80321_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
struct i80321_softc *sc = pa->pa_pc->pc_intr_v;
int b, d, f;
uint32_t busno;
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, &b, &d, &f);
/* No mappings for devices not on our bus. */
if (b != busno)
goto no_mapping;
switch (d) {
case 1: /* PCIX-PCIX bridge */
/*
* The S-ATA chips are behind the bridge, and all of
* the S-ATA interrupts are wired together.
*/
*ihp = ICU_INT_XINT(2);
return (0);
case 2: /* PCI slot */
/* All pins are wired together. */
*ihp = ICU_INT_XINT(3);
return (0);
case 3: /* i82546 dual Gig-E */
if (pa->pa_intrpin == 1 || pa->pa_intrpin == 2) {
*ihp = ICU_INT_XINT(0);
return (0);
}
goto no_mapping;
default:
no_mapping:
printf("iq80321_pci_intr_map: no mapping for %d/%d/%d/%c\n",
pa->pa_bus, pa->pa_device, pa->pa_function,
'@' + pa->pa_intrpin);
return (1);
}
return (0);
}
int
pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid,
int *offset, pcireg_t *value)
{
pcireg_t reg;
unsigned int ofs;
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))
return 0;
/* Determine the Capability List Pointer register to start with. */
reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
switch (PCI_HDRTYPE_TYPE(reg)) {
case 0: /* standard device header */
case 1: /* PCI-PCI bridge header */
ofs = PCI_CAPLISTPTR_REG;
break;
case 2: /* PCI-CardBus Bridge header */
ofs = PCI_CARDBUS_CAPLISTPTR_REG;
break;
default:
return 0;
}
ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs));
while (ofs != 0) {
if ((ofs & 3) || (ofs < 0x40)) {
int bus, device, function;
pci_decompose_tag(pc, tag, &bus, &device, &function);
printf("Skipping broken PCI header on %d:%d:%d\n",
bus, device, function);
break;
}
reg = pci_conf_read(pc, tag, ofs);
if (PCI_CAPLIST_CAP(reg) == capid) {
if (offset)
*offset = ofs;
if (value)
*value = reg;
return 1;
}
ofs = PCI_CAPLIST_NEXT(reg);
}
return 0;
}
int
vrc4172pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
pci_chipset_tag_t pc = pa->pa_pc;
pcitag_t intrtag = pa->pa_intrtag;
int bus, dev, func;
pci_decompose_tag(pc, intrtag, &bus, &dev, &func);
DPRINTF(("%s(%d, %d, %d): line = %d, pin = %d\n", pc->pc_dev->dv_xname,
bus, dev, func, pa->pa_intrline, pa->pa_intrpin));
*ihp = CONFIG_HOOK_PCIINTR_ID(bus, dev, func);
return (0);
}
int
api_up1000_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
pcitag_t bustag = pa->pa_intrtag;
int buspin = pa->pa_intrpin, line = pa->pa_intrline;
pci_chipset_tag_t pc = pa->pa_pc;
int bus, device, function;
if (buspin == 0) {
/* No IRQ used. */
return 1;
}
if (buspin > 4) {
printf("api_up1000_intr_map: bad interrupt pin %d\n",
buspin);
return 1;
}
pci_decompose_tag(pc, bustag, &bus, &device, &function);
/*
* The console places the interrupt mapping in the "line" value.
* A value of (char)-1 indicates there is no mapping.
*/
if (line == 0xff) {
printf("api_up1000_intr_map: no mapping for %d/%d/%d\n",
bus, device, function);
return (1);
}
/* XXX Check for 0? */
if (line > 15) {
#ifdef DIAGNOSTIC
printf("api_up1000_intr_map: ISA IRQ too large (%d)\n",
line);
#endif
return (1);
}
if (line == 2) {
#ifdef DIAGNOSTIC
printf("api_up1000_intr_map: changed IRQ 2 to IRQ 9\n");
#endif
line = 9;
}
*ihp = line;
return (0);
}
void
mppb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)
{
uint32_t bus, dev, func;
pci_decompose_tag(pc, tag, &bus, &dev, &func);
bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah,
(MPPB_CONF_STRIDE*dev) + reg, val);
#ifdef MPPB_DEBUG_CONF
aprint_normal("mppb conf write va: %lx, bus: %d, dev: %d, "
"func: %d, reg: %d -w-> data %x\n",
pc->pci_conf_datah, bus, dev, func, reg, val);
#endif /* MPPB_DEBUG_CONF */
}
