static void vx900_lpc_interrupt_stuff(device_t dev)
{
/* Enable setting trigger mode through 0x4d0, and 0x4d1 ports
* And enable I/O recovery time */
pci_mod_config8(dev, 0x40, 0, (1 << 2) | (1 << 6));
/* Set serial IRQ frame width to 6 PCI cycles (recommended by VIA)
* And enable serial IRQ */
pci_mod_config8(dev, 0x52, 3 << 0, (1 << 3) | (1 << 0));
/* Disable IRQ12 storm FIXME: bad comment */
pci_mod_config8(dev, 0x51, (1 << 2), 0);
pci_write_config8(dev, 0x4c, (1 << 6));
/* FIXME: Do we really need this? SeaBIOS/linux runs fine without it.
* Is this something the payload/OS should do, or is it safe for us to
* do it? */
/* Get the IRQs up and running */
setup_i8259();
vx900_lpc_dma_setup(dev);
/* The IOAPIC is special, and we treat it separately */
vx900_lpc_ioapic_setup(dev);
}
static void vx900_cpu_bus_preram_setup(void)
{
/* Faster CPU to DRAM Cycle */
pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08);
/* CPU Interface Control - Basic Options */
pci_mod_config8(HOST_BUS, 0x51, 0, 0x6c);
/*CPU Interface Control - Advanced Options */
pci_write_config8(HOST_BUS, 0x52, 0xc7);
/* Enable 8QW burst and 4QW request merging [4] and [2]
* and special mode for read cycles bit[3] */
pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 4) | (1 << 2) | (1 << 3));
/* High priority upstream requests on V4 bus */
pci_write_config8(HOST_BUS, 0x56, 0x03);
/* CPU to DRAM extra 1T access control */
pci_mod_config8(HOST_BUS, 0x59, 0x00, (1 << 2));
/* Queue reordering */
pci_mod_config8(HOST_BUS, 0x5f, 0x00, (1 << 6));
/* Only Write cycle of CPU->GFXCTL will flush the CPU->Memory FIFO */
pci_mod_config8(HOST_BUS, 0x98, 0x00, 0x60);
/* 1T delay for data on CPU bus */
pci_write_config8(HOST_BUS, 0x9e, 0x0e);
/* Arbitrate ownership of DRAM controller a few cycles earlier */
pci_mod_config8(HOST_BUS, 0x9f, 0x00, (1 << 7));
/* Write retire policy */
pci_write_config8(HOST_BUS, 0x5d, 0xa2);
/* Occupancy timer */
pci_write_config8(HOST_BUS, 0x53, 0x44);
/* Medium Threshold for Write Retire Policy - 6 requests */
pci_mod_config8(HOST_BUS, 0x56, 0x00, 0x60);
/* Bandwidth timer */
pci_write_config8(HOST_BUS, 0x5e, 0x44);
}
void pirq_assign_irqs(const u8 * pirq)
{
device_t lpc;
lpc = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX900_LPC, 0);
/* Take care of INTA -> INTD */
pci_mod_config8(lpc, 0x55, (0xf << 4), pirq[0] << 4);
pci_write_config8(lpc, 0x56, pirq[1] | (pirq[2] << 4));
pci_write_config8(lpc, 0x57, pirq[3] << 4);
/* Enable INTE -> INTH to be on separate IRQs */
pci_mod_config8(lpc, 0x46, 0, 1 << 4);
/* Now do INTE -> INTH */
pci_write_config8(lpc, 0x44, pirq[4] | (pirq[5] << 4));
pci_write_config8(lpc, 0x45, pirq[6] | (pirq[7] << 4));
}
static void vx900_lpc_dma_setup(device_t dev)
{
/* These are the steps recommended by VIA in order to get DMA running */
/* Enable Positive South Module PCI Cycle Decoding */
/* FIXME: Setting this seems to hang our system */
//pci_mod_config8(dev, 0x58, 0, 1<<4);
/* Positive decoding for ROM + APIC + On-board IO ports */
pci_mod_config8(dev, 0x6c, 0, (1 << 2) | (1 << 3) | (1 << 7));
/* Enable DMA channels. BIOS guide recommends DMA channel 2 off */
pci_write_config8(dev, 0x53, 0xfb);
/* Disable PCI/DMA Memory Cycles Output to PCI Bus */
pci_mod_config8(dev, 0x5b, (1 << 5), 0);
/* DMA bandwidth control - Improved bandwidth */
pci_write_config8(dev, 0x53, 0xff);
/* ISA Positive Decoding control */
pci_write_config8(dev, 0x6d, 0xdf);
pci_write_config8(dev, 0x6e, 0x98);
pci_write_config8(dev, 0x6f, 0x30);
}
static void vx900_lpc_misc_stuff(device_t dev)
{
char extint;
u8 val;
struct northbridge_via_vx900_config *nb = (void *)dev->chip_info;
/* GPIO 11,10 to SATALED [1,0] */
pci_mod_config8(dev, 0xe4, 0, 1 << 0);
/* Route the external interrupt line */
extint = nb->ext_int_route_to_pirq;
if (extint < 'A' || extint > 'H') {
printk(BIOS_WARNING, "Invalid PIRQ%c for external interrupt\n",
extint);
} else {
printk(BIOS_INFO, "Routing external interrupt to PIRQ%c\n",
extint);
val = extint - 'A';
val |= (1 << 3); /* bit3 enables the external int */
pci_mod_config8(dev, 0x55, 0xf, val);
}
}
/**
* \brief Disables 'shadowing' of system ROM
*
* Disable unnecessary shadowing of the ROM in the first 1MB of address space.
* coreboot runs in 32-bit mode from the start. Shadowing only gets in the way.
* This function frees the entire 640k-1M range for DRAM. VGA may still use
* the 640k-768k range, if enabled later.
*/
void vx900_disable_legacy_rom_shadow(void)
{
pci_write_config8(MCU, 0x80, 0xff); /* LPC ROM 768k - 832k */
pci_write_config8(MCU, 0x81, 0xff); /* LPC ROM 832k - 896k */
pci_write_config8(MCU, 0x82, 0xff); /* LPC ROM 896k - 960k */
/* LPC ROM 960k - 1M * SMRAM: 640k - 768k */
pci_write_config8(MCU, 0x83, 0x31);
/* Bits 6:0 are the ROM shadow on top of 4G, so leave those untouched */
pci_mod_config8(LPC, 0x41, 1 << 7, 0); /* LPC ROM 896k - 960k */
pci_write_config8(SNMIC, 0x61, 0); /* 768k - 832k */
pci_write_config8(SNMIC, 0x62, 0); /* 832k - 896k */
pci_write_config8(SNMIC, 0x63, 0); /* 896k - 1M */
pci_write_config8(SNMIC, 0x64, 0); /* 896k - 960k */
}
/**
*\brief VX900: Set up the south module IOAPIC (for the ISA/LPC bus)
*
* Enable the IOAPIC in the south module, and properly set it up.
* \n
* This is the hardware specific initialization for the IOAPIC, and complements
* the setup done by the generic IOAPIC driver. In order for the IOAPIC to work
* properly, it _must_ be declared in devicetree.cb .
* \n
* We are assuming this is called before the drivers/generic/ioapic code,
* which should be the case if devicetree.cb is set up properly.
*/
static void vx900_lpc_ioapic_setup(device_t dev)
{
/* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb
* If it's not, then the generic ioapic driver will not set it up
* correctly, and the MP table will not be correctly generated */
device_t ioapic;
for (ioapic = dev->next; ioapic; ioapic = ioapic->next) {
if (ioapic->path.type == DEVICE_PATH_IOAPIC)
break;
}
/* You did put an IOAPIC in devicetree.cb, didn't you? */
if (ioapic == 0) {
/* We don't have enough info to set up the IOAPIC */
printk(BIOS_ERR, "ERROR: South module IOAPIC not found. "
"Check your devicetree.cb\n");
return;
}
/* Found an IOAPIC, now we need to make sure it's the right one */
ioapic_config_t *config = (ioapic_config_t *) ioapic->chip_info;
if (!config->have_isa_interrupts) {
/* Umh, is this the right IOAPIC ? */
printk(BIOS_ERR, "ERROR: South module IOAPIC not carrying ISA "
"interrupts. Check your devicetree.cb\n");
printk(BIOS_ERR, "Will not initialize this IOAPIC.\n");
return;
}
/* The base address of this IOAPIC _must_ be at 0xfec00000.
* Don't move this value to a #define, as people might think it's
* configurable. It is not. */
const void *base = config->base;
if (base != (void *)0xfec00000) {
printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at "
"0xfec00000\n but we found it at %p\n", base);
return;
}
printk(BIOS_DEBUG, "VX900 LPC: Setting up the south module IOAPIC.\n");
/* Enable IOAPIC
* So much work for one line of code. Talk about bloat :)
* The 8259 PIC should still work even if the IOAPIC is enabled, so
* there's no crime in enabling the IOAPIC here. */
pci_mod_config8(dev, 0x58, 0, 1 << 6);
}
/**
* \brief Disables the VX900 integrated graphics controller
*
* Disable the graphics controller entirely. It will no longer be visible as a
* PCI device.
*/
void vx900_disable_gfx(void)
{
/* Disable GFX */
pci_mod_config8(MCU, 0xa1, 1 << 7, 0);
}