static void
ehci_pci_via_quirk(device_t self)
{
uint32_t val;
if ((pci_get_device(self) == 0x3104) &&
((pci_get_revid(self) & 0xf0) == 0x60)) {
/* Correct schedule sleep time to 10us */
val = pci_read_config(self, 0x4b, 1);
if (val & 0x20)
return;
val |= 0x20;
pci_write_config(self, 0x4b, val, 1);
device_printf(self, "VIA-quirk applied\n");
}
}
void
iwm_apm_config(struct iwm_softc *sc)
{
uint16_t reg;
reg = pci_read_config(sc->sc_dev, PCIER_LINK_CTL, sizeof(reg));
if (reg & PCIEM_LINK_CTL_ASPMC_L1) {
/* Um the Linux driver prints "Disabling L0S for this one ... */
IWM_SETBITS(sc, IWM_CSR_GIO_REG,
IWM_CSR_GIO_REG_VAL_L0S_ENABLED);
} else {
/* ... and "Enabling" here */
IWM_CLRBITS(sc, IWM_CSR_GIO_REG,
IWM_CSR_GIO_REG_VAL_L0S_ENABLED);
}
}
static int
i965_do_reset(struct drm_device *dev, u8 flags)
{
u8 gdrst;
/*
* Set the domains we want to reset (GRDOM/bits 2 and 3) as
* well as the reset bit (GR/bit 0). Setting the GR bit
* triggers the reset; when done, the hardware will clear it.
*/
gdrst = pci_read_config(dev->device, I965_GDRST, 1);
pci_write_config(dev->device, I965_GDRST, gdrst | flags | 0x1, 1);
return (_intel_wait_for(dev, i965_reset_complete(dev), 500, 1,
"915rst"));
}
/*
* Set the SYSTEM_IDLE_TIMEOUT to 80 ns on nForce2 systems to work
* around a hang that is triggered when the CPU generates a very fast
* CONNECT/HALT cycle sequence. Specifically, the hang can result in
* the lapic timer being stopped.
*
* This requires changing the value for config register at offset 0x6c
* for the Host-PCI bridge at bus/dev/function 0/0/0:
*
* Chip Current Value New Value
* ---- ---------- ----------
* C17 0x1F0FFF01 0x1F01FF01
* C18D 0x9F0FFF01 0x9F01FF01
*
* We do this by always clearing the bits in 0x000e0000.
*
* See also: http://lkml.org/lkml/2004/5/3/157
*/
static void
fixc1_nforce2(device_t dev)
{
uint32_t val;
if (pci_get_bus(dev) == 0 && pci_get_slot(dev) == 0 &&
pci_get_function(dev) == 0) {
val = pci_read_config(dev, 0x6c, 4);
if (val & 0x000e0000) {
device_printf(dev,
"correcting nForce2 C1 CPU disconnect hangs\n");
val &= ~0x000e0000;
pci_write_config(dev, 0x6c, val, 4);
}
}
}
static int
mptable_pcib_probe(device_t dev)
{
int bus;
if ((pci_get_class(dev) != PCIC_BRIDGE) ||
(pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
return (ENXIO);
bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
if (bus == 0)
return (ENXIO);
if (mptable_pci_probe_table(bus) != 0)
return (ENXIO);
device_set_desc(dev, "MPTable PCI-PCI bridge");
return (-1000);
}
static inline void
agg_initcodec(struct agg_info* ess)
{
u_int16_t data;
if (bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL)
& RINGBUS_CTRL_ACLINK_ENABLED) {
bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
DELAY(104); /* 20.8us * (4 + 1) */
}
/* XXX - 2nd codec should be looked at. */
bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
RINGBUS_CTRL_AC97_SWRESET);
DELAY(2);
bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
RINGBUS_CTRL_ACLINK_ENABLED);
DELAY(21);
agg_rdcodec(NULL, ess, 0);
if (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
& CODEC_STAT_MASK) {
bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
DELAY(21);
/* Try cold reset. */
device_printf(ess->dev, "will perform cold reset.\n");
data = bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR);
if (pci_read_config(ess->dev, 0x58, 2) & 1)
data |= 0x10;
data |= 0x009 &
~bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DATA);
bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0xff6);
bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
data | 0x009);
bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x000);
DELAY(2);
bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x001);
DELAY(1);
bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x009);
DELAY(500000);
bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, data);
DELAY(84); /* 20.8us * 4 */
bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
RINGBUS_CTRL_ACLINK_ENABLED);
DELAY(21);
}
}
static int
clkrun_hack(int run)
{
#ifdef __i386__
devclass_t pci_devclass;
device_t *pci_devices, *pci_children, *busp, *childp;
int pci_count = 0, pci_childcount = 0;
int i, j, port;
u_int16_t control;
bus_space_tag_t btag;
if ((pci_devclass = devclass_find("pci")) == NULL) {
return ENXIO;
}
devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
pci_childcount = 0;
if (device_get_children(*busp, &pci_children, &pci_childcount))
continue;
for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
/* XXX */
btag = X86_BUS_SPACE_IO;
control = bus_space_read_2(btag, 0x0, port);
control &= ~0x2000;
control |= run? 0 : 0x2000;
bus_space_write_2(btag, 0x0, port, control);
free(pci_devices, M_TEMP);
free(pci_children, M_TEMP);
return 0;
}
}
free(pci_children, M_TEMP);
}
free(pci_devices, M_TEMP);
return ENXIO;
#else
return 0;
#endif
}
static int
ichss_attach(device_t dev)
{
struct ichss_softc *sc;
uint16_t ss_en;
sc = device_get_softc(dev);
sc->dev = dev;
sc->bm_rid = 0;
sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid,
RF_ACTIVE);
if (sc->bm_reg == NULL) {
device_printf(dev, "failed to alloc BM arb register\n");
return (ENXIO);
}
sc->ctrl_rid = 1;
sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
&sc->ctrl_rid, RF_ACTIVE);
if (sc->ctrl_reg == NULL) {
device_printf(dev, "failed to alloc control register\n");
bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid,
sc->bm_reg);
return (ENXIO);
}
/* Activate SpeedStep control if not already enabled. */
ss_en = pci_read_config(ich_device, ICHSS_PMCFG_OFFSET, sizeof(ss_en));
if ((ss_en & ICHSS_ENABLE) == 0) {
device_printf(dev, "enabling SpeedStep support\n");
pci_write_config(ich_device, ICHSS_PMCFG_OFFSET,
ss_en | ICHSS_ENABLE, sizeof(ss_en));
}
/* Setup some defaults for our exported settings. */
sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
sc->sets[0].lat = 1000;
sc->sets[0].dev = dev;
sc->sets[1] = sc->sets[0];
cpufreq_register(dev);
return (0);
}
static int
tws_setup_irq(struct tws_softc *sc)
{
int messages;
u_int16_t cmd;
cmd = pci_read_config(sc->tws_dev, PCIR_COMMAND, 2);
switch(sc->intr_type) {
case TWS_INTx :
cmd = cmd & ~0x0400;
pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
sc->irqs = 1;
sc->irq_res_id[0] = 0;
sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
&sc->irq_res_id[0], RF_SHAREABLE | RF_ACTIVE);
if ( ! sc->irq_res[0] )
return(FAILURE);
if ( tws_setup_intr(sc, sc->irqs) == FAILURE )
return(FAILURE);
device_printf(sc->tws_dev, "Using legacy INTx\n");
break;
case TWS_MSI :
cmd = cmd | 0x0400;
pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
sc->irqs = 1;
sc->irq_res_id[0] = 1;
messages = 1;
if (pci_alloc_msi(sc->tws_dev, &messages) != 0 ) {
TWS_TRACE(sc, "pci alloc msi fail", 0, messages);
return(FAILURE);
}
sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
&sc->irq_res_id[0], RF_SHAREABLE | RF_ACTIVE);
if ( !sc->irq_res[0] )
return(FAILURE);
if ( tws_setup_intr(sc, sc->irqs) == FAILURE )
return(FAILURE);
device_printf(sc->tws_dev, "Using MSI\n");
break;
}
return(SUCCESS);
}
static void
ehci_pci_givecontroller(device_t self)
{
#if 0
ehci_softc_t *sc = device_get_softc(self);
u_int32_t cparams, eec;
int eecp;
cparams = EREAD4(sc, EHCI_HCCPARAMS);
for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
eecp = EHCI_EECP_NEXT(eec)) {
eec = pci_read_config(self, eecp, 4);
if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP)
continue;
pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 0, 1);
}
#endif
}
int
__haiku_disable_interrupts(device_t dev)
{
struct bge_softc *sc = device_get_softc(dev);
uint32 notInterrupted = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4)
& BGE_PCISTATE_INTR_STATE;
// bit of a strange register name. a nonzero actually means
// it is _not_ interrupted by the network chip
if (notInterrupted)
return 0;
BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
return 1;
}
static bus_size_t
bhndb_pci_sprom_size(struct bhndb_pci_softc *sc)
{
const struct bhndb_regwin *sprom_win;
uint32_t sctl;
bus_size_t sprom_sz;
sprom_win = bhndb_pci_sprom_regwin(sc);
/* PCI_V2 and later devices map SPROM/OTP via ChipCommon */
if (sprom_win == NULL)
return (0);
/* Determine SPROM size */
sctl = pci_read_config(sc->parent, BHNDB_PCI_SPROM_CONTROL, 4);
if (sctl & BHNDB_PCI_SPROM_BLANK)
return (0);
switch (sctl & BHNDB_PCI_SPROM_SZ_MASK) {
case BHNDB_PCI_SPROM_SZ_1KB:
sprom_sz = (1 * 1024);
break;
case BHNDB_PCI_SPROM_SZ_4KB:
sprom_sz = (4 * 1024);
break;
case BHNDB_PCI_SPROM_SZ_16KB:
sprom_sz = (16 * 1024);
break;
case BHNDB_PCI_SPROM_SZ_RESERVED:
default:
device_printf(sc->dev, "invalid PCI sprom size 0x%x\n", sctl);
return (0);
}
/* If the device has a larger SPROM than can be addressed via our SPROM
* register window, the SPROM image data will still be located within
* the window's addressable range */
sprom_sz = MIN(sprom_sz, sprom_win->win_size);
return (sprom_sz);
}
/*
* Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV
* capability. This bit is only writeable on the lowest-numbered PF but
* affects all PFs on the device.
*/
static int
pci_iov_set_ari(device_t bus)
{
device_t lowest;
device_t *devlist;
int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func;
uint16_t iov_ctl;
/* If ARI is disabled on the downstream port there is nothing to do. */
if (!PCIB_ARI_ENABLED(device_get_parent(bus)))
return (0);
error = device_get_children(bus, &devlist, &devcount);
if (error != 0)
return (error);
lowest = NULL;
for (i = 0; i < devcount; i++) {
if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) {
dev_func = pci_get_function(devlist[i]);
if (lowest == NULL || dev_func < lowest_func) {
lowest = devlist[i];
lowest_func = dev_func;
lowest_pos = iov_pos;
}
}
}
/*
* If we called this function some device must have the SR-IOV
* capability.
*/
KASSERT(lowest != NULL,
("Could not find child of %s with SR-IOV capability",
device_get_nameunit(bus)));
iov_ctl = pci_read_config(lowest, iov_pos + PCIR_SRIOV_CTL, 2);
iov_ctl |= PCIM_SRIOV_ARI_EN;
pci_write_config(lowest, iov_pos + PCIR_SRIOV_CTL, iov_ctl, 2);
free(devlist, M_TEMP);
return (0);
}
static void
bfe_pci_setup( struct bfe_softc * sc, u_int32_t cores )
{
u_int32_t bar_orig, pci_rev, val;
bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
val = CSR_READ_4(sc, BFE_SBINTVEC);
val |= cores;
CSR_WRITE_4(sc, BFE_SBINTVEC, val);
val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
}
static int
ata_jmicron_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
device_t child;
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
/* do we have multiple PCI functions ? */
if (pci_read_config(dev, 0xdf, 1) & 0x40) {
/* are we on the AHCI part ? */
if (ata_ahci_chipinit(dev) != ENXIO)
return 0;
/* otherwise we are on the PATA part */
ctlr->ch_attach = ata_jmicron_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_generic_reset;
ctlr->setmode = ata_jmicron_setmode;
ctlr->channels = ctlr->chip->cfg2;
}
else {
/* set controller configuration to a combined setup we support */
pci_write_config(dev, 0x40, 0x80c0a131, 4);
pci_write_config(dev, 0x80, 0x01200000, 4);
/* Create AHCI subdevice if AHCI part present. */
if (ctlr->chip->cfg1) {
child = device_add_child(dev, NULL, -1);
if (child != NULL) {
device_set_ivars(child, (void *)(intptr_t)-1);
bus_generic_attach(dev);
}
}
ctlr->ch_attach = ata_jmicron_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_generic_reset;
ctlr->setmode = ata_jmicron_setmode;
ctlr->channels = ctlr->chip->cfg2;
}
return 0;
}
static int
si_pci_probe(device_t dev)
{
const char *desc = NULL;
switch (pci_get_devid(dev)) {
case 0x400011cb:
desc = "Specialix SI/XIO PCI host card";
break;
case 0x200011cb:
if (pci_read_config(dev, SIJETSSIDREG, 4) == 0x020011cb)
desc = "Specialix SX PCI host card";
break;
}
if (desc) {
device_set_desc(dev, desc);
return 0;
}
return ENXIO;
}
static void
fixwsc_natoma(device_t dev)
{
int pmccfg;
pmccfg = pci_read_config(dev, 0x50, 2);
#if defined(SMP)
if (pmccfg & 0x8000) {
printf("Correcting Natoma config for SMP\n");
pmccfg &= ~0x8000;
pci_write_config(dev, 0x50, pmccfg, 2);
}
#else
if ((pmccfg & 0x8000) == 0) {
printf("Correcting Natoma config for non-SMP\n");
pmccfg |= 0x8000;
pci_write_config(dev, 0x50, pmccfg, 2);
}
#endif
}
void pci_msi_set_vector(u16 bdf, unsigned int vector)
{
int cap = pci_find_cap(bdf, PCI_CAP_MSI);
u16 ctl, data;
if (cap < 0)
return;
pci_write_config(bdf, cap + 0x04, 0xfee00000 | (cpu_id() << 12), 4);
ctl = pci_read_config(bdf, cap + 0x02, 2);
if (ctl & (1 << 7)) {
pci_write_config(bdf, cap + 0x08, 0, 4);
data = cap + 0x0c;
} else
data = cap + 0x08;
pci_write_config(bdf, data, vector, 2);
pci_write_config(bdf, cap + 0x02, 0x0001, 2);
}
static void
ata_amd_setmode(device_t dev, int mode)
{
device_t gparent = GRANDPARENT(dev);
struct ata_pci_controller *ctlr = device_get_softc(gparent);
struct ata_channel *ch = device_get_softc(device_get_parent(dev));
struct ata_device *atadev = device_get_softc(dev);
u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
int modes[7] = { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 };
int devno = (ch->unit << 1) + atadev->unit;
int reg = 0x53 - devno;
int error;
mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
if (ctlr->chip->cfg1 & AMD_CABLE) {
if (mode > ATA_UDMA2 &&
!(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
ata_print_cable(dev, "controller");
mode = ATA_UDMA2;
}
}
else
mode = ata_check_80pin(dev, mode);
error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
if (bootverbose)
device_printf(dev, "%ssetting %s on %s chip\n",
(error) ? "FAILURE " : "", ata_mode2str(mode),
ctlr->chip->text);
if (!error) {
pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
if (mode >= ATA_UDMA0)
pci_write_config(gparent, reg, modes[mode & ATA_MODE_MASK], 1);
else
pci_write_config(gparent, reg, 0x8b, 1);
atadev->mode = mode;
}
}
static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
ulong length)
#endif
{
#define DISP_LINE_LEN 16
ulong i, nbytes, linebytes;
int byte_size;
int rc = 0;
byte_size = pci_byte_size(size);
if (length == 0)
length = 0x40 / byte_size; /* Standard PCI config space */
/* Print the lines.
* once, and all accesses are with the specified bus width.
*/
nbytes = length * byte_size;
do {
printf("%08lx:", addr);
linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
for (i = 0; i < linebytes; i += byte_size) {
unsigned long val;
#ifdef CONFIG_DM_PCI
dm_pci_read_config(dev, addr, &val, size);
#else
val = pci_read_config(bdf, addr, size);
#endif
printf(" %0*lx", pci_field_width(size), val);
addr += byte_size;
}
printf("\n");
nbytes -= linebytes;
if (ctrlc()) {
rc = 1;
break;
}
} while (nbytes > 0);
return (rc);
}
static int
amr_pci_probe(device_t dev)
{
int i;
debug("called");
for (i = 0; amr_device_ids[i].vendor != 0; i++) {
if ((pci_get_vendor(dev) == amr_device_ids[i].vendor) &&
(pci_get_device(dev) == amr_device_ids[i].device)) {
/* do we need to test for a signature? */
if ((amr_device_ids[i].flag & PROBE_SIGNATURE) &&
(pci_read_config(dev, AMR_CFG_SIG, 2) != AMR_SIGNATURE))
continue;
device_set_desc(dev, "AMI MegaRAID");
return(0);
}
}
return(ENXIO);
}
static struct amr_ident *
amr_find_ident(device_t dev)
{
struct amr_ident *id;
int sig;
for (id = amr_device_ids; id->vendor != 0; id++) {
if ((pci_get_vendor(dev) == id->vendor) &&
(pci_get_device(dev) == id->device)) {
/* do we need to test for a signature? */
if (id->flags & AMR_ID_PROBE_SIG) {
sig = pci_read_config(dev, AMR_CFG_SIG, 2);
if ((sig != AMR_SIGNATURE_1) && (sig != AMR_SIGNATURE_2))
continue;
}
return (id);
}
}
return (NULL);
}
static int
mptable_pcib_probe(device_t dev)
{
int bus;
if (!ioapic_enable)
return (ENXIO);
if ((pci_get_class(dev) != PCIC_BRIDGE) ||
(pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
return (ENXIO);
bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
if (bus == 0)
return (ENXIO);
#ifdef notyet
if (mptable_pci_probe_table(bus) != 0)
return (ENXIO);
#endif
device_set_desc(dev, "MPTABLE PCI-PCI bridge");
return (-500);
}
void *os_map_pci_bar(
void *osext,
int index,
HPT_U32 offset,
HPT_U32 length
)
{
PHBA hba = (PHBA)osext;
hba->pcibar[index].rid = 0x10 + index * 4;
if (pci_read_config(hba->pcidev, hba->pcibar[index].rid, 4) & 1)
hba->pcibar[index].type = SYS_RES_IOPORT;
else
hba->pcibar[index].type = SYS_RES_MEMORY;
hba->pcibar[index].res = bus_alloc_resource(hba->pcidev,
hba->pcibar[index].type, &hba->pcibar[index].rid, 0, ~0, length, RF_ACTIVE);
hba->pcibar[index].base = (char *)rman_get_virtual(hba->pcibar[index].res) + offset;
return hba->pcibar[index].base;
}
static int
bt_pci_alloc_resources(device_t dev)
{
int command, type = 0, rid, zero;
struct resource *regs = NULL;
struct resource *irq = NULL;
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
#if 0
/* XXX Memory Mapped I/O seems to cause problems */
if (command & PCIM_CMD_MEMEN) {
type = SYS_RES_MEMORY;
rid = BT_PCI_MEMADDR;
regs = bus_alloc_resource(dev, type, &rid,
0, ~0, 1, RF_ACTIVE);
}
#else
if (!regs && (command & PCIM_CMD_PORTEN)) {
type = SYS_RES_IOPORT;
rid = BT_PCI_IOADDR;
regs = bus_alloc_resource(dev, type, &rid,
0, ~0, 1, RF_ACTIVE);
}
#endif
if (!regs)
return (ENOMEM);
zero = 0;
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero,
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
if (!irq) {
bus_release_resource(dev, type, rid, regs);
return (ENOMEM);
}
bt_init_softc(dev, regs, irq, 0);
return (0);
}
static int
agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
{
u_int8_t val;
u_int8_t key;
switch (aperture) {
case (512 * 1024 * 1024): key = 0; break;
case (256 * 1024 * 1024): key = 8; break;
case (128 * 1024 * 1024): key = 12; break;
case (64 * 1024 * 1024): key = 14; break;
case (32 * 1024 * 1024): key = 15; break;
default:
device_printf(dev, "Invalid aperture size (%dMb)\n",
aperture / 1024 / 1024);
return (EINVAL);
}
val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
return (0);
}
static int
piix_probe(device_t dev)
{
u_int32_t d;
if (devclass_get_device(devclass_find("acpi"), 0) != NULL)
return (ENXIO);
switch (pci_get_devid(dev)) {
case 0x71138086:
device_set_desc(dev, "PIIX Timecounter");
break;
default:
return (ENXIO);
}
d = pci_read_config(dev, PCIR_COMMAND, 2);
if (!(d & PCIM_CMD_PORTEN)) {
device_printf(dev, "PIIX I/O space not mapped\n");
return (ENXIO);
}
return (0);
}
static bhnd_clksrc
bhndb_pci_pwrctl_get_clksrc(device_t dev, device_t child,
bhnd_clock clock)
{
struct bhndb_pci_softc *sc;
uint32_t gpio_out;
sc = device_get_softc(dev);
/* Only supported on PCI devices */
if (bhndb_is_pcie_attached(sc->dev))
return (BHND_CLKSRC_UNKNOWN);
/* Only ILP is supported */
if (clock != BHND_CLOCK_ILP)
return (BHND_CLKSRC_UNKNOWN);
gpio_out = pci_read_config(sc->parent, BHNDB_PCI_GPIO_OUT, 4);
if (gpio_out & BHNDB_PCI_GPIO_SCS)
return (BHND_CLKSRC_PCI);
else
return (BHND_CLKSRC_XTAL);
}
static int
ata_acard_86X_setmode(device_t dev, int target, int mode)
{
device_t parent = device_get_parent(dev);
struct ata_pci_controller *ctlr = device_get_softc(parent);
struct ata_channel *ch = device_get_softc(dev);
int devno = (ch->unit << 1) + target;
mode = min(mode, ctlr->chip->max_dma);
/* XXX SOS missing WDMA0+1 + PIO modes */
if (mode >= ATA_WDMA2) {
u_int16_t reg44 = pci_read_config(parent, 0x44, 2);
reg44 &= ~(0x000f << (devno << 2));
if (mode >= ATA_UDMA0)
reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
pci_write_config(parent, 0x44, reg44, 2);
pci_write_config(parent, 0x4a, 0xa6, 1);
pci_write_config(parent, 0x40 + devno, 0x31, 1);
}
/* we could set PIO mode timings, but we assume the BIOS did that */
return (mode);
}
static int
amdpm_attach(device_t dev)
{
struct amdpm_softc *amdpm_sc = device_get_softc(dev);
u_char val_b;
/* Enable I/O block access */
val_b = pci_read_config(dev, AMDPCI_GEN_CONFIG_PM, 1);
pci_write_config(dev, AMDPCI_GEN_CONFIG_PM, val_b | AMDPCI_PMIOEN, 1);
/* Allocate I/O space */
if (pci_get_vendor(dev) == AMDPM_VENDORID_AMD)
amdpm_sc->rid = AMDPCI_PMBASE;
else
amdpm_sc->rid = NFPCI_PMBASE;
amdpm_sc->res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
&amdpm_sc->rid, RF_ACTIVE);
if (amdpm_sc->res == NULL) {
device_printf(dev, "could not map i/o space\n");
return (ENXIO);
}
mtx_init(&amdpm_sc->lock, device_get_nameunit(dev), "amdpm", MTX_DEF);
/* Allocate a new smbus device */
amdpm_sc->smbus = device_add_child(dev, "smbus", -1);
if (!amdpm_sc->smbus) {
amdpm_detach(dev);
return (EINVAL);
}
bus_generic_attach(dev);
return (0);
}
