void pci_init(void)
{
struct pci_controller *hose = &pci9054_hose;
/*
* Register the hose
*/
hose->first_busno = 0;
hose->last_busno = 0xff;
/* System memory space */
pci_set_region(hose->regions + 0,
0x00000000, 0x00000000, 0x01000000,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI Memory space */
pci_set_region(hose->regions + 1,
0x00000000, 0xc0000000, 0x10000000,
PCI_REGION_MEM);
pci_set_ops(hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
pci9054_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
pci9054_write_config_dword);
hose->region_count = 2;
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
int pci_sh4_init(struct pci_controller *hose)
{
hose->first_busno = 0;
hose->region_count = 0;
hose->last_busno = 0xff;
/* PCI memory space */
pci_set_region(hose->regions + 0,
CONFIG_PCI_MEM_BUS,
CONFIG_PCI_MEM_PHYS,
CONFIG_PCI_MEM_SIZE,
PCI_REGION_MEM);
hose->region_count++;
/* PCI IO space */
pci_set_region(hose->regions + 1,
CONFIG_PCI_IO_BUS,
CONFIG_PCI_IO_PHYS,
CONFIG_PCI_IO_SIZE,
PCI_REGION_IO);
hose->region_count++;
#if defined(CONFIG_PCI_SYS_BUS)
/* PCI System Memory space */
pci_set_region(hose->regions + 2,
CONFIG_PCI_SYS_BUS,
CONFIG_PCI_SYS_PHYS,
CONFIG_PCI_SYS_SIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count++;
#endif
udelay(1000);
pci_set_ops(hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
pci_sh4_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
pci_sh4_write_config_dword);
pci_register_hose(hose);
udelay(1000);
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
hose->last_busno = pci_hose_scan(hose);
return 0;
}
void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
{
pci_set_ops(hose,
indirect_read_config_byte,
indirect_read_config_word,
indirect_read_config_dword,
indirect_write_config_byte,
indirect_write_config_word,
indirect_write_config_dword);
hose->cfg_addr = (unsigned int *) cfg_addr;
hose->cfg_data = (unsigned char *) cfg_data;
}
void pci_setup_type1(struct pci_controller *hose)
{
pci_set_ops(hose,
type1_read_config_byte,
type1_read_config_word,
type1_read_config_dword,
type1_write_config_byte,
type1_write_config_word,
type1_write_config_dword);
hose->cfg_addr = (unsigned int *)PCI_REG_ADDR;
hose->cfg_data = (unsigned char *)PCI_REG_DATA;
}
void pci_mcf547x_8x_init(struct pci_controller *hose)
{
volatile pci_t *pci = (volatile pci_t *) MMAP_PCI;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Port configuration */
gpio->par_pcibg =
GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
GPIO_PAR_PCIBG_PCIBG4(3);
gpio->par_pcibr =
GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
GPIO_PAR_PCIBR_PCIBR4(3);
/* Assert reset bit */
pci->gscr |= PCI_GSCR_PR;
pci->tcr1 = PCI_TCR1_P;
/* Initiator windows */
pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
pci->iwcr =
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
pci->icr = 0;
/* Enable bus master and mem access */
pci->scr = PCI_SCR_B | PCI_SCR_M;
/* Cache line size and master latency */
pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
pci->cr2 = 0;
#ifdef CFG_PCI_BAR0
pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
pci->tbatr0a = CFG_PCI_TBATR0 | PCI_TBATR_EN;
#endif
#ifdef CFG_PCI_BAR1
pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
pci->tbatr1a = CFG_PCI_TBATR1 | PCI_TBATR_EN;
#endif
/* Deassert reset bit */
pci->gscr &= ~PCI_GSCR_PR;
udelay(1000);
/* Enable PCI bus master support */
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
CFG_PCI_IO_SIZE, PCI_REGION_IO);
pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
pci_write_cfg_dword);
/* Hose scan */
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
PCI_INIT_RET_TYPE
pci_init_board (void)
{
#ifdef CONFIG_ATH_EMULATION
prmsg("--- Skipping %s for emulation\n", __func__);
#else
uint32_t cmd;
if (is_drqfn() && !is_qca953x()) {
/*
* Dont enable PCIe in DRQFN package as it has some issues
* related to PCIe
*/
PCI_INIT_RETURN;
}
#if defined(CONFIG_MACH_QCA953x)
if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) {
ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
ath_reg_wr(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_RESET_1);
ath_reg_wr(PCIE_PHY_REG_3_ADDRESS, PCIE_PHY_REG_3_RESET_1);
ath_reg_rmw_set(PCIE_PWR_MGMT_ADDRESS, PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(1));
ath_reg_rmw_set(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_PCIE_RC_SET(1));
PCI_INIT_RETURN;
} else {
/* Honeybee -The PCIe reference clock frequency is being changed
to vary from 99.968MHz to 99.999MHz using SS modulation */
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84)|
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
}
#else
#if defined(CONFIG_MACH_QCA956x)
ath_reg_rmw_set(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_S_SET(PCIE_PHY_REG_1_S_RESET));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84) |
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
#else
// common for rc1 and rc2
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14));
#endif
#endif
ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
udelay(10000);
ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
udelay(1000);
ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1));
udelay(1000);
#if !defined(CONFIG_MACH_QCA956x)
#ifdef PCIE2_APP_ADDRESS
if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) {
pci_rc2_init_board();
return;
}
#endif
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
#ifdef PCIE2_APP_ADDRESS
ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
udelay(10000);
#endif
ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset
udelay(100000);
#ifdef PCIE2_APP_ADDRESS
ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
udelay(10000);
#endif
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) |
PCIE_APP_CFG_BE_SET(0xf) |
PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
PCIE_APP_LTSSM_ENABLE_SET(1));
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
ath_local_write_config(PCI_COMMAND, 4, cmd);
ath_local_write_config(0x20, 4, 0x1ff01000);
ath_local_write_config(0x24, 4, 0x1ff01000);
ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); // Pull endpoint out of reset
udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) {
prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n");
}
#endif
#ifdef PCIE2_APP_ADDRESS
pci_rc2_init_board();
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ath_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ath_pci_write_config);
#endif
plat_dev_init();
#endif /* CONFIG_ATH_EMULATION */
PCI_INIT_RETURN;
}
void pci_mcf5445x_init(struct pci_controller *hose)
{
pci_t *pci = (pci_t *)MMAP_PCI;
pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u32 barEn = 0;
out_be32(&pciarb->acr, 0x001f001f);
/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
PCIREQ2, PCIGNT2 */
out_be16(&gpio->par_pci,
GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
/* Assert reset bit */
setbits_be32(&pci->gscr, PCI_GSCR_PR);
setbits_be32(&pci->tcr1, PCI_TCR1_P);
/* Initiator windows */
out_be32(&pci->iw0btar,
CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
out_be32(&pci->iw1btar,
CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
out_be32(&pci->iw2btar,
CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
out_be32(&pci->iwcr,
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
out_be32(&pci->icr, 0);
/* Enable bus master and mem access */
out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
/* Cache line size and master latency */
out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
out_be32(&pci->cr2, 0);
#ifdef CONFIG_SYS_PCI_BAR0
out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B0E;
#endif
#ifdef CONFIG_SYS_PCI_BAR1
out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B1E;
#endif
#ifdef CONFIG_SYS_PCI_BAR2
out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B2E;
#endif
#ifdef CONFIG_SYS_PCI_BAR3
out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B3E;
#endif
#ifdef CONFIG_SYS_PCI_BAR4
out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B4E;
#endif
#ifdef CONFIG_SYS_PCI_BAR5
out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B5E;
#endif
out_be32(&pci->tcr2, barEn);
/* Deassert reset bit */
clrbits_be32(&pci->gscr, PCI_GSCR_PR);
udelay(1000);
/* Enable PCI bus master support */
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
pci_write_cfg_dword);
/* Hose scan */
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
void pci_init_board(void)
{
int mem_target, mem_attr, i;
int bus = 0;
u32 reg;
u32 soc_ctrl = readl(MVEBU_SYSTEM_REG_BASE + 0x4);
/* Check SoC Control Power State */
debug("%s: SoC Control %08x, 0en %01lx, 1en %01lx, 2en %01lx\n",
__func__, soc_ctrl, SELECT(soc_ctrl, 0), SELECT(soc_ctrl, 1),
SELECT(soc_ctrl, 2));
for (i = 0; i < MAX_PEX; i++) {
struct mvebu_pcie *pcie = &pcie_bus[i];
struct pci_controller *hose = &pcie->hose;
/* Get port number, lane number and memory target / attr */
mvebu_get_port_lane(pcie, i, &mem_target, &mem_attr);
/* Don't read at all from pci registers if port power is down */
if (pcie->lane == 0 && SELECT(soc_ctrl, pcie->port) == 0) {
i += 3;
debug("%s: skipping port %d\n", __func__, pcie->port);
continue;
}
pcie->base = (void __iomem *)PCIE_BASE(i);
/* Check link and skip ports that have no link */
if (!mvebu_pcie_link_up(pcie)) {
debug("%s: PCIe %d.%d - down\n", __func__,
pcie->port, pcie->lane);
continue;
}
debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
pcie->port, pcie->lane, (u32)pcie->base);
/* Read Id info and local bus/dev */
debug("direct conf read %08x, local bus %d, local dev %d\n",
readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
mvebu_pcie_get_local_dev_nr(pcie));
mvebu_pcie_set_local_bus_nr(pcie, bus);
mvebu_pcie_set_local_dev_nr(pcie, 0);
pcie->dev = PCI_BDF(bus, 0, 0);
pcie->mem.start = (u32)mvebu_pcie_membase;
pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
mvebu_pcie_membase += PCIE_MEM_SIZE;
if (mvebu_mbus_add_window_by_id(mem_target, mem_attr,
(phys_addr_t)pcie->mem.start,
PCIE_MEM_SIZE)) {
printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
(u32)pcie->mem.start, PCIE_MEM_SIZE);
}
/* Setup windows and configure host bridge */
mvebu_pcie_setup_wins(pcie);
/* Master + slave enable. */
reg = readl(pcie->base + PCIE_CMD_OFF);
reg |= PCI_COMMAND_MEMORY;
reg |= PCI_COMMAND_MASTER;
reg |= BIT(10); /* disable interrupts */
writel(reg, pcie->base + PCIE_CMD_OFF);
/* Setup U-Boot PCI Controller */
hose->first_busno = 0;
hose->current_busno = bus;
/* PCI memory space */
pci_set_region(hose->regions + 0, pcie->mem.start,
pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
0, 0,
gd->ram_size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 2;
pci_set_ops(hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
mvebu_pcie_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
mvebu_pcie_write_config_dword);
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
/* Set BAR0 to internal registers */
writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
bus = hose->last_busno + 1;
}
}
int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
{
volatile void *mbase = NULL;
int attempts = 0;
pci_set_ops(hose,
pcie_read_config_byte,
pcie_read_config_word,
pcie_read_config_dword,
pcie_write_config_byte,
pcie_write_config_word,
pcie_write_config_dword);
switch (port) {
case 0:
mbase = (u32 *)CFG_PCIE0_XCFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
break;
case 1:
mbase = (u32 *)CFG_PCIE1_XCFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
break;
case 2:
mbase = (u32 *)CFG_PCIE2_XCFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
break;
}
/*
* Set up outbound translation to hose->mem_space from PLB
* addresses at an offset of 0xd_0000_0000. We set the low
* bits of the mask to 11 to turn off splitting into 8
* subregions and to enable the outbound translation.
*/
out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
out_le32(mbase + PECFG_POM0LAL, 0x00001000);
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
case 1:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE));
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
case 2:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE));
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
}
/* Set up 16GB inbound memory window at 0 */
out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
out_le32(mbase + PECFG_BAR0LMPA, 0);
out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
out_le32(mbase + PECFG_PIMEN, 0x1);
/* Enable I/O, Mem, and Busmaster cycles */
out_le16((u16 *)(mbase + PCI_COMMAND),
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
attempts = 10;
switch (port) {
case 0:
while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) {
if (!(attempts--)) {
printf("PCIE0: BMEN is not active\n");
return -1;
}
mdelay(1000);
}
break;
case 1:
while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) {
if (!(attempts--)) {
printf("PCIE1: BMEN is not active\n");
return -1;
}
mdelay(1000);
}
break;
case 2:
while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) {
if (!(attempts--)) {
printf("PCIE2: BMEN is not active\n");
return -1;
}
mdelay(1000);
}
break;
}
printf("PCIE:%d successfully set as endpoint\n",port);
return 0;
}
void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
{
volatile void *mbase = NULL;
volatile void *rmbase = NULL;
pci_set_ops(hose,
pcie_read_config_byte,
pcie_read_config_word,
pcie_read_config_dword,
pcie_write_config_byte,
pcie_write_config_word,
pcie_write_config_dword);
switch (port) {
case 0:
mbase = (u32 *)CFG_PCIE0_XCFGBASE;
rmbase = (u32 *)CFG_PCIE0_CFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
break;
case 1:
mbase = (u32 *)CFG_PCIE1_XCFGBASE;
rmbase = (u32 *)CFG_PCIE1_CFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
break;
case 2:
mbase = (u32 *)CFG_PCIE2_XCFGBASE;
rmbase = (u32 *)CFG_PCIE2_CFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
break;
}
/*
* Set bus numbers on our root port
*/
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
/*
* Set up outbound translation to hose->mem_space from PLB
* addresses at an offset of 0xd_0000_0000. We set the low
* bits of the mask to 11 to turn off splitting into 8
* subregions and to enable the outbound translation.
*/
out_le32(mbase + PECFG_POM0LAH, 0x00000000);
out_le32(mbase + PECFG_POM0LAL, 0x00000000);
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
case 1:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE));
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
case 2:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE));
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
}
/* Set up 16GB inbound memory window at 0 */
out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
out_le32(mbase + PECFG_BAR0LMPA, 0);
out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
out_le32(mbase + PECFG_PIM0LAL, 0);
out_le32(mbase + PECFG_PIM0LAH, 0);
out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
out_le32(mbase + PECFG_PIMEN, 0x1);
/* Enable I/O, Mem, and Busmaster cycles */
out_le16((u16 *)(mbase + PCI_COMMAND),
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
printf("PCIE:%d successfully set as rootpoint\n",port);
}
void pci_mcf5445x_init(struct pci_controller *hose)
{
volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u32 barEn = 0;
pciarb->acr = 0x001F001F;
/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
PCIREQ2, PCIGNT2 */
gpio->par_pci =
GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
/* Assert reset bit */
pci->gscr |= PCI_GSCR_PR;
pci->tcr1 |= PCI_TCR1_P;
/* Initiator windows */
pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
pci->iwcr =
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
pci->icr = 0;
/* Enable bus master and mem access */
pci->scr = PCI_SCR_B | PCI_SCR_M;
/* Cache line size and master latency */
pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
pci->cr2 = 0;
#ifdef CFG_PCI_BAR0
pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B0E;
#endif
#ifdef CFG_PCI_BAR1
pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B1E;
#endif
#ifdef CFG_PCI_BAR2
pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2);
pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B2E;
#endif
#ifdef CFG_PCI_BAR3
pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3);
pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B3E;
#endif
#ifdef CFG_PCI_BAR4
pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4);
pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B4E;
#endif
#ifdef CFG_PCI_BAR5
pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5);
pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B5E;
#endif
pci->tcr2 = barEn;
/* Deassert reset bit */
pci->gscr &= ~PCI_GSCR_PR;
udelay(1000);
/* Enable PCI bus master support */
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
CFG_PCI_IO_SIZE, PCI_REGION_IO);
pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
pci_write_cfg_dword);
/* Hose scan */
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
void pci_init_board (void)
#endif /* #ifdef COMPRESSED_UBOOT */
{
uint32_t cmd;
ar7240_reg_rmw_clear(AR7240_RESET,AR7240_RESET_PCIE_PHY_SERIAL);
udelay(100);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0);
udelay(100000);
/*
* Initialize PCIE PLL and get it out of RESET
*/
ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x02050800);
ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x00050800);
udelay(100);
ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x00040800);
udelay(100000);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4);
udelay(100000);
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
ar7240_local_write_config(PCI_COMMAND, 4, cmd);
ar7240_local_write_config(0x20, 4, 0x1ff01000);
ar7240_local_write_config(0x24, 4, 0x1ff01000);
if ((is_ar7241() || is_ar7242() || is_wasp())) {
ar7240_reg_wr(0x180f0000, 0x1ffc1);
} else {
ar7240_reg_wr(0x180f0000, 0x1);
}
#ifdef COMPRESSED_UBOOT
udelay(100);
#else
udelay(1000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
return;
}
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ar7240_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ar7240_pci_write_config);
#endif
plat_dev_init();
#ifdef COMPRESSED_UBOOT
return 0;
#endif
}
void pci_init_board (void)
#endif /* #ifdef COMPRESSED_UBOOT */
{
#ifdef CONFIG_AP123
return;
#else
uint32_t cmd = 0, reg_val;
//printf("%s: PCIe PLL 0x%x\n", __func__, mips3_cp0_count_read());
//printf("%s: PCIe PLL 0x%x 0xb8000008 = 0x%08x\n", __func__, mips3_cp0_count_read(), ar7240_reg_rd(0xb8040008));
pci_udelay(100000);
//count ++;
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x20) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0));
} else {
#ifndef COMPRESSED_UBOOT
printf("%s: PCIe PLL not set for 40MHz refclk\n", __func__);
#endif
}
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE); // core in reset
pci_udelay(10000);
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE_PHY);// phy in reset
pci_udelay(10000);
ar7240_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog in reset
pci_udelay(10000);
ar7240_reg_wr(0x180f0000, 0x1ffc0); // ltssm is disabled
pci_udelay(100);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0); // End point in reset
pci_udelay(100000);
//ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);
if ((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0) {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(0));
pci_udelay(1000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
ar7240_reg_rd(AR934X_PCIE_PLL_CONFIG) &
(~PCIE_PLL_CONFIG_BYPASS_SET(1)));
pci_udelay(1000);
} else {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(2) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(0xb8116c00, (0x5 << 27) | (160 << 18) | 0);
} else {
ar7240_reg_wr_nf(0xb8116c00, (0x2 << 27) | (0x28 << 18) | 0);
}
do {
ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (1 << 16) | (3 << 13) | (0x1e << 7));
ar7240_reg_wr_nf(0xb8116c08, (6 << 23));
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (3 << 13) | (0x1e << 7));
ar7240_reg_rmw_clear(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
ar7240_reg_rmw_set(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
ar7240_reg_wr(0xb804000c, 1 << 2);
pci_udelay(1000);
while (((cmd = ar7240_reg_rd(PCIe_DPLL4_ADDRESS)) & PCIe_DPLL4_MEAS_DONE_SET(1)) == 0) {
printf("0x%x 0x%x 0x%x\n", KSEG1ADDR(PCIe_DPLL4_ADDRESS), cmd);
pci_udelay(10);
}
{ int i; for (i = 0; i < 100; i++) udelay(10); }
#if 0
msdvc = PCIe_DPLL4_MEAN_DVC_GET(cmd);
cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS));
if (msdvc & 0x400) msdvc = ((~msdvc & 0x7FF) + 1); /* 11 bit signed number , but not intentioanlly multiply by (-1), ASK VIPUL*/
msdvc = cmd - (msdvc *msdvc);
msdvc_sq = msdvc * msdvc;
if (cmd >= 0x40000) {
err_count++;
if (sqsum_min_fail == 0)
sqsum_min_fail = cmd;
if (cmd > sqsum_max_fail)
sqsum_max_fail = cmd;
if (cmd < sqsum_min_fail)
sqsum_min_fail = cmd;
sqsum_avg_fail = (sqsum_avg_fail - (sqsum_avg_fail / err_count)) + (cmd / err_count);
if (num_pll_loops == 0)
err_pll1++;
if (num_pll_loops == 1)
err_pll2++;
if (num_pll_loops == 2)
err_pll3++;
if (num_pll_loops == 3)
err_pll4++;
if (num_pll_loops == 4) {
err_pll5++;
break;
}
} else {
if (sqsum_min == 0)
sqsum_min = cmd;
if (cmd < sqsum_min)
sqsum_min = cmd;
if (cmd > sqsum_max)
sqsum_max = cmd;
//sqsum_avg = (sqsum_avg - (sqsum_avg / count)) + (cmd / count);
sqsum_avg += cmd;
/*msdvc calc*/
if (msdvc_min == 0) msdvc_min = msdvc;
if (msdvc < msdvc_min) msdvc_min =msdvc;
if (msdvc > msdvc_max) msdvc_max =msdvc;
msdvc_avg += msdvc;
msdvc_sq_avg += msdvc_sq;
}
num_pll_loops++;
#endif
} while ((cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS))) >= 0x40000);
ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_BYPASS_SET(1));
pci_udelay(10000);
/*
* PCIe Dithering configuration
*/
if (is_ar934x_12_or_later()) {
ar7240_reg_wr_nf(PCIe_DPLL2_ADDRESS,
PCIe_DPLL2_LOCAL_PLL_SET(0) |
PCIe_DPLL2_KI_SET(0x4)|
PCIe_DPLL2_KD_SET(0x40));
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x40010800);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX, 0xc013fffe);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MIN, 0x0013e666);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00010800);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00000800);
}
//run_command("md 0xb8116c00 4", 0);
}
ar7240_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY); // phy out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE); // core out of reset
pci_udelay(1000);
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
ar7240_local_write_config(PCI_COMMAND, 4, cmd); // pci cmd reg init
ar7240_local_write_config(0x20, 4, 0x1ff01000); // membase setting
ar7240_local_write_config(0x24, 4, 0x1ff01000); // prefetch membase setting
if ((is_ar7241() || is_ar7242() || is_wasp())) {
ar7240_reg_wr(0x180f0000, 0x1ffc1); // ltssm enable
} else {
ar7240_reg_wr(0x180f0000, 0x1);
}
pci_udelay(100000);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4); // EP out of reset
pci_udelay(100000);
#ifdef COMPRESSED_UBOOT
pci_udelay(100);
#else
/*
* Delay increased from 100 to 1000, so as to
* get the correct status from PCI LCL RESET register
*/
pci_udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
return;
}
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ar7240_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ar7240_pci_write_config);
#endif
plat_dev_init();
#endif // CONFIG_AP123
#ifdef COMPRESSED_UBOOT
return 0;
#endif
}
void init_octeon_pcie(void)
{
int first_busno;
int i;
int rc = 0;
int node = cvmx_get_node_num();
struct pci_controller *hose;
int pcie_port;
first_busno = OCTEON_FIRST_PCIE_BUSNO;
memset(&hose_pcie[0], 0, sizeof(hose_pcie[0]) * num_pcie_ports);
debug("Starting PCIE on node %d\n", node);
for (i = 0; i < num_pcie_ports; i++) {
pcie_port = ((node << 4) | i);
rc = cvmx_pcie_rc_initialize(pcie_port);
if (rc != 0)
continue;
mdelay(1000); /* Should delay 1 second according to standard */
hose = &hose_pcie[i];
hose->priv_data = (void *)&oct_pcie_data[i];
oct_pcie_data[i].pcie_port = pcie_port;;
hose->config_table = pci_board_config_table;
hose->first_busno = first_busno;
hose->last_busno = 0xff;
/* PCI I/O space (Sub-DID == 2) */
pci_set_region(hose->regions + 0,
octeon_pcie_region_info[i].io_base,
octeon_pcie_region_info[i].io_base,
octeon_pcie_region_info[i].io_size,
PCI_REGION_IO);
/* PCI memory space (Sub-DID == 3) */
pci_set_region(hose->regions + 1,
octeon_pcie_region_info[i].mem_base,
octeon_pcie_region_info[i].mem_base,
octeon_pcie_region_info[i].mem_size,
PCI_REGION_MEM);
hose->region_count = 2;
pci_set_ops(hose,
octeon_pcie_read_config_byte,
octeon_pcie_read_config_word,
octeon_pcie_read_config_dword,
octeon_pcie_write_config_byte,
octeon_pcie_write_config_word,
octeon_pcie_write_config_dword);
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
debug("PCIe: port=%d, first_bus=%d, last_bus=%d,\n\t"
"mem_base=0x%x, mem_size=0x%x, io_base=0x%x, io_size=0x%x\n",
octeon_get_pcie_port(hose),
hose->first_busno, hose->last_busno,
octeon_pcie_region_info[i].mem_base,
octeon_pcie_region_info[i].mem_size,
octeon_pcie_region_info[i].io_base,
octeon_pcie_region_info[i].io_size);
first_busno = hose->last_busno + 1;
#if CONFIG_OCTEON_PCI_ENABLE_32BIT_MAPPING
if (OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) {
cvmx_pemx_bar_ctl_t bar_ctl;
cvmx_pemx_bar1_indexx_t pemx_bar1_indexx;
uint64_t bar_base;
int j;
/* Setup BAR1 to map bus address 0x0 to the base of
* u-boot's TLB mapping. This allows us to have u-boot
* located anywhere in memory (including above 32 bit
* addressable space) and still have 32 bit PCI devices
* have access to memory that is statically allocated
* or malloced by u-boot, both of which are TLB mapped.
*/
cvmx_write_csr_node(node, CVMX_PEMX_P2N_BAR1_START(i), 0);
/* Disable bar0/bar2, as we are not using them here */
cvmx_write_csr_node(node, CVMX_PEMX_P2N_BAR0_START(i), -1);
cvmx_write_csr_node(node, CVMX_PEMX_P2N_BAR2_START(i), -1);
/* Select 64 MByte mapping size for bar 1 on
* all ports
*/
bar_ctl.u64 = cvmx_read_csr_node(node, CVMX_PEMX_BAR_CTL(i));
bar_ctl.s.bar1_siz = 1; /* 64MB */
bar_ctl.s.bar2_enb = 0;
cvmx_write_csr_node(node, CVMX_PEMX_BAR_CTL(i), bar_ctl.u64);
/* Configure the regions in bar 1 to map to the
* DRAM used by u-boot.
*/
/* Round down to 4MByte boundary to meet BAR mapping
* requirements
*/
bar_base = gd->bd->bi_uboot_ram_addr & ~0x3fffffull;
debug("pcie: port %d, setting BAR base to 0x%llx\n",
i, bar_base);
pemx_bar1_indexx.u64 = 0;
pemx_bar1_indexx.s.addr_v = 1;
pemx_bar1_indexx.s.end_swp = 1;
pemx_bar1_indexx.s.ca = 1;
for (j = 0; j < 16; j++) {
pemx_bar1_indexx.s.addr_idx =
(bar_base + 4 * 1024 * 1024 * j) >> 22;
cvmx_write64_uint64(CVMX_PEMX_BAR1_INDEXX(j, i),
pemx_bar1_indexx.u64);
}
}
#endif /* CONFIG_OCTEON_PCI_ENABLE_32BIT_MAPPING */
}
