/**
* genwqe_setup_vf_jtimer() - Setup VF hardware timeouts for DDCB execution
*/
static bool genwqe_setup_vf_jtimer(struct genwqe_dev *cd)
{
struct pci_dev *pci_dev = cd->pci_dev;
unsigned int vf;
u32 T = genwqe_T_psec(cd);
u64 x;
int totalvfs;
totalvfs = pci_sriov_get_totalvfs(pci_dev);
if (totalvfs <= 0)
return false;
for (vf = 0; vf < totalvfs; vf++) {
if (cd->vf_jobtimeout_msec[vf] == 0)
continue;
x = ilog2(cd->vf_jobtimeout_msec[vf] *
16000000000uL/(T * 15)) - 10;
genwqe_write_vreg(cd, IO_SLC_VF_APPJOB_TIMEOUT,
0xff00 | (x & 0xff), vf + 1);
}
return true;
}
/* Function to check number of LMACs present and set VF::LMAC mapping.
* Mapping will be used while initializing channels.
*/
static void nic_set_lmac_vf_mapping(struct nicpf *nic)
{
unsigned bgx_map = bgx_get_map(nic->node);
int bgx, next_bgx_lmac = 0;
int lmac, lmac_cnt = 0;
u64 lmac_credit;
nic->num_vf_en = 0;
for (bgx = 0; bgx < nic->hw->bgx_cnt; bgx++) {
if (!(bgx_map & (1 << bgx)))
continue;
lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
for (lmac = 0; lmac < lmac_cnt; lmac++)
nic->vf_lmac_map[next_bgx_lmac++] =
NIC_SET_VF_LMAC_MAP(bgx, lmac);
nic->num_vf_en += lmac_cnt;
/* Program LMAC credits */
lmac_credit = (1ull << 1); /* channel credit enable */
lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
/* 48KB BGX Tx buffer size, each unit is of size 16bytes */
lmac_credit |= (((((48 * 1024) / lmac_cnt) -
NIC_HW_MAX_FRS) / 16) << 12);
lmac = bgx * MAX_LMAC_PER_BGX;
for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++)
nic_reg_write(nic,
NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
lmac_credit);
/* On CN81XX there are only 8 VFs but max possible no of
* interfaces are 9.
*/
if (nic->num_vf_en >= pci_sriov_get_totalvfs(nic->pdev)) {
nic->num_vf_en = pci_sriov_get_totalvfs(nic->pdev);
break;
}
}
}
static void nic_get_hw_info(struct nicpf *nic)
{
u16 sdevid;
struct hw_info *hw = nic->hw;
pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid);
switch (sdevid) {
case PCI_SUBSYS_DEVID_88XX_NIC_PF:
hw->bgx_cnt = MAX_BGX_PER_CN88XX;
hw->chans_per_lmac = 16;
hw->chans_per_bgx = 128;
hw->cpi_cnt = 2048;
hw->rssi_cnt = 4096;
hw->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
hw->tl3_cnt = 256;
hw->tl2_cnt = 64;
hw->tl1_cnt = 2;
hw->tl1_per_bgx = true;
break;
case PCI_SUBSYS_DEVID_81XX_NIC_PF:
hw->bgx_cnt = MAX_BGX_PER_CN81XX;
hw->chans_per_lmac = 8;
hw->chans_per_bgx = 32;
hw->chans_per_rgx = 8;
hw->chans_per_lbk = 24;
hw->cpi_cnt = 512;
hw->rssi_cnt = 256;
hw->rss_ind_tbl_size = 32; /* Max RSSI / Max interfaces */
hw->tl3_cnt = 64;
hw->tl2_cnt = 16;
hw->tl1_cnt = 10;
hw->tl1_per_bgx = false;
break;
case PCI_SUBSYS_DEVID_83XX_NIC_PF:
hw->bgx_cnt = MAX_BGX_PER_CN83XX;
hw->chans_per_lmac = 8;
hw->chans_per_bgx = 32;
hw->chans_per_lbk = 64;
hw->cpi_cnt = 2048;
hw->rssi_cnt = 1024;
hw->rss_ind_tbl_size = 64; /* Max RSSI / Max interfaces */
hw->tl3_cnt = 256;
hw->tl2_cnt = 64;
hw->tl1_cnt = 18;
hw->tl1_per_bgx = false;
break;
}
hw->tl4_cnt = MAX_QUEUES_PER_QSET * pci_sriov_get_totalvfs(nic->pdev);
}
int mlx5_sriov_init(struct mlx5_core_dev *dev)
{
struct mlx5_core_sriov *sriov = &dev->priv.sriov;
struct pci_dev *pdev = dev->pdev;
int total_vfs;
if (!mlx5_core_is_pf(dev))
return 0;
total_vfs = pci_sriov_get_totalvfs(pdev);
sriov->num_vfs = pci_num_vf(pdev);
sriov->vfs_ctx = kcalloc(total_vfs, sizeof(*sriov->vfs_ctx), GFP_KERNEL);
if (!sriov->vfs_ctx)
return -ENOMEM;
return 0;
}
/* PF -> VF mailbox communication APIs */
static void nic_enable_mbx_intr(struct nicpf *nic)
{
int vf_cnt = pci_sriov_get_totalvfs(nic->pdev);
#define INTR_MASK(vfs) ((vfs < 64) ? (BIT_ULL(vfs) - 1) : (~0ull))
/* Clear it, to avoid spurious interrupts (if any) */
nic_reg_write(nic, NIC_PF_MAILBOX_INT, INTR_MASK(vf_cnt));
/* Enable mailbox interrupt for all VFs */
nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, INTR_MASK(vf_cnt));
/* One mailbox intr enable reg per 64 VFs */
if (vf_cnt > 64) {
nic_reg_write(nic, NIC_PF_MAILBOX_INT + sizeof(u64),
INTR_MASK(vf_cnt - 64));
nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64),
INTR_MASK(vf_cnt - 64));
}
}
/**
* genwqe_pci_setup() - Allocate PCIe related resources for our card
*/
static int genwqe_pci_setup(struct genwqe_dev *cd)
{
int err;
struct pci_dev *pci_dev = cd->pci_dev;
err = pci_enable_device_mem(pci_dev);
if (err) {
dev_err(&pci_dev->dev,
"err: failed to enable pci memory (err=%d)\n", err);
goto err_out;
}
/* Reserve PCI I/O and memory resources */
err = pci_request_mem_regions(pci_dev, genwqe_driver_name);
if (err) {
dev_err(&pci_dev->dev,
"[%s] err: request bars failed (%d)\n", __func__, err);
err = -EIO;
goto err_disable_device;
}
/* check for 64-bit DMA address supported (DAC) */
if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
err = pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(64));
if (err) {
dev_err(&pci_dev->dev,
"err: DMA64 consistent mask error\n");
err = -EIO;
goto out_release_resources;
}
/* check for 32-bit DMA address supported (SAC) */
} else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) {
err = pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(32));
if (err) {
dev_err(&pci_dev->dev,
"err: DMA32 consistent mask error\n");
err = -EIO;
goto out_release_resources;
}
} else {
dev_err(&pci_dev->dev,
"err: neither DMA32 nor DMA64 supported\n");
err = -EIO;
goto out_release_resources;
}
pci_set_master(pci_dev);
pci_enable_pcie_error_reporting(pci_dev);
/* EEH recovery requires PCIe fundamental reset */
pci_dev->needs_freset = 1;
/* request complete BAR-0 space (length = 0) */
cd->mmio_len = pci_resource_len(pci_dev, 0);
cd->mmio = pci_iomap(pci_dev, 0, 0);
if (cd->mmio == NULL) {
dev_err(&pci_dev->dev,
"[%s] err: mapping BAR0 failed\n", __func__);
err = -ENOMEM;
goto out_release_resources;
}
cd->num_vfs = pci_sriov_get_totalvfs(pci_dev);
if (cd->num_vfs < 0)
cd->num_vfs = 0;
err = genwqe_read_ids(cd);
if (err)
goto out_iounmap;
return 0;
out_iounmap:
pci_iounmap(pci_dev, cd->mmio);
out_release_resources:
pci_release_mem_regions(pci_dev);
err_disable_device:
pci_disable_device(pci_dev);
err_out:
return err;
}
/* On top of the default firmware vswitch setup, create a VEB vswitch and
* expansion vport for use by this function.
*/
int efx_ef10_vswitching_probe_pf(struct efx_nic *efx)
{
#ifdef CONFIG_SFC_SRIOV
struct efx_ef10_nic_data *nic_data = efx->nic_data;
struct net_device *net_dev = efx->net_dev;
int rc;
#if !defined(EFX_USE_KCOMPAT) || defined(EFX_HAVE_SRIOV_GET_TOTALVFS)
if (pci_sriov_get_totalvfs(efx->pci_dev) <= 0 && !enable_vswitch) {
#else
if (efx->max_vfs <= 0 && !enable_vswitch) {
#endif
/* vswitch not needed as we have no VFs */
efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
return 0;
}
rc = efx_ef10_vswitch_alloc(efx, EVB_PORT_ID_ASSIGNED,
MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB);
if (rc)
goto fail1;
rc = efx_ef10_vport_alloc(efx, EVB_PORT_ID_ASSIGNED,
MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL,
EFX_EF10_NO_VLAN, &nic_data->vport_id);
if (rc)
goto fail2;
efx->ef10_resources.vport_id = nic_data->vport_id;
rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id, net_dev->dev_addr);
if (rc)
goto fail3;
ether_addr_copy(nic_data->vport_mac, net_dev->dev_addr);
rc = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
if (rc)
goto fail4;
return 0;
fail4:
efx_ef10_vport_del_mac(efx, nic_data->vport_id, nic_data->vport_mac);
eth_zero_addr(nic_data->vport_mac);
fail3:
efx_ef10_vport_free(efx, nic_data->vport_id);
nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
fail2:
efx_ef10_vswitch_free(efx, EVB_PORT_ID_ASSIGNED);
fail1:
return rc;
#else
return 0;
#endif
}
int efx_ef10_vswitching_probe_vf(struct efx_nic *efx)
{
#ifdef CONFIG_SFC_SRIOV
struct efx_ef10_nic_data *nic_data = efx->nic_data;
return efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
#else
return 0;
#endif
}
int efx_ef10_vswitching_restore_pf(struct efx_nic *efx)
{
#ifdef CONFIG_SFC_SRIOV
struct efx_ef10_nic_data *nic_data = efx->nic_data;
int rc;
if (!nic_data->must_probe_vswitching)
return 0;
rc = efx_ef10_vswitching_probe_pf(efx);
if (rc)
goto fail;
rc = efx_ef10_sriov_restore_vf_vswitching(efx);
if (rc)
goto fail;
nic_data->must_probe_vswitching = false;
fail:
return rc;
#else
return 0;
#endif
}
int efx_ef10_vswitching_restore_vf(struct efx_nic *efx)
{
#ifdef CONFIG_SFC_SRIOV
struct efx_ef10_nic_data *nic_data = efx->nic_data;
int rc;
if (!nic_data->must_probe_vswitching)
return 0;
rc = efx_ef10_vadaptor_free(efx, EVB_PORT_ID_ASSIGNED);
if (rc)
return rc;
nic_data->must_probe_vswitching = false;
#endif
return 0;
}
void efx_ef10_vswitching_remove_pf(struct efx_nic *efx)
{
#ifdef CONFIG_SFC_SRIOV
struct efx_ef10_nic_data *nic_data = efx->nic_data;
efx_ef10_sriov_free_vf_vswitching(efx);
efx_ef10_vadaptor_free(efx, nic_data->vport_id);
if (nic_data->vport_id == EVB_PORT_ID_ASSIGNED)
return; /* No vswitch was ever created */
if (!is_zero_ether_addr(nic_data->vport_mac)) {
efx_ef10_vport_del_mac(efx, nic_data->vport_id,
efx->net_dev->dev_addr);
eth_zero_addr(nic_data->vport_mac);
}
efx_ef10_vport_free(efx, nic_data->vport_id);
nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
#if !defined(EFX_USE_KCOMPAT) || defined(EFX_HAVE_PCI_DEV_FLAGS_ASSIGNED)
/* Only free the vswitch if no VFs are assigned */
if (!pci_vfs_assigned(efx->pci_dev))
#endif
efx_ef10_vswitch_free(efx, nic_data->vport_id);
#endif
}
void efx_ef10_vswitching_remove_vf(struct efx_nic *efx)
{
#ifdef CONFIG_SFC_SRIOV
efx_ef10_vadaptor_free(efx, EVB_PORT_ID_ASSIGNED);
#endif
}
