static void __init
luan_setup_hoses(void)
{
struct pci_controller *hose0, *hose1, *hose2;
/* Configure windows on the PCI-X host bridge */
luan_setup_pcix();
/* Allocate hoses for PCIX0, PCIX1 and PCIX2 */
hose0 = pcibios_alloc_controller();
hose1 = pcibios_alloc_controller();
hose2 = pcibios_alloc_controller();
if (!hose0 || !hose1 || !hose2)
return;
/* Setup PCIX0 */
hose0->first_busno = 0;
hose0->last_busno = 0xff;
luan_setup_hose(hose0,
LUAN_PCIX0_LOWER_MEM,
LUAN_PCIX0_UPPER_MEM,
PCIX0_CFGA,
PCIX0_CFGD,
PCIX0_IO_BASE);
hose0->last_busno = pciauto_bus_scan(hose0, hose0->first_busno);
/* Setup PCIX1 */
hose1->first_busno = hose0->last_busno + 1;
hose1->last_busno = 0xff;
luan_setup_hose(hose1,
LUAN_PCIX1_LOWER_MEM,
LUAN_PCIX1_UPPER_MEM,
PCIX1_CFGA,
PCIX1_CFGD,
PCIX1_IO_BASE);
hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
/* Setup PCIX2 */
hose2->first_busno = hose1->last_busno + 1;
hose2->last_busno = 0xff;
luan_setup_hose(hose2,
LUAN_PCIX2_LOWER_MEM,
LUAN_PCIX2_UPPER_MEM,
PCIX2_CFGA,
PCIX2_CFGD,
PCIX2_IO_BASE);
hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = luan_map_irq;
}
static void __init
yosemite_setup_hose(void)
{
unsigned int bar_response, bar;
struct pci_controller *hose;
yosemite_setup_pci();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = YOSEMITE_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
YOSEMITE_PCI_LOWER_IO,
YOSEMITE_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
YOSEMITE_PCI_LOWER_MEM,
YOSEMITE_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
ppc_md.pci_exclude_device = yosemite_exclude_device;
hose->io_space.start = YOSEMITE_PCI_LOWER_IO;
hose->io_space.end = YOSEMITE_PCI_UPPER_IO;
hose->mem_space.start = YOSEMITE_PCI_LOWER_MEM;
hose->mem_space.end = YOSEMITE_PCI_UPPER_MEM;
isa_io_base =
(unsigned long)ioremap64(YOSEMITE_PCI_IO_BASE, YOSEMITE_PCI_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
setup_indirect_pci(hose,
YOSEMITE_PCI_CFGA_PLB32,
YOSEMITE_PCI_CFGD_PLB32);
hose->set_cfg_type = 1;
/* Zero config bars */
for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
early_write_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno), bar,
0x00000000);
early_read_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno), bar,
&bar_response);
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = yosemite_map_irq;
}
static void __init
sandpoint_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
if (mpc10x_bridge_init(hose,
MPC10X_MEM_MAP_B,
MPC10X_MEM_MAP_B, MPC10X_MAPB_EUMB_BASE) == 0) {
/* Do early winbond init, then scan PCI bus */
sandpoint_setup_winbond_83553(hose);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = sandpoint_map_irq;
} else {
if (ppc_md.progress)
ppc_md.progress("Bridge init failed", 0x100);
printk("Host bridge init failed\n");
}
return;
}
void __init
pplus_setup_hose(void)
{
struct pci_controller* hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = PREP_ISA_MEM_BASE;
hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
pplus_init_resource(&hose->io_resource, 0x00000000, 0x0fffffff,
IORESOURCE_IO);
pplus_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfdffffff,
IORESOURCE_MEM);
hose->io_space.start = 0x00000000;
hose->io_space.end = 0x0fffffff;
hose->mem_space.start = 0x00000000;
hose->mem_space.end = 0x3cfbffff; /* MPIC at 0x3cfc0000-0x3dffffff */
setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc);
pplus_set_VIA_IDE_legacy();
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = pplus_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
pplus_set_board_type();
}
static void __init
yucca_setup_hoses(void)
{
struct pci_controller *hose;
char name[20];
int i;
if (0 && ppc440spe_init_pcie()) {
printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
return;
}
for (i = 0; i <= 2; ++i) {
if (!yucca_pcie_card_present(i))
continue;
printk(KERN_INFO "PCIE%d: card present\n", i);
yucca_setup_pcie_fpga_rootpoint(i);
if (ppc440spe_init_pcie_rootport(i)) {
printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
continue;
}
hose = pcibios_alloc_controller();
if (!hose)
return;
sprintf(name, "PCIE%d host bridge", i);
pci_init_resource(&hose->io_resource,
YUCCA_PCIX_LOWER_IO,
YUCCA_PCIX_UPPER_IO,
IORESOURCE_IO,
name);
hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
i * YUCCA_PCIE_MEM_SIZE;
hose->mem_space.end = hose->mem_space.start +
YUCCA_PCIE_MEM_SIZE - 1;
pci_init_resource(&hose->mem_resources[0],
hose->mem_space.start,
hose->mem_space.end,
IORESOURCE_MEM,
name);
hose->first_busno = 0;
hose->last_busno = 15;
hose_type[hose->index] = HOSE_PCIE0 + i;
ppc440spe_setup_pcie(hose, i);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
}
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = yucca_map_irq;
}
static void __init
p3p440_setup_hose(void)
{
struct pci_controller *hose;
if (!is_monarch()) {
/*
* REMARK: This Non-Monarch mode need perhaps some changes.
* It's not tested at all, because of lack of hardware. --sr
*/
printk("P3P440-PCI: Non-Monarch detected, skipping PCI init!\n");
return;
}
/* Configure windows on the PCI-X host bridge */
p3p440_setup_pcix();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = P3P440_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
P3P440_PCI_LOWER_IO,
P3P440_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
P3P440_PCI_LOWER_MEM,
P3P440_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = P3P440_PCI_LOWER_IO;
hose->io_space.end = P3P440_PCI_UPPER_IO;
hose->mem_space.start = P3P440_PCI_LOWER_MEM;
hose->mem_space.end = P3P440_PCI_UPPER_MEM;
hose->io_base_virt = ioremap64(P3P440_PCI_IO_BASE, P3P440_PCI_IO_SIZE);
isa_io_base = (unsigned long)hose->io_base_virt;
setup_indirect_pci(hose, PCIX0_CFGA, PCIX0_CFGD);
hose->set_cfg_type = 1;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = p3p440_map_irq;
}
static void __init taiga_setup_bridge(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (hose){
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = TAIGA_PCI_MEM_OFFSET;
/* Setup resources to match map
* PCI memory and IO space are set in PFAB_BARs by boot code
* 64KB take one 16MB LUT entry, PFAB_IO
*/
pci_init_resource(&hose->io_resource, TAIGA_PCI_IO_START,
TAIGA_PCI_IO_END, IORESOURCE_IO,
"PCI host bridge");
/* OCN to PCI/X transaction is unchanged,
* bar1 first 8 LUTs, 128MB
*/
pci_init_resource(&hose->mem_resources[0],
TAIGA_PCI_MEM_START,
TAIGA_PCI_MEM_END,
IORESOURCE_MEM, "PCI host bridge");
(hose)->io_space.start = TAIGA_PCI_IO_START;
(hose)->io_space.end = TAIGA_PCI_IO_END;
(hose)->mem_space.start = TAIGA_PCI_MEM_START;
(hose)->mem_space.end = TAIGA_PCI_MEM_END;
(hose)->io_base_virt = (void *)TAIGA_ISA_IO_BASE;
(hose)->ops = &direct_pci_ops;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = taiga_map_irq;
if (ppc_md.progress)
ppc_md.progress("tsi108: resources set", 0x100);
tsi108_bridge_init(hose, TSI108_CSR_ADDR_PHYS);
} else {
printk("PCI Host bridge init failed\n");
}
}
static void __init
ebony_setup_hose(void)
{
struct pci_controller *hose;
/* Configure windows on the PCI-X host bridge */
ebony_setup_pcix();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
EBONY_PCI_LOWER_IO,
EBONY_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
EBONY_PCI_LOWER_MEM,
EBONY_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = EBONY_PCI_LOWER_IO;
hose->io_space.end = EBONY_PCI_UPPER_IO;
hose->mem_space.start = EBONY_PCI_LOWER_MEM;
hose->mem_space.end = EBONY_PCI_UPPER_MEM;
isa_io_base =
(unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
setup_indirect_pci(hose,
EBONY_PCI_CFGA_PLB32,
EBONY_PCI_CFGD_PLB32);
hose->set_cfg_type = 1;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = ebony_map_irq;
}
void __init platform_pcibios_init(void)
{
struct pci_controller *pci_ctrl;
/* Setup pci_controller */
pci_ctrl = pcibios_alloc_controller();
if (!pci_ctrl) {
printk("PCI: cannot allocate space for the pci controller\n");
return;
}
/* Move V3USC to 0xFD000000 */
V3USC_LB_REG_BASE_W = PCI_V320_BASE >> 16;
*(unsigned int*)(XT2000_V3CFG_PADDR) = 0;
/* Initialize the V3 */
v320usc_pci_init();
/* Setup the controller */
pci_ctrl->first_busno = 0;
pci_ctrl->last_busno = 0xff;
pci_ctrl->ops = &v320usc_pci_ops;
pci_ctrl->map_irq = map_irq;
pci_ctrl->io_space.start = PCI_IO_SPACE_PCI_BASE;
pci_ctrl->io_space.end = PCI_IO_SPACE_PCI_BASE + PCI_IO_SPACE_SIZE;
pci_ctrl->io_space.base = PCI_IO_SPACE_CPU_BASE;
pci_ctrl->mem_space.start = PCI_MEM_SPACE_PCI_BASE;
pci_ctrl->mem_space.end = PCI_MEM_SPACE_PCI_BASE + PCI_MEM_SPACE_SIZE;
pci_ctrl->mem_space.base = 0;
pcibios_init_resource(&pci_ctrl->io_resource,
PCI_IO_SPACE_PCI_BASE,
PCI_IO_SPACE_PCI_BASE + PCI_IO_SPACE_SIZE,
IORESOURCE_IO, "PCI host bridge");
pcibios_init_resource(&pci_ctrl->mem_resources[0],
PCI_MEM_SPACE_CPU_BASE,
PCI_MEM_SPACE_CPU_BASE + PCI_MEM_SPACE_SIZE,
IORESOURCE_MEM, "PCI host bridge");
/* Enumerate the PCI bus */
pci_ctrl->last_busno = pciauto_bus_scan(pci_ctrl,pci_ctrl->first_busno);
}
void __init prpmc750_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->io_base_virt = (void *)PRPMC750_ISA_IO_BASE;
hose->pci_mem_offset = PRPMC750_PCI_PHY_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
PRPMC750_PCI_IO_START,
PRPMC750_PCI_IO_END,
IORESOURCE_IO, "PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
PRPMC750_PROC_PCI_MEM_START,
PRPMC750_PROC_PCI_MEM_END,
IORESOURCE_MEM, "PCI host bridge");
hose->io_space.start = PRPMC750_PCI_IO_START;
hose->io_space.end = PRPMC750_PCI_IO_END;
hose->mem_space.start = PRPMC750_PCI_MEM_START;
hose->mem_space.end = PRPMC750_PCI_MEM_END - HAWK_MPIC_SIZE;
if (hawk_init(hose, PRPMC750_HAWK_PPC_REG_BASE,
PRPMC750_PROC_PCI_MEM_START,
PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
PRPMC750_PROC_PCI_IO_START, PRPMC750_PROC_PCI_IO_END,
PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
!= 0) {
printk(KERN_CRIT "Could not initialize host bridge\n");
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = prpmc750_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = prpmc_map_irq;
}
void __init
mvme5100_setup_bridge(void)
{
struct pci_controller* hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = MVME5100_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
MVME5100_PCI_LOWER_IO,
MVME5100_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
MVME5100_PCI_LOWER_MEM,
MVME5100_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = MVME5100_PCI_LOWER_IO;
hose->io_space.end = MVME5100_PCI_UPPER_IO;
hose->mem_space.start = MVME5100_PCI_LOWER_MEM;
hose->mem_space.end = MVME5100_PCI_UPPER_MEM;
hose->io_base_virt = (void *)MVME5100_ISA_IO_BASE;
/* Use indirect method of Hawk */
setup_indirect_pci(hose,
MVME5100_PCI_CONFIG_ADDR,
MVME5100_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup_resources = mvme5100_pcibios_fixup_resources;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mvme5100_map_irq;
}
void __init
spruce_setup_hose(void)
{
struct pci_controller *hose;
/* Setup hose */
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_init_resource(&hose->io_resource,
SPRUCE_PCI_LOWER_IO,
SPRUCE_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
SPRUCE_PCI_LOWER_MEM,
SPRUCE_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = SPRUCE_PCI_LOWER_IO;
hose->io_space.end = SPRUCE_PCI_UPPER_IO;
hose->mem_space.start = SPRUCE_PCI_LOWER_MEM;
hose->mem_space.end = SPRUCE_PCI_UPPER_MEM;
hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE;
setup_indirect_pci(hose,
SPRUCE_PCI_CONFIG_ADDR,
SPRUCE_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = spruce_map_irq;
}
void __init
pal4_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = 0;
/* Could snatch these from the CPC700.... */
pci_init_resource(&hose->io_resource,
0x0,
0x03ffffff,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
0x90000000,
0x9fffffff,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = 0x00800000;
hose->io_space.end = 0x03ffffff;
hose->mem_space.start = 0x90000000;
hose->mem_space.end = 0x9fffffff;
hose->io_base_virt = (void *) 0xf8000000;
setup_indirect_pci(hose, CPC700_PCI_CONFIG_ADDR,
CPC700_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = pal4_map_irq;
}
static void __init
lopec_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
if (mpc10x_bridge_init(hose, MPC10X_MEM_MAP_B, MPC10X_MEM_MAP_B,
MPC10X_MAPB_EUMB_BASE) == 0) {
hose->mem_resources[0].end = 0xffffffff;
lopec_setup_winbond_83553(hose);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = lopec_map_irq;
}
}
int __init
pcore_find_bridges(void)
{
struct pci_controller* hose;
int host_bridge, board_type;
hose = pcibios_alloc_controller();
if (!hose)
return 0;
mpc10x_bridge_init(hose,
MPC10X_MEM_MAP_B,
MPC10X_MEM_MAP_B,
MPC10X_MAPB_EUMB_BASE);
/* Determine board type */
early_read_config_dword(hose,
0,
PCI_DEVFN(0,0),
PCI_VENDOR_ID,
&host_bridge);
if (host_bridge == MPC10X_BRIDGE_106)
board_type = PCORE_TYPE_6750;
else /* MPC10X_BRIDGE_107 */
board_type = PCORE_TYPE_680;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = pcore_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
if (board_type == PCORE_TYPE_6750)
ppc_md.pci_map_irq = pcore_6750_map_irq;
else /* PCORE_TYPE_680 */
ppc_md.pci_map_irq = pcore_680_map_irq;
return board_type;
}
/**************************************************************************
* FUNCTION: chestnut_setup_bridge
*
* DESCRIPTION: initalize board-specific settings on the MV64360
*
****/
static void __init
chestnut_setup_bridge(void)
{
struct mv64x60_setup_info si;
int i;
if ( ppc_md.progress )
ppc_md.progress("chestnut_setup_bridge: enter", 0);
memset(&si, 0, sizeof(si));
si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
/* setup only PCI bus 0 (bus 1 not used) */
si.pci_0.enable_bus = 1;
si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
si.pci_0.pci_io.pci_base_hi = 0;
si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
si.pci_0.pci_cmd_bits = 0;
si.pci_0.latency_timer = 0x80;
for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
#if defined(CONFIG_NOT_COHERENT_CACHE)
si.cpu_prot_options[i] = 0;
si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
si.pci_1.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_NONE |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
si.cpu_prot_options[i] = 0;
si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
si.pci_1.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_WB |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
#endif
}
/* Lookup host bridge - on CPU 0 - no SMP support */
if (mv64x60_init(&bh, &si)) {
printk("\n\nPCI Bridge initialization failed!\n");
}
pci_dram_offset = 0;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = chestnut_map_irq;
ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
mv64x60_set_bus(&bh, 0, 0);
bh.hose_a->first_busno = 0;
bh.hose_a->last_busno = 0xff;
bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
}
void __init
mpc83xx_setup_hose(void)
{
u32 val32;
volatile immr_clk_t * clk;
struct pci_controller * hose1;
#ifdef CONFIG_MPC83xx_PCI2
struct pci_controller * hose2;
#endif
bd_t * binfo = (bd_t *)__res;
clk = ioremap(binfo->bi_immr_base + 0xA00,
sizeof(immr_clk_t));
/*
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
*/
val32 = clk->occr;
udelay(2000);
clk->occr = 0xff000000;
udelay(2000);
iounmap(clk);
hose1 = pcibios_alloc_controller();
if(!hose1)
return;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mpc83xx_map_irq;
hose1->bus_offset = 0;
hose1->first_busno = 0;
hose1->last_busno = 0xff;
setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
hose1->set_cfg_type = 1;
mpc83xx_setup_pci1(hose1);
hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
#ifdef CONFIG_MPC83xx_PCI2
isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
#else
isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
MPC83xx_PCI1_IO_SIZE);
#endif /* CONFIG_MPC83xx_PCI2 */
hose1->io_base_virt = (void *)isa_io_base;
/* setup resources */
pci_init_resource(&hose1->io_resource,
MPC83xx_PCI1_LOWER_IO,
MPC83xx_PCI1_UPPER_IO,
IORESOURCE_IO, "PCI host bridge 1");
pci_init_resource(&hose1->mem_resources[0],
MPC83xx_PCI1_LOWER_MEM,
MPC83xx_PCI1_UPPER_MEM,
IORESOURCE_MEM, "PCI host bridge 1");
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
#ifdef CONFIG_MPC83xx_PCI2
hose2 = pcibios_alloc_controller();
if(!hose2)
return;
hose2->bus_offset = hose1->last_busno + 1;
hose2->first_busno = hose1->last_busno + 1;
hose2->last_busno = 0xff;
setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
hose2->set_cfg_type = 1;
mpc83xx_setup_pci2(hose2);
hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
/* setup resources */
pci_init_resource(&hose2->io_resource,
MPC83xx_PCI2_LOWER_IO,
MPC83xx_PCI2_UPPER_IO,
IORESOURCE_IO, "PCI host bridge 2");
pci_init_resource(&hose2->mem_resources[0],
MPC83xx_PCI2_LOWER_MEM,
MPC83xx_PCI2_UPPER_MEM,
IORESOURCE_MEM, "PCI host bridge 2");
hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
#endif /* CONFIG_MPC83xx_PCI2 */
}
void __init
mpc85xx_setup_hose(void)
{
struct pci_controller *hose_a;
#ifdef CONFIG_85xx_PCI2
struct pci_controller *hose_b;
#endif
bd_t *binfo = (bd_t *) __res;
hose_a = pcibios_alloc_controller();
if (!hose_a)
return;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mpc85xx_map_irq;
hose_a->first_busno = 0;
hose_a->bus_offset = 0;
hose_a->last_busno = 0xff;
setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
hose_a->set_cfg_type = 1;
mpc85xx_setup_pci1(hose_a);
hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
#ifdef CONFIG_85xx_PCI2
hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
MPC85XX_PCI1_IO_SIZE +
MPC85XX_PCI2_IO_SIZE);
#else
hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
MPC85XX_PCI1_IO_SIZE);
#endif
isa_io_base = (unsigned long)hose_a->io_base_virt;
/* setup resources */
pci_init_resource(&hose_a->mem_resources[0],
MPC85XX_PCI1_LOWER_MEM,
MPC85XX_PCI1_UPPER_MEM,
IORESOURCE_MEM, "PCI1 host bridge");
pci_init_resource(&hose_a->io_resource,
MPC85XX_PCI1_LOWER_IO,
MPC85XX_PCI1_UPPER_IO,
IORESOURCE_IO, "PCI1 host bridge");
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
/* Pre pciauto_bus_scan VIA init */
mpc85xx_cds_enable_via(hose_a);
#endif
hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
/* Post pciauto_bus_scan VIA fixup */
mpc85xx_cds_fixup_via(hose_a);
#endif
#ifdef CONFIG_85xx_PCI2
hose_b = pcibios_alloc_controller();
if (!hose_b)
return;
hose_b->bus_offset = hose_a->last_busno + 1;
hose_b->first_busno = hose_a->last_busno + 1;
hose_b->last_busno = 0xff;
setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
hose_b->set_cfg_type = 1;
mpc85xx_setup_pci2(hose_b);
hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE;
/* setup resources */
pci_init_resource(&hose_b->mem_resources[0],
MPC85XX_PCI2_LOWER_MEM,
MPC85XX_PCI2_UPPER_MEM,
IORESOURCE_MEM, "PCI2 host bridge");
pci_init_resource(&hose_b->io_resource,
MPC85XX_PCI2_LOWER_IO,
MPC85XX_PCI2_UPPER_IO,
IORESOURCE_IO, "PCI2 host bridge");
hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
/* let board code know what the last bus number was on PCI1 */
mpc85xx_pci1_last_busno = hose_a->last_busno;
#endif
return;
}
static void __init
yucca_setup_hoses(void)
{
struct pci_controller *hose;
char name[20];
enum yucca_hoses hs;
int bus_no = 0;
for (hs = HOSE_PCIX; hs < HOSE_MAX; ++hs) {
if (is_pcie_hose(hs)) {
if (!yucca_pcie_card_present(pcie_hose_num(hs)))
continue;
pr_debug("PCIE%d: card present\n", pcie_hose_num(hs));
yucca_setup_pcie_fpga_root_or_endpoint(pcie_hose_num(hs));
if (ppc440spe_init_pcie_root_or_endport(pcie_hose_num(hs))) {
printk(KERN_ERR "PCIE%d: initialization "
"failed\n", pcie_hose_num(hs));
continue;
}
}
hose = pcibios_alloc_controller();
if (!hose)
return;
sprintf(name, "PCI%s%d host bridge",
is_pcix_hose(hs) ? "X" : "E",
is_pcie_hose(hs) ? pcie_hose_num(hs) : 0
);
pci_init_resource(&hose->io_resource,
YUCCA_PCIX_LOWER_IO,
YUCCA_PCIX_UPPER_IO,
IORESOURCE_IO,
name);
if (is_pcix_hose(hs)) {
hose->mem_space.start = YUCCA_PCIX_LOWER_MEM;
hose->mem_space.end = hose->mem_space.start +
YUCCA_PCIX_MEM_SIZE - 1;
} else {
hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
pcie_hose_num(hs) * YUCCA_PCIE_MEM_SIZE;
hose->mem_space.end = hose->mem_space.start +
YUCCA_PCIE_MEM_SIZE - 1;
}
pci_init_resource(&hose->mem_resources[0],
hose->mem_space.start,
hose->mem_space.end,
IORESOURCE_MEM,
name);
hose->first_busno = bus_no;
hose->last_busno = 0xFF;
hose_type[hose->index] = hs;
if (is_pcix_hose(hs)) {
hose->io_space.start = YUCCA_PCIX_LOWER_IO;
hose->io_space.end = YUCCA_PCIX_UPPER_IO;
isa_io_base =
(unsigned long)
ioremap64(PCIX0_IO_BASE, PCIX_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
ppc440spe_setup_pcix(hose);
setup_indirect_pci(hose, PCIX0_CFGA, PCIX0_CFGD);
hose->set_cfg_type = 1;
} else {
if(ppc440spe_setup_pcie(hose, pcie_hose_num(hs)) != 0)
{
printk(KERN_WARNING"PCIE setup failed for hose no %d\n",
pcie_hose_num(hs));
continue;
}
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
bus_no = hose->last_busno + 1;
pr_debug("%s: resources allocated\n", name);
}
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = yucca_map_irq;
}
static void __init hdpu_setup_bridge(void)
{
struct mv64x60_setup_info si;
int i;
memset(&si, 0, sizeof(si));
si.phys_reg_base = HDPU_BRIDGE_REG_BASE;
si.pci_0.enable_bus = 1;
si.pci_0.pci_io.cpu_base = HDPU_PCI0_IO_START_PROC_ADDR;
si.pci_0.pci_io.pci_base_hi = 0;
si.pci_0.pci_io.pci_base_lo = HDPU_PCI0_IO_START_PCI_ADDR;
si.pci_0.pci_io.size = HDPU_PCI0_IO_SIZE;
si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
si.pci_0.pci_mem[0].cpu_base = HDPU_PCI0_MEM_START_PROC_ADDR;
si.pci_0.pci_mem[0].pci_base_hi = HDPU_PCI0_MEM_START_PCI_HI_ADDR;
si.pci_0.pci_mem[0].pci_base_lo = HDPU_PCI0_MEM_START_PCI_LO_ADDR;
si.pci_0.pci_mem[0].size = HDPU_PCI0_MEM_SIZE;
si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
si.pci_0.pci_cmd_bits = 0;
si.pci_0.latency_timer = 0x80;
si.pci_1.enable_bus = 1;
si.pci_1.pci_io.cpu_base = HDPU_PCI1_IO_START_PROC_ADDR;
si.pci_1.pci_io.pci_base_hi = 0;
si.pci_1.pci_io.pci_base_lo = HDPU_PCI1_IO_START_PCI_ADDR;
si.pci_1.pci_io.size = HDPU_PCI1_IO_SIZE;
si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
si.pci_1.pci_mem[0].cpu_base = HDPU_PCI1_MEM_START_PROC_ADDR;
si.pci_1.pci_mem[0].pci_base_hi = HDPU_PCI1_MEM_START_PCI_HI_ADDR;
si.pci_1.pci_mem[0].pci_base_lo = HDPU_PCI1_MEM_START_PCI_LO_ADDR;
si.pci_1.pci_mem[0].size = HDPU_PCI1_MEM_SIZE;
si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
si.pci_1.pci_cmd_bits = 0;
si.pci_1.latency_timer = 0x80;
for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
#if defined(CONFIG_NOT_COHERENT_CACHE)
si.cpu_prot_options[i] = 0;
si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
si.pci_1.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_NONE |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
si.pci_0.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_NONE |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
si.cpu_prot_options[i] = 0;
si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; /* errata */
si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; /* errata */
si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; /* errata */
si.pci_0.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_WB |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
si.pci_1.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_WB |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#endif
}
hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_PCI);
/* Lookup PCI host bridges */
mv64x60_init(&bh, &si);
pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = hdpu_map_irq;
mv64x60_set_bus(&bh, 0, 0);
bh.hose_a->first_busno = 0;
bh.hose_a->last_busno = 0xff;
bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
bh.hose_b->last_busno = 0xff;
bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
bh.hose_b->first_busno);
ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG);
/*
* Enabling of PCI internal-vs-external arbitration
* is a platform- and errata-dependent decision.
*/
return;
}
void __init
mcpn765_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = MCPN765_PCI_PHY_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
MCPN765_PCI_IO_START,
MCPN765_PCI_IO_END,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
MCPN765_PCI_MEM_START,
MCPN765_PCI_MEM_END,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = MCPN765_PCI_IO_START;
hose->io_space.end = MCPN765_PCI_IO_END;
hose->mem_space.start = MCPN765_PCI_MEM_START;
hose->mem_space.end = MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE;
if (hawk_init(hose,
MCPN765_HAWK_PPC_REG_BASE,
MCPN765_PROC_PCI_MEM_START,
MCPN765_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
MCPN765_PROC_PCI_IO_START,
MCPN765_PROC_PCI_IO_END,
MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE + 1) != 0) {
printk("Could not initialize HAWK bridge\n");
}
/* VIA IDE BAR decoders are only 16-bits wide. PCI Auto Config
* will reassign the bars outside of 16-bit I/O space, which will
* "break" things. To prevent this, we'll set the IDE chip into
* legacy mode and seed the bars with their legacy addresses (in 16-bit
* I/O space). The Auto Config code will skip the IDE contoller in
* legacy mode, so our bar values will stick.
*/
mcpn765_set_VIA_IDE_legacy();
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
/* Now that we've got 16-bit addresses in the bars, we can switch the
* IDE controller back into native mode so we can do "modern" resource
* and interrupt management.
*/
mcpn765_set_VIA_IDE_native();
ppc_md.pcibios_fixup = mcpn765_pcibios_fixup;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mcpn765_map_irq;
return;
}
void
ppc4xx_find_bridges(void)
{
struct pci_controller *hose_a;
struct pcil0_regs *pcip;
unsigned int new_pmm_max;
unsigned int new_pmm_min;
isa_io_base = 0;
isa_mem_base = 0;
pci_dram_offset = 0;
#if (PSR_PCI_ARBIT_EN > 1)
/* Check if running in slave mode */
if ((mfdcr(DCRN_CHPSR) & PSR_PCI_ARBIT_EN) == 0) {
printk("Running as PCI slave, kernel PCI disabled !\n");
return;
}
#endif
/* Setup PCI32 hose */
hose_a = pcibios_alloc_controller();
if (!hose_a)
return;
setup_indirect_pci(hose_a, PPC405_PCI_CONFIG_ADDR,
PPC405_PCI_CONFIG_DATA);
#ifdef CONFIG_XILINX_OCP
/* Eliminate "unused variable" warning for pcip. Optimizer removes. */
pcip = NULL;
new_pmm_min = PPC405_PCI_LOWER_MEM;
new_pmm_max = PPC405_PCI_UPPER_MEM;
#else /* Must be IBM */
pcip = ioremap(PPC4xx_PCI_LCFG_PADDR, PAGE_SIZE);
if (pcip != NULL) {
unsigned int tmp_addr;
unsigned int tmp_size;
unsigned int reg_index;
#if defined(CONFIG_BIOS_FIXUP)
bios_fixup(hose_a, pcip);
#endif
new_pmm_min = 0xffffffff;
for (reg_index = 0; reg_index < 3; reg_index++) {
tmp_size = in_le32((void *) &(pcip->pmm[reg_index].ma)); // *_PMM0MA
if (tmp_size & 0x1) {
tmp_addr = in_le32((void *) &(pcip->pmm[reg_index].pcila)); // *_PMM0PCILA
if (tmp_addr < PPC405_PCI_PHY_MEM_BASE) {
printk(KERN_DEBUG
"Disabling mapping to PCI mem addr 0x%8.8x\n",
tmp_addr);
out_le32((void *) &(pcip->pmm[reg_index].ma), tmp_size & ~1); // *_PMMOMA
} else {
tmp_addr = in_le32((void *) &(pcip->pmm[reg_index].la)); // *_PMMOLA
if (tmp_addr < new_pmm_min)
new_pmm_min = tmp_addr;
tmp_addr =
tmp_addr + (0xffffffff -
(tmp_size &
0xffffc000));
if (tmp_addr > PPC405_PCI_UPPER_MEM) {
new_pmm_max = tmp_addr; // PPC405_PCI_UPPER_MEM
} else {
new_pmm_max =
PPC405_PCI_UPPER_MEM;
}
}
}
} // for
iounmap(pcip);
}
#endif
hose_a->first_busno = 0;
hose_a->last_busno = 0xff;
hose_a->pci_mem_offset = 0;
/* Setup bridge memory/IO ranges & resources
* TODO: Handle firmwares setting up a legacy ISA mem base
*/
hose_a->io_space.start = PPC405_PCI_LOWER_IO;
hose_a->io_space.end = PPC405_PCI_UPPER_IO;
hose_a->mem_space.start = new_pmm_min;
hose_a->mem_space.end = new_pmm_max;
hose_a->io_base_phys = PPC405_PCI_PHY_IO_BASE;
hose_a->io_base_virt = ioremap(hose_a->io_base_phys, 0x10000);
hose_a->io_resource.start = 0;
hose_a->io_resource.end = PPC405_PCI_UPPER_IO - PPC405_PCI_LOWER_IO;
hose_a->io_resource.flags = IORESOURCE_IO;
hose_a->io_resource.name = "PCI I/O";
hose_a->mem_resources[0].start = new_pmm_min;
hose_a->mem_resources[0].end = new_pmm_max;
hose_a->mem_resources[0].flags = IORESOURCE_MEM;
hose_a->mem_resources[0].name = "PCI Memory";
isa_io_base = (int) hose_a->io_base_virt;
isa_mem_base = 0; /* ISA not implemented */
ISA_DMA_THRESHOLD = 0x00ffffff; /* ??? ISA not implemented */
/* Scan busses & initial setup by pci_auto */
hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
/* Setup ppc_md */
ppc_md.pcibios_fixup = NULL;
ppc_md.pci_exclude_device = ppc4xx_exclude_device;
ppc_md.pcibios_fixup_resources = ppc405_pcibios_fixup_resources;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = ppc405_map_irq;
}
void __init
mpc83xx_setup_hose(void)
{
u32 val32;
volatile immr_clk_t * clk;
volatile law_t * pci_law;
struct pci_controller * hose1;
#ifdef CONFIG_MPC83xx_PCI2
struct pci_controller * hose2;
#endif
bd_t * binfo = (bd_t *)__res;
u8 val8;
clk = ioremap(binfo->bi_immr_base + 0xA00, sizeof(immr_clk_t));
pci_law = ioremap(binfo->bi_immr_base + 0x60, sizeof(law_t));
/* Configure PCI clock drivers */
val32 = clk->occr;
udelay(2000);
#ifdef CONFIG_CLK_DIV_ENABLE
clk->occr = 0xffff0003;
#else
clk->occr = 0xff000000;
#endif
udelay(2000);
iounmap(clk);
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = MPC83xx_PCI1_LOWER_MEM & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = MPC83xx_PCI1_IO_BASE & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
iounmap(pci_law);
#ifndef CONFIG_MPC834x_ITX
/*
* Configure PMC <-> PCI by I2C bus
*/
early_i2c_init(CFG_I2C_SPD,CFG_I2C_SLV);
val8 = 0;
early_i2c_write(0x23,0x6,1,&val8,1);
early_i2c_write(0x23,0x7,1,&val8,1);
val8 = 0xff;
early_i2c_write(0x23,0x2,1,&val8,1);
early_i2c_write(0x23,0x3,1,&val8,1);
val8 = 0;
early_i2c_write(0x26,0x6,1,&val8,1);
val8 = 0x34;
early_i2c_write(0x26,0x7,1,&val8,1);
#ifdef CONFIG_PCI_64BIT
val8 = 0xf4; /* 64bit PMC2<->PCI1 */
#elif defined(CONFIG_PCI_ONE_PCI1) || defined(CONFIG_MPC832XE_MDS)
val8 = 0xf9; /* 32bit PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 */
#elif defined(CONFIG_PCI_TWO_PCI1) || defined(CONFIG_MPC8360E_PB)
val8 = 0xf7; /* 32bit PMC1<->PCI1,PMC2<->PCI1 PCM3<->PCI2 disabled*/
#else
val8 = 0xf3; /* 32bit PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 */
#endif
early_i2c_write(0x26,0x2,1,&val8,1);
val8 = 0xff;
early_i2c_write(0x26,0x3,1,&val8,1);
val8 = 0;
early_i2c_write(0x27,0x6,1,&val8,1);
early_i2c_write(0x27,0x7,1,&val8,1);
val8 = 0xff;
early_i2c_write(0x27,0x2,1,&val8,1);
val8 = 0xef;
early_i2c_write(0x27,0x3,1,&val8,1);
asm("eieio");
#endif /* CONFIG_MPC834x_ITX */
hose1 = pcibios_alloc_controller();
if(!hose1)
return;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mpc83xx_map_irq;
hose1->bus_offset = 0;
hose1->first_busno = 0;
hose1->last_busno = 0xff;
setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
hose1->ops = &mpc83xx_indirect_pci_ops;
mpc83xx_setup_pci1(hose1);
hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
#ifdef CONFIG_MPC83xx_PCI2
isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
#else
isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
MPC83xx_PCI1_IO_SIZE);
#endif /* CONFIG_MPC83xx_PCI2 */
hose1->io_base_virt = (void *)isa_io_base;
/* setup resources */
pci_init_resource(&hose1->io_resource,
MPC83xx_PCI1_LOWER_IO,
MPC83xx_PCI1_UPPER_IO,
IORESOURCE_IO, "PCI host bridge 1");
pci_init_resource(&hose1->mem_resources[0],
MPC83xx_PCI1_LOWER_MEM,
MPC83xx_PCI1_UPPER_MEM,
IORESOURCE_MEM, "PCI host bridge 1");
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
#ifdef CONFIG_MPC83xx_PCI2
hose2 = pcibios_alloc_controller();
if(!hose2)
return;
hose2->bus_offset = hose1->last_busno + 1;
hose2->first_busno = hose1->last_busno + 1;
hose2->last_busno = 0xff;
setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
hose2->ops = &mpc83xx_indirect_pci_ops;
mpc83xx_setup_pci2(hose2);
hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
/* setup resources */
pci_init_resource(&hose2->io_resource,
MPC83xx_PCI2_LOWER_IO,
MPC83xx_PCI2_UPPER_IO,
IORESOURCE_IO, "PCI host bridge 2");
pci_init_resource(&hose2->mem_resources[0],
MPC83xx_PCI2_LOWER_MEM,
MPC83xx_PCI2_UPPER_MEM,
IORESOURCE_MEM, "PCI host bridge 2");
hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
#endif /* CONFIG_MPC83xx_PCI2 */
}
void __init ixdp2800_pci_init(void *sysdata)
{
ixp2000_pci_init(sysdata);
*IXP2000_PCI_CMDSTAT = 0;
*IXP2000_PCI_ADDR_EXT = 0x0000e000;
*IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x20000000 - 1) & ~0xfffff;
*IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x40000 - 1) & ~0x3ffff;
DBG("allocating hose\n");
hose = pcibios_alloc_controller();
if (!hose)
panic("Could not allocate PCI hose");
hose->first_busno = 0;
hose->last_busno = 0;
hose->io_space.start = 0x00000000;
hose->io_space.end = 0x0000ffff;
hose->mem_space.start = 0xe0000000;
hose->mem_space.end = 0xffffffff;
/*
* Scan bus and exclude devices depending on whether we are the
* master or slave NPU. Sigh...
*
* NOTE TO HW DESIGNERS: DO NOT PUT MULTIPLE PCI HOST CPUS
* ON THE SAME BUS SEGMENT. THAT'S WHAT NON-TRANSPARENT
* BRIDGES ARE FOR.
*/
if (npu_is_master()) {
DBG("setup BARS\n");
*IXP2000_PCI_SDRAM_BAR = PHYS_OFFSET;
*IXP2000_PCI_CMDSTAT = (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* autoconfig the bus */
DBG("AUTOCONFIG\n");
hose->last_busno = pciauto_bus_scan(hose, 0);
/* scan the bus */
DBG("SCANNING THE BUS\n");
pci_scan_bus(0,&ixp2000_ops, sysdata);
pci_exclude_device(0x01, 0x20); /* Remove slave's NIC*/
pci_exclude_device(0x0, 0x38); /* Remove self XXX FIXME*/
} else {
/* Wait for the master NPU to enable us */
while(!(*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER));
pci_scan_bus(0,&ixp2000_ops, sysdata);
int i;
pci_exclude_device(0x01, 0x38); /* Remove PMC site */
pci_exclude_device(0x01, 0x18); /* Remove master NIC*/
pci_exclude_device(0x0, 0x20); /* Remove remove 21154*/
pci_exclude_device(0x0, 0x30); /* Remove 21555*/
pci_exclude_device(0x0, 0x28); /* Remove Self XXX FIXME */
/*
* need to keep for IXA SDK support
*/
#if 0
pci_exclude_device(0x0, 0x38); /* Remove Master IXP*/
#endif
/*
* In case there's a bridge on the PMC, we remove everything
* on bus 2.
*/
for(i = 0; i < 0xff; i++)
pci_exclude_device(0x2, i);
}
}
void __init
katana_setup_peripherals(void)
{
u32 base;
/* Set up windows for boot CS, soldered & socketed flash, and CPLD */
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
/* Assume firmware set up window sizes correctly for dev 0 & 1 */
mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base,
&katana_flash_size_0);
if (katana_flash_size_0 > 0) {
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
}
mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base,
&katana_flash_size_1);
if (katana_flash_size_1 > 0) {
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
(KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0),
katana_flash_size_1, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
}
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
/* Set up Enet->SRAM window */
mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
/* Give enet r/w access to memory region */
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
/* Must wait until window set up before retrieving board id */
katana_get_board_id();
/* Enumerate pci bus (must know board id before getting proc number) */
if (katana_get_proc_num() == 0)
bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
#if defined(CONFIG_NOT_COHERENT_CACHE)
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
#else
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
/*
* Setting the SRAM to 0. Note that this generates parity errors on
* internal data path in SRAM since it's first time accessing it
* while after reset it's not configured.
*/
memset(sram_base, 0, MV64360_SRAM_SIZE);
/* Only processor zero [on 3750] is an PCI interrupt controller */
if (katana_get_proc_num() == 0)
katana_intr_setup();
}
static void __init
luan_setup_hoses(void)
{
struct pci_controller *hose0, *hose1, *hose2;
int last_busno = -1;
/* Configure windows on the PCI-X host bridge */
luan_setup_pcix();
/* Setup PCIX0 */
if (SDR_READ(0x01c0) & 0x20000000) {
hose0 = pcibios_alloc_controller();
if (!hose0)
return;
hose0->first_busno = 0;
hose0->last_busno = 0xff;
hose0->index = 0;
luan_setup_hose(hose0,
LUAN_PCIX0_LOWER_MEM,
LUAN_PCIX0_UPPER_MEM,
PCIX0_CFGA,
PCIX0_CFGD,
PCIX0_IO_BASE);
last_busno = hose0->last_busno =
pciauto_bus_scan(hose0, hose0->first_busno);
}
/* Setup PCIX1 */
if (SDR_READ(0x01c3) & 0x20000000) {
hose1 = pcibios_alloc_controller();
if (!hose1)
return;
hose1->first_busno = last_busno + 1;
hose1->last_busno = 0xff;
hose1->index = 1;
luan_setup_hose(hose1,
LUAN_PCIX1_LOWER_MEM,
LUAN_PCIX1_UPPER_MEM,
PCIX1_CFGA,
PCIX1_CFGD,
PCIX1_IO_BASE);
last_busno = hose1->last_busno =
pciauto_bus_scan(hose1, hose1->first_busno);
}
/* Setup PCIX2 */
if (SDR_READ(0x01c6) & 0x20000000) {
hose2 = pcibios_alloc_controller();
if (!hose2)
return;
hose2->first_busno = last_busno + 1;
hose2->last_busno = 0xff;
hose2->index = 2;
luan_setup_hose(hose2,
LUAN_PCIX2_LOWER_MEM,
LUAN_PCIX2_UPPER_MEM,
PCIX2_CFGA,
PCIX2_CFGD,
PCIX2_IO_BASE);
hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
}
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = luan_map_irq;
}
void
ppc4xx_find_bridges(void)
{
struct pci_controller *hose_a;
struct pcil0_regs *pcip;
unsigned int tmp_addr;
unsigned int tmp_size;
unsigned int reg_index;
unsigned int new_pmm_max = 0;
unsigned int new_pmm_min = 0;
isa_io_base = 0;
isa_mem_base = 0;
pci_dram_offset = 0;
/* Setup PCI32 hose */
hose_a = pcibios_alloc_controller();
if (!hose_a)
return;
setup_indirect_pci(hose_a, PPC405_PCI_CONFIG_ADDR,
PPC405_PCI_CONFIG_DATA);
pcip = ioremap(PPC4xx_PCI_LCFG_PADDR, PAGE_SIZE);
if (pcip != NULL) {
#if defined(CONFIG_BIOS_FIXUP)
bios_fixup(hose_a, pcip);
#endif
new_pmm_min = 0xffffffff;
for (reg_index = 0; reg_index < 3; reg_index++) {
tmp_size = in_le32(&pcip->pmm[reg_index].ma); // mask & attrs
/* test the enable bit */
if ((tmp_size & 0x1) == 0)
continue;
tmp_addr = in_le32(&pcip->pmm[reg_index].pcila); // PCI addr
if (tmp_addr < PPC405_PCI_PHY_MEM_BASE) {
printk(KERN_DEBUG
"Disabling mapping to PCI mem addr 0x%8.8x\n",
tmp_addr);
out_le32(&pcip->pmm[reg_index].ma, tmp_size & ~1); // *_PMMOMA
continue;
}
tmp_addr = in_le32(&pcip->pmm[reg_index].la); // *_PMMOLA
if (tmp_addr < new_pmm_min)
new_pmm_min = tmp_addr;
tmp_addr = tmp_addr +
(0xffffffff - (tmp_size & 0xffffc000));
if (tmp_addr > PPC405_PCI_UPPER_MEM) {
new_pmm_max = tmp_addr; // PPC405_PCI_UPPER_MEM
} else {
new_pmm_max = PPC405_PCI_UPPER_MEM;
}
} // for
iounmap(pcip);
}
hose_a->first_busno = 0;
hose_a->last_busno = 0xff;
hose_a->pci_mem_offset = 0;
/* Setup bridge memory/IO ranges & resources
* TODO: Handle firmwares setting up a legacy ISA mem base
*/
hose_a->io_space.start = PPC405_PCI_LOWER_IO;
hose_a->io_space.end = PPC405_PCI_UPPER_IO;
hose_a->mem_space.start = new_pmm_min;
hose_a->mem_space.end = new_pmm_max;
hose_a->io_base_phys = PPC405_PCI_PHY_IO_BASE;
hose_a->io_base_virt = ioremap(hose_a->io_base_phys, 0x10000);
hose_a->io_resource.start = 0;
hose_a->io_resource.end = PPC405_PCI_UPPER_IO - PPC405_PCI_LOWER_IO;
hose_a->io_resource.flags = IORESOURCE_IO;
hose_a->io_resource.name = "PCI I/O";
hose_a->mem_resources[0].start = new_pmm_min;
hose_a->mem_resources[0].end = new_pmm_max;
hose_a->mem_resources[0].flags = IORESOURCE_MEM;
hose_a->mem_resources[0].name = "PCI Memory";
isa_io_base = (int) hose_a->io_base_virt;
isa_mem_base = 0; /* ISA not implemented */
ISA_DMA_THRESHOLD = 0x00ffffff; /* ??? ISA not implemented */
/* Scan busses & initial setup by pci_auto */
hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
hose_a->last_busno = 0;
/* Setup ppc_md */
ppc_md.pcibios_fixup = NULL;
ppc_md.pci_exclude_device = ppc4xx_exclude_device;
ppc_md.pcibios_fixup_resources = ppc405_pcibios_fixup_resources;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = ppc405_map_irq;
}
void adir_find_bridges(void)
{
struct pci_controller *hose_a, *hose_b;
/* Setup PCI32 hose */
hose_a = pcibios_alloc_controller();
if (!hose_a)
return;
hose_a->first_busno = 0;
hose_a->last_busno = 0xff;
hose_a->pci_mem_offset = ADIR_PCI32_MEM_BASE;
hose_a->io_space.start = 0;
hose_a->io_space.end = ADIR_PCI32_VIRT_IO_SIZE - 1;
hose_a->mem_space.start = 0;
hose_a->mem_space.end = ADIR_PCI32_MEM_SIZE - 1;
hose_a->io_resource.start = 0;
hose_a->io_resource.end = ADIR_PCI32_VIRT_IO_SIZE - 1;
hose_a->io_resource.flags = IORESOURCE_IO;
hose_a->mem_resources[0].start = ADIR_PCI32_MEM_BASE;
hose_a->mem_resources[0].end = ADIR_PCI32_MEM_BASE +
ADIR_PCI32_MEM_SIZE - 1;
hose_a->mem_resources[0].flags = IORESOURCE_MEM;
hose_a->io_base_phys = ADIR_PCI32_IO_BASE;
hose_a->io_base_virt = (void *) ADIR_PCI32_VIRT_IO_BASE;
ppc_md.pci_exclude_device = adir_exclude_device;
setup_indirect_pci(hose_a, ADIR_PCI32_CONFIG_ADDR,
ADIR_PCI32_CONFIG_DATA);
/* Initialize PCI32 bus registers */
early_write_config_byte(hose_a,
hose_a->first_busno,
PCI_DEVFN(0, 0),
CPC710_BUS_NUMBER,
hose_a->first_busno);
early_write_config_byte(hose_a,
hose_a->first_busno,
PCI_DEVFN(0, 0),
CPC710_SUB_BUS_NUMBER,
hose_a->last_busno);
hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
/* Write out correct max subordinate bus number for hose A */
early_write_config_byte(hose_a,
hose_a->first_busno,
PCI_DEVFN(0, 0),
CPC710_SUB_BUS_NUMBER,
hose_a->last_busno);
/* Setup PCI64 hose */
hose_b = pcibios_alloc_controller();
if (!hose_b)
return;
hose_b->first_busno = hose_a->last_busno + 1;
hose_b->last_busno = 0xff;
hose_b->pci_mem_offset = ADIR_PCI64_MEM_BASE;
hose_b->io_space.start = 0;
hose_b->io_space.end = ADIR_PCI64_VIRT_IO_SIZE - 1;
hose_b->mem_space.start = 0;
hose_b->mem_space.end = ADIR_PCI64_MEM_SIZE - 1;
hose_b->io_resource.start = 0;
hose_b->io_resource.end = ADIR_PCI64_VIRT_IO_SIZE - 1;
hose_b->io_resource.flags = IORESOURCE_IO;
hose_b->mem_resources[0].start = ADIR_PCI64_MEM_BASE;
hose_b->mem_resources[0].end = ADIR_PCI64_MEM_BASE +
ADIR_PCI64_MEM_SIZE - 1;
hose_b->mem_resources[0].flags = IORESOURCE_MEM;
hose_b->io_base_phys = ADIR_PCI64_IO_BASE;
hose_b->io_base_virt = (void *) ADIR_PCI64_VIRT_IO_BASE;
setup_indirect_pci(hose_b, ADIR_PCI64_CONFIG_ADDR,
ADIR_PCI64_CONFIG_DATA);
/* Initialize PCI64 bus registers */
early_write_config_byte(hose_b,
0,
PCI_DEVFN(0, 0),
CPC710_SUB_BUS_NUMBER,
0xff);
early_write_config_byte(hose_b,
0,
PCI_DEVFN(0, 0),
CPC710_BUS_NUMBER,
hose_b->first_busno);
hose_b->last_busno = pciauto_bus_scan(hose_b,
hose_b->first_busno);
/* Write out correct max subordinate bus number for hose B */
early_write_config_byte(hose_b,
hose_b->first_busno,
PCI_DEVFN(0, 0),
CPC710_SUB_BUS_NUMBER,
hose_b->last_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = adir_map_irq;
}
