void pciauto_config_init(struct pci_controller *hose)
{
int i;
hose->pci_io = hose->pci_mem = NULL;
for (i=0; i<hose->region_count; i++) {
switch(hose->regions[i].flags) {
case PCI_REGION_IO:
if (!hose->pci_io ||
hose->pci_io->size < hose->regions[i].size)
hose->pci_io = hose->regions + i;
break;
case PCI_REGION_MEM:
if (!hose->pci_mem ||
hose->pci_mem->size < hose->regions[i].size)
hose->pci_mem = hose->regions + i;
break;
}
}
if (hose->pci_mem) {
pciauto_region_init(hose->pci_mem);
DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
hose->pci_mem->bus_start,
hose->pci_mem->bus_start + hose->pci_mem->size - 1);
}
if (hose->pci_io) {
pciauto_region_init(hose->pci_io);
DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
hose->pci_io->bus_start,
hose->pci_io->bus_start + hose->pci_io->size - 1);
}
}
/*-----------------------------------------------------------------------------+
* pci_init. Initializes the 405GP PCI Configuration regs.
*-----------------------------------------------------------------------------*/
void pci_405gp_init(struct pci_controller *hose)
{
int i, reg_num = 0;
bd_t *bd = gd->bd;
unsigned short temp_short;
unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
char *ptmla_str, *ptmms_str;
#endif
unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
#else
unsigned long pmmla[3] = {0x80000000, 0,0};
unsigned long pmmma[3] = {0xC0000001, 0,0};
unsigned long pmmpcila[3] = {0x80000000, 0,0};
unsigned long pmmpciha[3] = {0x00000000, 0,0};
#endif
#ifdef CONFIG_PCI_PNP
#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
char *s;
#endif
#endif
#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
ptmla_str = getenv("ptm1la");
ptmms_str = getenv("ptm1ms");
if(NULL != ptmla_str && NULL != ptmms_str ) {
ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
}
ptmla_str = getenv("ptm2la");
ptmms_str = getenv("ptm2ms");
if(NULL != ptmla_str && NULL != ptmms_str ) {
ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
}
#endif
/*
* Register the hose
*/
hose->first_busno = 0;
hose->last_busno = 0xff;
/* ISA/PCI I/O space */
pci_set_region(hose->regions + reg_num++,
MIN_PCI_PCI_IOADDR,
MIN_PLB_PCI_IOADDR,
0x10000,
PCI_REGION_IO);
/* PCI I/O space */
pci_set_region(hose->regions + reg_num++,
0x00800000,
0xe8800000,
0x03800000,
PCI_REGION_IO);
reg_num = 2;
/* Memory spaces */
for (i=0; i<2; i++)
if (ptmms[i] & 1)
{
if (!i) hose->pci_fb = hose->regions + reg_num;
pci_set_region(hose->regions + reg_num++,
ptmpcila[i], ptmla[i],
~(ptmms[i] & 0xfffff000) + 1,
PCI_REGION_MEM |
PCI_REGION_SYS_MEMORY);
}
/* PCI memory spaces */
for (i=0; i<3; i++)
if (pmmma[i] & 1)
{
pci_set_region(hose->regions + reg_num++,
pmmpcila[i], pmmla[i],
~(pmmma[i] & 0xfffff000) + 1,
PCI_REGION_MEM);
}
hose->region_count = reg_num;
pci_setup_indirect(hose,
PCICFGADR,
PCICFGDATA);
if (hose->pci_fb)
pciauto_region_init(hose->pci_fb);
/* Let board change/modify hose & do initial checks */
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
}
pci_register_hose(hose);
/*--------------------------------------------------------------------------+
* 405GP PCI Master configuration.
* Map one 512 MB range of PLB/processor addresses to PCI memory space.
* PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
* Use byte reversed out routines to handle endianess.
*--------------------------------------------------------------------------*/
out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
out32r(PMM0LA, pmmla[0]);
out32r(PMM0PCILA, pmmpcila[0]);
out32r(PMM0PCIHA, pmmpciha[0]);
out32r(PMM0MA, pmmma[0]);
/*--------------------------------------------------------------------------+
* PMM1 is not used. Initialize them to zero.
*--------------------------------------------------------------------------*/
out32r(PMM1MA, (pmmma[1]&~0x1));
out32r(PMM1LA, pmmla[1]);
out32r(PMM1PCILA, pmmpcila[1]);
out32r(PMM1PCIHA, pmmpciha[1]);
out32r(PMM1MA, pmmma[1]);
/*--------------------------------------------------------------------------+
* PMM2 is not used. Initialize them to zero.
*--------------------------------------------------------------------------*/
out32r(PMM2MA, (pmmma[2]&~0x1));
out32r(PMM2LA, pmmla[2]);
out32r(PMM2PCILA, pmmpcila[2]);
out32r(PMM2PCIHA, pmmpciha[2]);
out32r(PMM2MA, pmmma[2]);
/*--------------------------------------------------------------------------+
* 405GP PCI Target configuration. (PTM1)
* Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
*--------------------------------------------------------------------------*/
out32r(PTM1LA, ptmla[0]); /* insert address */
out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
/*--------------------------------------------------------------------------+
* 405GP PCI Target configuration. (PTM2)
*--------------------------------------------------------------------------*/
out32r(PTM2LA, ptmla[1]); /* insert address */
pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
if (ptmms[1] == 0)
{
out32r(PTM2MS, 0x00000001); /* set enable bit */
pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
out32r(PTM2MS, 0x00000000); /* disable */
}
else
{
out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
}
/*
* Insert Subsystem Vendor and Device ID
*/
pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
#ifdef CONFIG_CPCI405
if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
else
pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
#else
pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
#endif
/*
* Insert Class-code
*/
#ifdef CONFIG_SYS_PCI_CLASSCODE
pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
#endif /* CONFIG_SYS_PCI_CLASSCODE */
/*--------------------------------------------------------------------------+
* If PCI speed = 66MHz, set 66MHz capable bit.
*--------------------------------------------------------------------------*/
if (bd->bi_pci_busfreq >= 66000000) {
pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
}
#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
(((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
#endif
{
/*--------------------------------------------------------------------------+
* Write the 405GP PCI Configuration regs.
* Enable 405GP to be a master on the PCI bus (PMM).
* Enable 405GP to act as a PCI memory target (PTM).
*--------------------------------------------------------------------------*/
pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}
#endif
#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
#endif
/*
* Set HCE bit (Host Configuration Enabled)
*/
pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
#ifdef CONFIG_PCI_PNP
/*--------------------------------------------------------------------------+
* Scan the PCI bus and configure devices found.
*--------------------------------------------------------------------------*/
#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
(((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
#endif
{
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI_PNP */
}
