void
reset_for_srm(void)
{
struct srm_irq_reset *qreset;
struct srm_io_reset *ireset;
/* Reset any IRQs that we changed. */
for (qreset = srm_irq_resets; qreset ; qreset = qreset->next) {
pcibios_write_config_byte(qreset->dev->bus->number,
qreset->dev->devfn,
PCI_INTERRUPT_LINE,
qreset->irq);
#if 1
printk("reset_for_srm: bus %d slot 0x%x "
"SRM IRQ 0x%x changed back from 0x%x\n",
qreset->dev->bus->number,
PCI_SLOT(qreset->dev->devfn),
qreset->irq, qreset->dev->irq);
#endif
}
/* Reset any IO addresses that we changed. */
for (ireset = srm_io_resets; ireset ; ireset = ireset->next) {
pcibios_write_config_dword(ireset->dev->bus->number,
ireset->dev->devfn,
ireset->reg, ireset->io);
#if 1
printk("reset_for_srm: bus %d slot 0x%x "
"SRM MEM/IO restored to 0x%x\n",
ireset->dev->bus->number,
PCI_SLOT(ireset->dev->devfn),
ireset->io);
#endif
}
}
/*
* Dword write to configuration space of primary PCI bus.
*/
static void
pconfig_write(int addr, int val)
{
#ifdef PCI_SUPPORT_VER2
pci_write_config_dword(safl_pdev, addr, val);
#else
pcibios_write_config_dword(safl_pci_bus, safl_pci_devfn, addr, val);
#endif
}
void smbus_enable(void)
{
/* iobase addr */
pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
/* smbus enable */
pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN);
/* iospace enable */
pcibios_write_config_word(PM_BUS, PM_DEVFN, PCI_COMMAND, PCI_COMMAND_IO);
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
}
void smbus_enable(void)
{
unsigned char byte;
/* iobase addr */
pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1);
/* smbus enable */
pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1);
/* iospace enable */
pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
}
asmlinkage int
sys_pciconfig_write(unsigned long bus, unsigned long dfn,
unsigned long off, unsigned long len,
unsigned char *buf)
{
unsigned char ubyte;
unsigned short ushort;
unsigned int uint;
long err = 0;
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
if (!pcibios_present())
return -ENOSYS;
switch (len) {
case 1:
err = get_user(ubyte, buf);
if (err)
break;
err = pcibios_write_config_byte(bus, dfn, off, ubyte);
if (err != PCIBIOS_SUCCESSFUL) {
err = -EFAULT;
}
break;
case 2:
err = get_user(ushort, (unsigned short *)buf);
if (err)
break;
err = pcibios_write_config_word(bus, dfn, off, ushort);
if (err != PCIBIOS_SUCCESSFUL) {
err = -EFAULT;
}
break;
case 4:
err = get_user(uint, (unsigned int *)buf);
if (err)
break;
err = pcibios_write_config_dword(bus, dfn, off, uint);
if (err != PCIBIOS_SUCCESSFUL) {
err = -EFAULT;
}
break;
default:
err = -EINVAL;
break;
}
return err;
}
void UxPciConfigWrite(ux_diva_card_t *card, int size, int offset, void *value)
{
switch (size)
{
case sizeof(byte):
pcibios_write_config_byte(card->bus_num, card->func_num, offset, * (byte *) value);
break;
case sizeof(word):
pcibios_write_config_word(card->bus_num, card->func_num, offset, * (word *) value);
break;
case sizeof(dword):
pcibios_write_config_dword(card->bus_num, card->func_num, offset, * (dword *) value);
break;
default:
printk(KERN_WARNING "Divas: Invalid size in UxPciConfigWrite\n");
}
}
__initfunc(int w83c553f_init(void))
{
u_char bus, dev;
#if 0
unsigned char t8;
unsigned short t16;
#endif
unsigned int t32;
struct pci_dev *pdev;
if ((pdev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_83C553, NULL))) {
bus = pdev->bus->number;
dev = pdev->devfn + 1;
pcibios_read_config_dword(bus, dev, PCI_VENDOR_ID, &t32);
if (t32 == (PCI_DEVICE_ID_WINBOND_82C105<<16) + PCI_VENDOR_ID_WINBOND) {
#if 0
printk("Enabling SL82C105 IDE on W83C553F\n");
/*
* FIXME: this doesn't help :-(
*/
/* I/O mapping */
pcibios_read_config_word(bus, dev, PCI_COMMAND, &t16);
t16 |= PCI_COMMAND_IO;
pcibios_write_config_word(bus, dev, PCI_COMMAND, t16);
/* Standard IDE registers */
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_0,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_0, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_0,
0x000001f0 | 1);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_1,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_1, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_1,
0x000003f4 | 1);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_2,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_2, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_2,
0x00000170 | 1);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_3,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_3, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_3,
0x00000374 | 1);
/* IDE Bus Master Control */
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_4,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_4, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_4,
0x1000 | 1);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_5,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_5, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_5,
0x1010 | 1);
/* IDE Interrupt */
pcibios_read_config_byte(bus, dev, PCI_INTERRUPT_LINE, &t8);
chrp_ide_irq = t8;
#endif
return 1;
}
}
return 0;
}
/*
scan the pci bus
look for vendor/device Id == Siemens PITA
if found
look for subvendor id
if found
write to pita register 1c in the first address range the value 0x04000000
*/
int pcimod_scan(void)
{
int i, pos = 0;
int bus, fun;
unsigned char headertype = 0;
u32 id;
u32 vdid; /* vendor/device id */
int candev = 0; /* number of found devices */
if (!pcibios_present()) {
printk("CAN: No PCI bios present\n");
return ENODEV;
}
/* printk("CAN: PCI bios present!\n"); */
/*
* This code is derived from "drivers/pci/pci.c". This means that
* the GPL applies to this source file and credit is due to the
* original authors (Drew Eckhardt, Frederic Potter, David
* Mosberger-Tang)
*/
for (bus = 0; !bus; bus++) { /* only bus 0 :-) */
for (fun=0; fun < 0x100 && pos < PAGE_SIZE; fun++) {
if (!PCI_FUNC(fun)) /* first function */
pcibios_read_config_byte(bus,fun,PCI_HEADER_TYPE, &headertype);
else if (!(headertype & 0x80))
continue;
/* the following call gets vendor AND device ID */
pcibios_read_config_dword(bus, fun, PCI_VENDOR_ID, &id);
if (!id || id == ~0) {
headertype = 0; continue;
}
/* v-endor and d-evice id */
vdid = id;
#if 0
printk(" -- found pci device, vendor id = %u/0x%x , device 0x%x\n",
(id & 0xffff), (id & 0xffff), (id >> 16));
#endif
pcibios_read_config_dword(bus, fun, PCI_CLASS_REVISION, &id);
#if 0
printk(" class 0x%x, Revision %d\n",
(id >> 8), (id & 0x0ff));
#endif
if(vdid == (PCI_VENDOR + (PCI_DEVICE << 16))) {
unsigned char irq;
u16 cmd;
u32 svdid; /* subsystem vendor/device id */
/* found EMS CAN CPC-PCI */
vdid = 0; /* reset it */
printk(" found Siemens PITA PCI-Chip\n");
pcibios_read_config_byte(bus, fun, PCI_INTERRUPT_LINE, &irq);
printk(" using IRQ %d\n", irq);
pcibios_read_config_word(bus, fun, PCI_COMMAND, &cmd);
/* printk(" cmd: 0x%x\n", cmd); */
/* PCI_COMMAND should be at least PCI_COMMAND_MEMORY */
pcibios_write_config_word(bus, fun,
/* PCI_COMMAND, PCI_COMMAND_MEMORY); */
PCI_COMMAND, PCI_COMMAND_MEMORY + PCI_COMMAND_MASTER );
pcibios_read_config_word(bus, fun, PCI_COMMAND, &cmd);
/* printk(" cmd: 0x%x\n", cmd); */
pcibios_read_config_dword(bus, fun, PCI_SUBSYSTEM_VENDOR_ID, &svdid);
/* printk(" s_vendor 0x%x, s_device 0x%x\n", */
/* (svdid & 0xffff), (svdid >> 16)); */
/* How can we be sure that that is an EMS CAN card ?? */
for (i = 0; addresses[i]; i++) {
u32 curr, mask;
char *type;
pcibios_read_config_dword(bus, fun, addresses[i], &curr);
cli();
pcibios_write_config_dword(bus, fun, addresses[i], ~0);
pcibios_read_config_dword(bus, fun, addresses[i], &mask);
pcibios_write_config_dword(bus, fun, addresses[i], curr);
sti();
/* printk(" region %i: mask 0x%08lx, now at 0x%08lx\n", i, */
/* (unsigned long)mask, */
/* (unsigned long)curr); */
#if 0 /* we don't need this message, so we don't need this code */
if (!mask) {
printk(" region %i not existent\n", i);
break;
}
#endif
/* extract the type, and the programmable bits */
if (mask & PCI_BASE_ADDRESS_SPACE) {
type = "I/O"; mask &= PCI_BASE_ADDRESS_IO_MASK;
} else {
type = "mem"; mask &= PCI_BASE_ADDRESS_MEM_MASK;
}
/* printk(" region %i: type %s, size %i\n", i, */
/* type, ~mask+1); */
if(i == 0) {
/* BAR0 internal PITA registers */
unsigned long ptr = (unsigned long)ioremap(curr, 256);
/* enable memory access */
/* printk("write to pita\n"); */
writel(0x04000000, ptr + 0x1c);
Can_pitapci_control[candev] = ptr;
}
if(i == 1) {
/* BAR1 parallel I/O
* at address 0 are some EMS control registers
* at address 0x400 the first controller area
* at address 0x600 the second controller area
* registers are read as 32bit
*
* at adress 0 we can verify the card
* 0x55 0xaa 0x01 0xcb
*/
/* dump_CAN(curr, 4); */
reset_CPC_PCI(curr);
/* enable interrupts Int_0 */
/* write to PITAs ICR register */
writel(0x00020000, Can_pitapci_control[candev] + 0x0);
/* dump_CAN(curr + 0x400, 4); */
if(controller_available(curr + 0x400, 4)) {
printk("CAN: at pos 1\n");
if(candev > 4) {
printk("CAN: only 4 devices supported\n");
break; /* the devices scan loop */
}
Base[candev]
= (unsigned long)ioremap(curr + 0x400, 32*4);
IOModel[candev] = 'm';
IRQ[candev] = irq;
candev++;
} else {
printk("CAN: NO at pos 1\n");
}
/* dump_CAN(curr + 0x600, 4); */
if(controller_available(curr + 0x600, 4)) {
printk("CAN: at pos 2\n");
if(candev > 4) {
printk("CAN: only 4 devices supported\n");
break; /* the devices scan loop */
}
/* share the board control register with prev ch */
Can_pitapci_control[candev] =
Can_pitapci_control[candev - 1];
Base[candev]
= (unsigned long)ioremap(curr + 0x600, 32*4);
IOModel[candev] = 'm';
IRQ[candev] = irq;
candev++;
} else {
printk("CAN: NO at pos 2\n");
}
}
}
} /* EMS CPC-PCI */
} /* for all devices */
} /* for all busses */
return 0;
}
void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v)
{
pcibios_write_config_dword(bus, (dev<<3)|func, reg, v);
}
__initfunc(int
setup_sct_quadro(struct IsdnCard *card))
{
struct IsdnCardState *cs = card->cs;
char tmp[64];
#if CONFIG_PCI
u_char pci_bus = 0, pci_device_fn = 0, pci_irq = 0, pci_rev_id;
u_int found = 0;
u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
#endif
strcpy(tmp, sct_quadro_revision);
printk(KERN_INFO "HiSax: T-Berkom driver Rev. %s\n", HiSax_getrev(tmp));
if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
cs->subtyp = SCT_1; /* Preset */
} else
return (0);
/* Identify subtype by para[0] */
if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
cs->subtyp = card->para[0];
else
printk(KERN_WARNING "HiSax: %s: Invalid subcontroller in configuration, default to 1\n",
CardType[card->typ]);
#if CONFIG_PCI
if (!pci_present()) {
printk(KERN_ERR "bkm_a4t: no PCI bus present\n");
return (0);
}
if ((dev_a8 = pci_find_device(PLX_VENDOR_ID, PLX_DEVICE_ID, dev_a8))) {
u_int sub_sys_id = 0;
pci_read_config_dword(dev_a8, PCI_SUBSYSTEM_VENDOR_ID,
&sub_sys_id);
if (sub_sys_id == ((SCT_SUBSYS_ID << 16) | SCT_SUBVEN_ID)) {
found = 1;
pci_ioaddr1 = dev_a8->base_address[ 1];
pci_irq = dev_a8->irq;
pci_bus = dev_a8->bus->number;
pci_device_fn = dev_a8->devfn;
}
}
if (!found) {
printk(KERN_WARNING "HiSax: %s (%s): Card not found\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
if (!pci_irq) { /* IRQ range check ?? */
printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
#ifdef ATTEMPT_PCI_REMAPPING
/* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
pcibios_read_config_byte(pci_bus, pci_device_fn, PCI_REVISION_ID, &pci_rev_id);
if ((pci_ioaddr1 & 0x80) && (pci_rev_id == 1)) {
printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
/* Restart PCI negotiation */
pcibios_write_config_dword(pci_bus, pci_device_fn,
PCI_BASE_ADDRESS_1, (u_int) - 1);
/* Move up by 0x80 byte */
pci_ioaddr1 += 0x80;
pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
pcibios_write_config_dword(pci_bus, pci_device_fn,
PCI_BASE_ADDRESS_1, pci_ioaddr1);
dev_a8->base_address[ 1] = pci_ioaddr1;
}
/* End HACK */
#endif
pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
/* Take over */
cs->irq = pci_irq;
cs->irq_flags |= SA_SHIRQ;
/* pci_ioaddr1 is unique to all subdevices */
/* pci_ioaddr2 is for the fourth subdevice only */
/* pci_ioaddr3 is for the third subdevice only */
/* pci_ioaddr4 is for the second subdevice only */
/* pci_ioaddr5 is for the first subdevice only */
cs->hw.ax.plx_adr = pci_ioaddr1;
/* Enter all ipac_base addresses */
ipac_state[SCT_1].base = pci_ioaddr5 + 0x00;
ipac_state[SCT_2].base = pci_ioaddr4 + 0x08;
ipac_state[SCT_3].base = pci_ioaddr3 + 0x10;
ipac_state[SCT_4].base = pci_ioaddr2 + 0x20;
/* For isac and hscx control path */
cs->hw.ax.base = ipac_state[cs->subtyp].base;
/* For isac and hscx data path */
cs->hw.ax.data_adr = cs->hw.ax.base + 4;
#else
printk(KERN_WARNING "HiSax: %s (%s): NO_PCI_BIOS\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
printk(KERN_WARNING "HiSax: %s (%s): Unable to configure\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
return (0);
#endif /* CONFIG_PCI */
printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4X, 0x%.4X, 0x%.4X and IRQ %d\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp],
cs->hw.ax.plx_adr,
cs->hw.ax.base,
cs->hw.ax.data_adr,
cs->irq);
test_and_set_bit(HW_IPAC, &cs->HW_Flags);
/* Disable all currently not active ipacs */
if (!is_ipac_active(SCT_1))
set_ipac_active(SCT_1, 0);
if (!is_ipac_active(SCT_2))
set_ipac_active(SCT_2, 0);
if (!is_ipac_active(SCT_3))
set_ipac_active(SCT_3, 0);
if (!is_ipac_active(SCT_4))
set_ipac_active(SCT_4, 0);
/* Perfom general reset (if possible) */
reset_bkm(cs);
cs->readisac = &ReadISAC;
cs->writeisac = &WriteISAC;
cs->readisacfifo = &ReadISACfifo;
cs->writeisacfifo = &WriteISACfifo;
cs->BC_Read_Reg = &ReadHSCX;
cs->BC_Write_Reg = &WriteHSCX;
cs->BC_Send_Data = &hscx_fill_fifo;
cs->cardmsg = &BKM_card_msg;
cs->irq_func = &bkm_interrupt_ipac;
printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp],
readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
return (1);
}
int __init
setup_sct_quadro(struct IsdnCard *card)
{
#if CONFIG_PCI
struct IsdnCardState *cs = card->cs;
char tmp[64];
u_char pci_rev_id;
u_int found = 0;
u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
strcpy(tmp, sct_quadro_revision);
printk(KERN_INFO "HiSax: T-Berkom driver Rev. %s\n", HiSax_getrev(tmp));
if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
cs->subtyp = SCT_1; /* Preset */
} else
return (0);
/* Identify subtype by para[0] */
if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
cs->subtyp = card->para[0];
else {
printk(KERN_WARNING "HiSax: %s: Invalid subcontroller in configuration, default to 1\n",
CardType[card->typ]);
return (0);
}
if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) ||
(sub_vendor_id != PCI_VENDOR_ID_BERKOM)))
return (0);
if (cs->subtyp == SCT_1) {
if (!pci_present()) {
printk(KERN_ERR "bkm_a4t: no PCI bus present\n");
return (0);
}
while ((dev_a8 = pci_find_device(PCI_VENDOR_ID_PLX,
PCI_DEVICE_ID_PLX_9050, dev_a8))) {
pci_get_sub_vendor(dev_a8,sub_vendor_id);
pci_get_sub_system(dev_a8,sub_sys_id);
if ((sub_sys_id == PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) &&
(sub_vendor_id == PCI_VENDOR_ID_BERKOM)) {
if (pci_enable_device(dev_a8))
return(0);
pci_ioaddr1 = pci_resource_start_io(dev_a8, 1);
pci_irq = dev_a8->irq;
pci_bus = dev_a8->bus->number;
pci_device_fn = dev_a8->devfn;
found = 1;
break;
}
}
if (!found) {
printk(KERN_WARNING "HiSax: %s (%s): Card not found\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
#ifdef ATTEMPT_PCI_REMAPPING
/* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
pcibios_read_config_byte(pci_bus, pci_device_fn,
PCI_REVISION_ID, &pci_rev_id);
if ((pci_ioaddr1 & 0x80) && (pci_rev_id == 1)) {
printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
/* Restart PCI negotiation */
pcibios_write_config_dword(pci_bus, pci_device_fn,
PCI_BASE_ADDRESS_1, (u_int) - 1);
/* Move up by 0x80 byte */
pci_ioaddr1 += 0x80;
pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
pcibios_write_config_dword(pci_bus, pci_device_fn,
PCI_BASE_ADDRESS_1, pci_ioaddr1);
get_pcibase(dev_a8, 1) = pci_ioaddr1;
}
#endif /* End HACK */
}
if (!pci_irq) { /* IRQ range check ?? */
printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
/* Take over */
cs->irq = pci_irq;
cs->irq_flags |= SA_SHIRQ;
/* pci_ioaddr1 is unique to all subdevices */
/* pci_ioaddr2 is for the fourth subdevice only */
/* pci_ioaddr3 is for the third subdevice only */
/* pci_ioaddr4 is for the second subdevice only */
/* pci_ioaddr5 is for the first subdevice only */
cs->hw.ax.plx_adr = pci_ioaddr1;
/* Enter all ipac_base addresses */
switch(cs->subtyp) {
case 1:
cs->hw.ax.base = pci_ioaddr5 + 0x00;
if (sct_alloc_io(pci_ioaddr1, 128))
return(0);
if (sct_alloc_io(pci_ioaddr5, 64))
return(0);
/* disable all IPAC */
writereg(pci_ioaddr5, pci_ioaddr5 + 4,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
IPAC_MASK, 0xFF);
break;
case 2:
cs->hw.ax.base = pci_ioaddr4 + 0x08;
if (sct_alloc_io(pci_ioaddr4, 64))
return(0);
break;
case 3:
cs->hw.ax.base = pci_ioaddr3 + 0x10;
if (sct_alloc_io(pci_ioaddr3, 64))
return(0);
break;
case 4:
cs->hw.ax.base = pci_ioaddr2 + 0x20;
if (sct_alloc_io(pci_ioaddr2, 64))
return(0);
break;
}
/* For isac and hscx data path */
cs->hw.ax.data_adr = cs->hw.ax.base + 4;
printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp],
cs->hw.ax.plx_adr,
cs->hw.ax.base,
cs->hw.ax.data_adr,
cs->irq);
test_and_set_bit(HW_IPAC, &cs->HW_Flags);
cs->readisac = &ReadISAC;
cs->writeisac = &WriteISAC;
cs->readisacfifo = &ReadISACfifo;
cs->writeisacfifo = &WriteISACfifo;
cs->BC_Read_Reg = &ReadHSCX;
cs->BC_Write_Reg = &WriteHSCX;
cs->BC_Send_Data = &hscx_fill_fifo;
cs->cardmsg = &BKM_card_msg;
cs->irq_func = &bkm_interrupt_ipac;
printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp],
readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
return (1);
#else
printk(KERN_ERR "HiSax: bkm_a8 only supported on PCI Systems\n");
#endif /* CONFIG_PCI */
}
struct nic *sis900_probe(struct nic *nic, unsigned short *io_addrs, struct pci_device *pci)
{
int i;
int found=0;
int phy_addr;
u16 signature;
u8 revision;
int ret;
if (io_addrs == 0 || *io_addrs == 0)
return NULL;
ioaddr = *io_addrs & ~3;
vendor = pci->vendor;
dev_id = pci->dev_id;
pcibios_write_config_dword(pci->bus, pci->devfn, 0x40, 0x00000000);
adjust_pci_device(pci);
ret = 0;
pcibios_read_config_byte(pci->bus,pci->devfn, PCI_REVISION, &revision);
if (revision == SIS630E_900_REV || revision == SIS630EA1_900_REV)
ret = sis630e_get_mac_addr(pci, nic);
else if (revision == SIS630S_900_REV)
ret = sis630e_get_mac_addr(pci, nic);
else
ret = sis900_get_mac_addr(pci, nic);
if (ret == 0)
{
printf ("sis900_probe: Error MAC address not found\n");
return NULL;
}
printf("\nsis900_probe: MAC addr %! at ioaddr %#hX\n",
nic->node_addr, ioaddr);
printf("sis900_probe: Vendor:%#hX Device:%#hX\n", vendor, dev_id);
found = 0;
for (phy_addr = 0; phy_addr < 32; phy_addr++) {
u16 mii_status;
u16 phy_id0, phy_id1;
mii_status = sis900_mdio_read(phy_addr, MII_STATUS);
if (mii_status == 0xffff || mii_status == 0x0000)
continue;
phy_id0 = sis900_mdio_read(phy_addr, MII_PHY_ID0);
phy_id1 = sis900_mdio_read(phy_addr, MII_PHY_ID1);
for (i = 0; mii_chip_table[i].phy_id1; i++) {
if (phy_id0 == mii_chip_table[i].phy_id0) {
printf("sis900_probe: %s transceiver found at address %d.\n",
mii_chip_table[i].name, phy_addr);
mii.chip_info = &mii_chip_table[i];
mii.phy_addr = phy_addr;
mii.status = sis900_mdio_read(phy_addr, MII_STATUS);
mii.next = NULL;
found=1;
break;
}
}
}
if (found == 0) {
printf("sis900_probe: No MII transceivers found!\n");
return NULL;
}
cur_phy = mii.phy_addr;
printf("sis900_probe: Using %s as default\n", mii.chip_info->name);
sis900_init(nic);
nic->reset = sis900_init;
nic->poll = sis900_poll;
nic->transmit = sis900_transmit;
nic->disable = sis900_disable;
return nic;
}
