int
etherinit(void)
{
Ether *ctlr;
int ctlrno, i, mask, n, x;
fmtinstall('E', eipfmt);
if (getconf("*fakeintrs") != nil || getconf("*9loadfakeintrs") != nil)
startfakeintrs();
etherdetach = xetherdetach;
mask = 0;
for(ctlrno = 0; ctlrno < MaxEther; ctlrno++){
ctlr = ðer[ctlrno];
memset(ctlr, 0, sizeof(Ether));
if(iniread && isaconfig("ether", ctlrno, ctlr) == 0)
continue;
for(n = 0; ethercards[n].type; n++){
if(!iniread){
if(ethercards[n].noprobe)
continue;
memset(ctlr, 0, sizeof(Ether));
strcpy(ctlr->type, ethercards[n].type);
}
else if(cistrcmp(ethercards[n].type, ctlr->type))
continue;
ctlr->ctlrno = ctlrno;
x = splhi();
if((*ethercards[n].reset)(ctlr)){
splx(x);
if(iniread)
break;
else
continue;
}
ctlr->state = 1; /* card found */
mask |= 1<<ctlrno;
if(ctlr->irq == 2)
ctlr->irq = 9;
setvec(VectorPIC + ctlr->irq, ctlr->interrupt, ctlr);
print("ether#%d: %s: port 0x%luX irq %lud",
ctlr->ctlrno, ctlr->type, ctlr->port, ctlr->irq);
if(ctlr->mem)
print(" addr 0x%luX", ctlr->mem & ~KZERO);
if(ctlr->size)
print(" size 0x%luX", ctlr->size);
print(": %E\n", ctlr->ea);
if(ctlr->nrb == 0)
ctlr->nrb = Nrb;
ctlr->rb = ialloc(sizeof(RingBuf)*ctlr->nrb, 0);
if(ctlr->ntb == 0)
ctlr->ntb = Ntb;
ctlr->tb = ialloc(sizeof(RingBuf)*ctlr->ntb, 0);
ctlr->rh = 0;
ctlr->ri = 0;
for(i = 0; i < ctlr->nrb; i++)
ctlr->rb[i].owner = Interface;
ctlr->th = 0;
ctlr->ti = 0;
for(i = 0; i < ctlr->ntb; i++)
ctlr->tb[i].owner = Host;
splx(x);
break;
}
}
if (mask == 0) {
print("no ethernet interfaces recognised\n");
pcihinv(nil, Pcibcnet);
}
return mask;
}
static void
pcicfginit(void)
{
int sbno, bno, n;
Pcidev **list, *p;
if(pcicfgmode != -1)
return;
lock(&pcicfginitlock);
if(pcicfgmode != -1){
unlock(&pcicfginitlock);
return;
}
fmtinstall('T', tbdffmt);
/*
* Try to determine if PCI Mode1 configuration implemented.
* (Bits [30:24] of PciADDR must be 0, according to the spec.)
* Mode2 won't appear in 64-bit machines.
*/
n = inl(PciADDR);
if(!(n & 0x7F000000)){
outl(PciADDR, 0x80000000);
outb(PciADDR+3, 0);
if(inl(PciADDR) & 0x80000000)
pcicfgmode = 1;
}
outl(PciADDR, n);
if(pcicfgmode < 0){
unlock(&pcicfginitlock);
return;
}
list = &pciroot;
for(bno = 0; bno <= Maxbus; bno++) {
sbno = bno;
bno = pcilscan(bno, "0.0.0", list);
while(*list)
list = &(*list)->link;
if(sbno != 0)
continue;
/*
* If we have found a PCI-to-Cardbus bridge, make sure
* it has no valid mappings anymore.
*/
for(p = pciroot; p != nil; p = p->link){
if (p->ccrb == 6 && p->ccru == 7) {
/* reset the cardbus */
pcicfgw16(p, PciBCR, 0x40 | pcicfgr16(p, PciBCR));
delay(50);
}
}
}
pcireservemem();
unlock(&pcicfginitlock);
// Bring the virtio devices live.
virtiosetup();
//if(getconf("*pcihinv"))
pcihinv(nil);
}