void
mpshutdown(void)
{
/*
* To be done...
*/
if(!canlock(&mpshutdownlock)){
/*
* If this processor received the CTRL-ALT-DEL from
* the keyboard, acknowledge it. Send an INIT to self.
*/
#ifdef FIXTHIS
if(lapicisr(VectorKBD))
lapiceoi(VectorKBD);
#endif /* FIX THIS */
arch->introff();
idle();
}
if(active.rebooting)
return;
print("apshutdown: active = %#8.8ux\n", active.machs);
delay(1000);
splhi();
arch->resetothers();
pcireset();
i8042reset();
/*
* Often the BIOS hangs during restart if a conventional 8042
* warm-boot sequence is tried. The following is Intel specific and
* seems to perform a cold-boot, but at least it comes back.
* And sometimes there is no keyboard...
*
* The reset register (0xcf9) is usually in one of the bridge
* chips. The actual location and sequence could be extracted from
* ACPI but why bother, this is the end of the line anyway.
*/
print("no kbd; trying bios warm boot...");
*(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
outb(0xCF9, 0x02);
outb(0xCF9, 0x06);
print("can't reset\n");
for(;;)
idle();
}
void
mpshutdown(void)
{
/*
* To be done...
*/
if(!canlock(&mpshutdownlock)){
/*
* If this processor received the CTRL-ALT-DEL from
* the keyboard, acknowledge it. Send an INIT to self.
*/
#ifdef FIXTHIS
if(lapicisr(VectorKBD))
lapiceoi(VectorKBD);
#endif /* FIX THIS */
idle();
}
print("apshutdown: active = 0x%2.2uX\n", active.machs);
delay(1000);
splhi();
/*
* INIT all excluding self.
*/
lapicicrw(0, 0x000C0000|ApicINIT);
#ifdef notdef
/*
* Often the BIOS hangs during restart if a conventional 8042
* warm-boot sequence is tried. The following is Intel specific and
* seems to perform a cold-boot, but at least it comes back.
*/
*(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
outb(0xCF9, 0x02);
outb(0xCF9, 0x06);
#else
pcireset();
i8042reset();
#endif /* notdef */
}
/*
* at entry, l.s has set m for cpu0 and printed "Plan 9 from Be"
* but has not zeroed bss.
*/
void
main(void)
{
int cpu;
static ulong vfy = 0xcafebabe;
up = nil;
if (vfy != 0xcafebabe) {
serialputc('?');
serialputc('d');
panic("data segment misaligned");
}
memset(edata, 0, end - edata);
/*
* we can't lock until smpon has run, but we're supposed to wait
* until l1 & l2 are on. too bad. l1 is on, l2 will soon be.
*/
smpon();
iprint("ll Labs ");
cacheinit();
/*
* data segment is aligned, bss is zeroed, caches' characteristics
* are known. begin initialisation.
*/
mach0init();
l2pageinit();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
/* l2 looks for *l2off= in plan9.ini */
l2cache->on(); /* l2->on requires locks to work, thus smpon */
l2cache->info(&cachel[2]);
allcache->on();
cortexa9cachecfg();
trapinit(); /* so confinit can probe memory to size it */
confinit(); /* figures out amount of memory */
/* xinit prints (if it can), so finish up the banner here. */
delay(100);
navailcpus = getncpus();
iprint("(mp arm; %d cpus)\n\n", navailcpus);
delay(100);
for (cpu = 1; cpu < navailcpus; cpu++)
stopcpu(cpu);
xinit();
irqtooearly = 0; /* now that xinit and trapinit have run */
mainmem->flags |= POOL_ANTAGONISM /* | POOL_PARANOIA */ ;
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockinit) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
archreset(); /* cfg clock signals, print cache cfg */
clockinit(); /* start clocks */
timersinit();
delay(50); /* let uart catch up */
printinit();
kbdenable();
cpuidprint();
chkmissing();
procinit0();
initseg();
// dmainit();
links();
conf.monitor = 1;
// screeninit();
iprint("pcireset...");
pcireset(); /* this tends to hang after a reboot */
iprint("ok\n");
chandevreset(); /* most devices are discovered here */
// i8250console(); /* too early; see init0 */
pageinit(); /* prints "1020M memory: ⋯ */
swapinit();
userinit();
/*
* starting a cpu will eventually result in it calling schedinit,
* so everything necessary to run user processes should be set up
* before starting secondary cpus.
*/
launchinit();
/* SMP & FW are already on when we get here; u-boot set them? */
for (cpu = 1; cpu < navailcpus; cpu++)
if (startcpu(cpu) < 0)
panic("cpu%d didn't start", cpu);
l1diag();
schedinit();
panic("cpu%d: schedinit returned", m->machno);
}
