static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
DMAState *s = opaque;
uint32_t saddr;
saddr = (addr & DMA_MAXADDR) >> 2;
DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->dmaregs[saddr], val);
switch (saddr) {
case 0:
if (!(val & DMA_INTREN))
pic_set_irq_new(s->intctl, s->espirq, 0);
if (val & DMA_RESET) {
esp_reset(s->esp_opaque);
} else if (val & 0x40) {
val &= ~0x40;
} else if (val == 0)
val = 0x40;
val &= 0x0fffffff;
val |= DMA_VER;
break;
case 1:
s->dmaregs[0] |= DMA_LOADED;
break;
case 4:
if (!(val & DMA_INTREN))
pic_set_irq_new(s->intctl, s->leirq, 0);
if (val & DMA_RESET)
pcnet_h_reset(s->lance_opaque);
val &= 0x0fffffff;
val |= DMA_VER;
break;
default:
break;
}
s->dmaregs[saddr] = val;
}
static void parent_lance_reset(void *opaque, int irq, int level)
{
SysBusPCNetState *d = opaque;
if (level)
pcnet_h_reset(&d->state);
}
static void pci_reset(DeviceState *dev)
{
PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev.qdev, dev);
pcnet_h_reset(&d->state);
}
static void lance_reset(DeviceState *dev)
{
SysBusPCNetState *d = DO_UPCAST(SysBusPCNetState, busdev.qdev, dev);
pcnet_h_reset(&d->state);
}
static void lance_reset(DeviceState *dev)
{
SysBusPCNetState *d = SYSBUS_PCNET(dev);
pcnet_h_reset(&d->state);
}