/* Reset the adapter. */
void
ie_gsc_reset(struct ie_softc *sc, int what)
{
struct ie_gsc_softc *gsc = (struct ie_gsc_softc *) sc;
int i;
switch (what) {
case CHIP_PROBE:
bus_space_write_4(gsc->iot, gsc->ioh, IE_GSC_REG_RESET, 0);
break;
case CARD_RESET:
bus_space_write_4(gsc->iot, gsc->ioh, IE_GSC_REG_RESET, 0);
/*
* per [2] 4.6.2.1
* delay for 10 system clocks + 5 transmit clocks,
* NB: works for system clocks over 10MHz
*/
DELAY(1000);
/*
* after the hardware reset:
* inform i825[89]6 about new SCP address,
* which must be at least 16-byte aligned
*/
ie_gsc_port(sc, IE_PORT_ALT_SCP);
ie_gsc_attend(sc, what);
for (i = 9000; i-- && ie_gsc_read16(sc, IE_ISCP_BUSY(sc->iscp));
DELAY(100))
pdcache(0, (vaddr_t)sc->sc_maddr + sc->iscp, IE_ISCP_SZ);
#if I82596_DEBUG
if (i < 0) {
printf("timeout for PORT command (%x)%s\n",
ie_gsc_read16(sc, IE_ISCP_BUSY(sc->iscp)),
(gsc->flags & IEGSC_GECKO)? " on gecko":"");
return;
}
#endif
break;
}
}
void
mbus_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs)
{
struct pglist pglist;
paddr_t pa, epa;
TAILQ_INIT(&pglist);
for(; nsegs--; segs++)
for (pa = segs->ds_addr, epa = pa + segs->ds_len;
pa < epa; pa += PAGE_SIZE) {
struct vm_page *pg = PHYS_TO_VM_PAGE(pa);
if (!pg)
panic("mbus_dmamem_free: no page for pa");
TAILQ_INSERT_TAIL(&pglist, pg, pageq);
pdcache(HPPA_SID_KERNEL, pa, PAGE_SIZE);
pdtlb(HPPA_SID_KERNEL, pa);
pitlb(HPPA_SID_KERNEL, pa);
}
uvm_pglistfree(&pglist);
}