void cleanup_module(void)
{
i2c_bit_del_bus(&bit_hydra_ops);
if (hydra_base) {
pdregw(0); /* clear SCLK_OE and SDAT_OE */
iounmap((void *) hydra_base);
}
}
static int __devinit hydra_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
unsigned int base_addr;
base_addr = dev->resource[0].start;
hydra_base = (unsigned long) ioremap(base_addr, 0x100);
pdregw(0); /* clear SCLK_OE and SDAT_OE */
return i2c_bit_add_bus(&bit_hydra_ops);
}
static void bit_hydra_setsda(void *data, int state)
{
u32 val = pdregr();
if (state)
val &= ~HYDRA_SDAT_OE;
else {
val &= ~HYDRA_SDAT;
val |= HYDRA_SDAT_OE;
}
pdregw(val);
}
static void bit_hydra_setscl(void *data, int state)
{
u32 val = pdregr();
if (state)
val &= ~HYDRA_SCLK_OE;
else {
val &= ~HYDRA_SCLK;
val |= HYDRA_SCLK_OE;
}
pdregw(val);
pdregr(); /* flush posted write */
}
static
#else
extern
#endif
int __init i2c_hydra_init(void)
{
if (find_hydra() < 0) {
printk("Error while reading PCI configuration\n");
return -ENODEV;
}
pdregw(0); /* clear SCLK_OE and SDAT_OE */
if (i2c_bit_add_bus(&bit_hydra_ops) == 0) {
printk("Hydra i2c: Module succesfully loaded\n");
return 0;
} else {
iounmap((void *) hydra_base);
printk
("Hydra i2c: Algo-bit error, couldn't register bus\n");
return -ENODEV;
}
}
static void __devexit hydra_remove(struct pci_dev *dev)
{
pdregw(0); /* clear SCLK_OE and SDAT_OE */
i2c_bit_del_bus(&bit_hydra_ops);
iounmap((void *) hydra_base);
}
