Exemplo n.º 1
0
static void swPanelPowerSequence(int disp, int delay)
{
	unsigned int reg;

	/* disp should be 1 to open sequence */
	reg = peek32(PANEL_DISPLAY_CTRL);
	reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
	poke32(PANEL_DISPLAY_CTRL, reg);
	primary_wait_vertical_sync(delay);

	reg = peek32(PANEL_DISPLAY_CTRL);
	reg |= (disp ? PANEL_DISPLAY_CTRL_DATA : 0);
	poke32(PANEL_DISPLAY_CTRL, reg);
	primary_wait_vertical_sync(delay);

	reg = peek32(PANEL_DISPLAY_CTRL);
	reg |= (disp ? PANEL_DISPLAY_CTRL_VBIASEN : 0);
	poke32(PANEL_DISPLAY_CTRL, reg);
	primary_wait_vertical_sync(delay);

	reg = peek32(PANEL_DISPLAY_CTRL);
	reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
	poke32(PANEL_DISPLAY_CTRL, reg);
	primary_wait_vertical_sync(delay);
}
Exemplo n.º 2
0
unsigned int ddk750_get_vm_size(void)
{
	unsigned int reg;
	unsigned int data;

	/* sm750le only use 64 mb memory*/
	if (sm750_get_chip_type() == SM750LE)
		return SZ_64M;

	/* for 750,always use power mode0*/
	reg = peek32(MODE0_GATE);
	reg |= MODE0_GATE_GPIO;
	poke32(MODE0_GATE, reg);

	/* get frame buffer size from GPIO */
	reg = peek32(MISC_CTRL) & MISC_CTRL_LOCALMEM_SIZE_MASK;
	switch (reg) {
	case MISC_CTRL_LOCALMEM_SIZE_8M:
		data = SZ_8M;  break; /* 8  Mega byte */
	case MISC_CTRL_LOCALMEM_SIZE_16M:
		data = SZ_16M; break; /* 16 Mega byte */
	case MISC_CTRL_LOCALMEM_SIZE_32M:
		data = SZ_32M; break; /* 32 Mega byte */
	case MISC_CTRL_LOCALMEM_SIZE_64M:
		data = SZ_64M; break; /* 64 Mega byte */
	default:
		data = 0;
		break;
	}
	return data;
}
Exemplo n.º 3
0
int sm750_hw_i2c_init(unsigned char bus_speed_mode)
{
	unsigned int value;

	/* Enable GPIO 30 & 31 as IIC clock & data */
	value = peek32(GPIO_MUX);

	value |= (GPIO_MUX_30 | GPIO_MUX_31);
	poke32(GPIO_MUX, value);

	/*
	 * Enable Hardware I2C power.
	 * TODO: Check if we need to enable GPIO power?
	 */
	sm750_enable_i2c(1);

	/* Enable the I2C Controller and set the bus speed mode */
	value = peek32(I2C_CTRL) & ~(I2C_CTRL_MODE | I2C_CTRL_EN);
	if (bus_speed_mode)
		value |= I2C_CTRL_MODE;
	value |= I2C_CTRL_EN;
	poke32(I2C_CTRL, value);

	return 0;
}
Exemplo n.º 4
0
static void setDisplayControl(int ctrl, int disp_state)
{
	/* state != 0 means turn on both timing & plane en_bit */
	unsigned long reg, val, reserved;
	int cnt = 0;

	if (!ctrl) {
		reg = PANEL_DISPLAY_CTRL;
		reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK;
	} else {
		reg = CRT_DISPLAY_CTRL;
		reserved = CRT_DISPLAY_CTRL_RESERVED_MASK;
	}

	val = peek32(reg);
	if (disp_state) {
		/*
		 * Timing should be enabled first before enabling the
		 * plane because changing at the same time does not
		 * guarantee that the plane will also enabled or
		 * disabled.
		 */
		val |= DISPLAY_CTRL_TIMING;
		poke32(reg, val);

		val |= DISPLAY_CTRL_PLANE;

		/*
		 * Somehow the register value on the plane is not set
		 * until a few delay. Need to write and read it a
		 * couple times
		 */
		do {
			cnt++;
			poke32(reg, val);
		} while ((peek32(reg) & ~reserved) != (val & ~reserved));
		pr_debug("Set Plane enbit:after tried %d times\n", cnt);
	} else {
		/*
		 * When turning off, there is no rule on the
		 * programming sequence since whenever the clock is
		 * off, then it does not matter whether the plane is
		 * enabled or disabled.  Note: Modifying the plane bit
		 * will take effect on the next vertical sync. Need to
		 * find out if it is necessary to wait for 1 vsync
		 * before modifying the timing enable bit.
		 */
		val &= ~DISPLAY_CTRL_PLANE;
		poke32(reg, val);

		val &= ~DISPLAY_CTRL_TIMING;
		poke32(reg, val);
	}
}
Exemplo n.º 5
0
void ddk750_set_dpms(DPMS_t state)
{
	unsigned int value;

	if (sm750_get_chip_type() == SM750LE) {
		value = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK;
		value |= (state << CRT_DISPLAY_CTRL_DPMS_SHIFT);
		poke32(CRT_DISPLAY_CTRL, value);
	} else {
		value = peek32(SYSTEM_CTRL);
		value = (value & ~SYSTEM_CTRL_DPMS_MASK) | state;
		poke32(SYSTEM_CTRL, value);
	}
}
Exemplo n.º 6
0
/*
 *  This function reads data from the slave device and stores them
 *  in the given buffer
 *
 *  Parameters:
 *      addr            - i2c Slave device address
 *      length          - Total number of bytes to be read
 *      buf             - Pointer to a buffer to be filled with the data read
 *                     from the slave device. It has to be the same size as the
 *                     length to make sure that it can keep all the data read.
 *
 *  Return Value:
 *      Total number of actual bytes read from the slave device
 */
static unsigned int hw_i2c_read_data(unsigned char addr,
				     unsigned int length,
				     unsigned char *buf)
{
	unsigned char count, i;
	unsigned int total_bytes = 0;

	/* Set the Device Address */
	poke32(I2C_SLAVE_ADDRESS, addr | 0x01);

	/*
	 * Read data and save them to the buffer.
	 * Note:
	 *      Only 16 byte can be accessed per i2c start instruction.
	 */
	do {
		/*
		 * Reset I2C by writing 0 to I2C_RESET register to
		 * clear all the status.
		 */
		poke32(I2C_RESET, 0);

		/* Set the number of bytes to be read */
		if (length <= MAX_HWI2C_FIFO)
			count = length - 1;
		else
			count = MAX_HWI2C_FIFO - 1;
		poke32(I2C_BYTE_COUNT, count);

		/* Start the I2C */
		poke32(I2C_CTRL, peek32(I2C_CTRL) | I2C_CTRL_CTRL);

		/* Wait until transaction done. */
		if (hw_i2c_wait_tx_done() != 0)
			break;

		/* Save the data to the given buffer */
		for (i = 0; i <= count; i++)
			*buf++ = peek32(I2C_DATA0 + i);

		/* Subtract length by 16 */
		length -= (count + 1);

		/* Number of bytes read. */
		total_bytes += (count + 1);

	} while (length > 0);

	return total_bytes;
}
Exemplo n.º 7
0
void ostimer_init(void)
{
	/* Timer wraps when it hits comparison value */
	poke32(TCU_OSTCSR, OSTCSR_PRESCALE_16);

	/* Counter initial value. */
	poke32(TCU_OSTCNTH, 0);
	poke32(TCU_OSTCNTL, 0);

	/* Use EXTCLK as the clock source */
	poke32(TCU_OSTCSR, peek32(TCU_OSTCSR) | OSTCSR_EXT_EN);

	/* Comparison value -- once every MS. */
	poke32(TCU_OSTDR, OS_TIMER_HZ / 1000);

	/* Enable the timer*/
	poke32(TESR, TER_OSTEN);

	/* Register for interrupts */
	intc_register_handler_tcu0(ostimer_interrupt);

	/* Unmask timer IRQ, in TCU */
	poke32(TMCR, TMR_OSTMASK);

	/* Unmask timer IRQ, in interrupt controller */
	intc_irq_unmask_tcu0();
}
Exemplo n.º 8
0
void sm750_hw_i2c_close(void)
{
	unsigned int value;

	/* Disable I2C controller */
	value = peek32(I2C_CTRL) & ~I2C_CTRL_EN;
	poke32(I2C_CTRL, value);

	/* Disable I2C Power */
	sm750_enable_i2c(0);

	/* Set GPIO 30 & 31 back as GPIO pins */
	value = peek32(GPIO_MUX);
	value &= ~GPIO_MUX_30;
	value &= ~GPIO_MUX_31;
	poke32(GPIO_MUX, value);
}
Exemplo n.º 9
0
/*
 * This function initializes the i2c attributes and bus
 *
 * Parameters:
 *      clk_gpio      - The GPIO pin to be used as i2c SCL
 *      data_gpio     - The GPIO pin to be used as i2c SDA
 *
 * Return Value:
 *      -1   - Fail to initialize the i2c
 *       0   - Success
 */
long sm750_sw_i2c_init(unsigned char clk_gpio, unsigned char data_gpio)
{
	int i;

	/*
	 * Return 0 if the GPIO pins to be used is out of range. The
	 * range is only from [0..63]
	 */
	if ((clk_gpio > 31) || (data_gpio > 31))
		return -1;

	if (sm750_get_chip_type() == SM750LE)
		return sm750le_i2c_init(clk_gpio, data_gpio);

	/* Initialize the GPIO pin for the i2c Clock Register */
	sw_i2c_clk_gpio_mux_reg = GPIO_MUX;
	sw_i2c_clk_gpio_data_reg = GPIO_DATA;
	sw_i2c_clk_gpio_data_dir_reg = GPIO_DATA_DIRECTION;

	/* Initialize the Clock GPIO Offset */
	sw_i2c_clk_gpio = clk_gpio;

	/* Initialize the GPIO pin for the i2c Data Register */
	sw_i2c_data_gpio_mux_reg = GPIO_MUX;
	sw_i2c_data_gpio_data_reg = GPIO_DATA;
	sw_i2c_data_gpio_data_dir_reg = GPIO_DATA_DIRECTION;

	/* Initialize the Data GPIO Offset */
	sw_i2c_data_gpio = data_gpio;

	/* Enable the GPIO pins for the i2c Clock and Data (GPIO MUX) */
	poke32(sw_i2c_clk_gpio_mux_reg,
	       peek32(sw_i2c_clk_gpio_mux_reg) & ~(1 << sw_i2c_clk_gpio));
	poke32(sw_i2c_data_gpio_mux_reg,
	       peek32(sw_i2c_data_gpio_mux_reg) & ~(1 << sw_i2c_data_gpio));

	/* Enable GPIO power */
	sm750_enable_gpio(1);

	/* Clear the i2c lines. */
	for (i = 0; i < 9; i++)
		sw_i2c_stop();

	return 0;
}
Exemplo n.º 10
0
int main(int, char *[]){

    srandom(time(NULL)); //seed random()

    if ((fp = ::open("/dev/usrp_e0", O_RDWR)) < 0){
        std::cerr << "Open failed" << std::endl;
        return -1;
    }

    size_t num_pass = 0, num_fail = 0;
    for (size_t i = 0; i < num_test_iters; i++){
	if(i%1000000 == 0) {
	    std::cout << "num pass: "******"\tnum fail: " << num_fail << std::endl;
	}
        //make random values
        int random_test32 = ::random();
        int random_test16 = ::random() & 0xffff;
        int random_secs = ::random();

        //set a bunch of registers
        poke16(UE_REG_MISC_TEST, random_test16);
        poke32(UE_REG_SR_MISC_TEST32, random_test32);
        poke32(UE_REG_TIME64_TICKS, 0);
        poke32(UE_REG_TIME64_IMM, 1); //immediate
        poke32(UE_REG_TIME64_SECS, random_secs);

        //read a bunch of registers
        if (
            (peek16(UE_REG_MISC_TEST) == random_test16) and
            (peek32(UE_REG_RB_MISC_TEST32) == random_test32) and
            (peek32(UE_REG_RB_TIME_NOW_SECS) == random_secs) and
//            (peek32(UE_REG_RB_TIME_NOW_TICKS) < 1000000) and
        true) num_pass++;
        else  num_fail++;
    }

    std::cout << "num pass: "******"num fail: " << num_fail << std::endl;

    ::close(fp);
    return 0;
}
Exemplo n.º 11
0
/*
 *  This function read the data from the SDA GPIO pin
 *
 *  Return Value:
 *      The SDA data bit sent by the Slave
 */
static unsigned char sw_i2c_read_sda(void)
{
	unsigned long gpio_dir;
	unsigned long gpio_data;
	unsigned long dir_mask = 1 << sw_i2c_data_gpio;

	/* Make sure that the direction is input (High) */
	gpio_dir = peek32(sw_i2c_data_gpio_data_dir_reg);
	if ((gpio_dir & dir_mask) != ~dir_mask) {
		gpio_dir &= ~(1 << sw_i2c_data_gpio);
		poke32(sw_i2c_data_gpio_data_dir_reg, gpio_dir);
	}

	/* Now read the SDA line */
	gpio_data = peek32(sw_i2c_data_gpio_data_reg);
	if (gpio_data & (1 << sw_i2c_data_gpio))
		return 1;
	else
		return 0;
}
Exemplo n.º 12
0
void ddk750_setLogicalDispOut(enum disp_output output)
{
	unsigned int reg;

	if (output & PNL_2_USAGE) {
		/* set panel path controller select */
		reg = peek32(PANEL_DISPLAY_CTRL);
		reg &= ~PANEL_DISPLAY_CTRL_SELECT_MASK;
		reg |= (((output & PNL_2_MASK) >> PNL_2_OFFSET) <<
			PANEL_DISPLAY_CTRL_SELECT_SHIFT);
		poke32(PANEL_DISPLAY_CTRL, reg);
	}
Exemplo n.º 13
0
static int fixcrash( TSF32 FarPtr client )
{
    static unsigned char opcode;
    static unsigned short opcodew;
    static int zero = 0;

    peek32( client->eip, client->cs, &opcodew, 2 );
    opcode = (unsigned char)( opcodew & 0xFF );

    /* We zero the word on the stack because we will return to the
            POP instruction and try again.  We also zero the offending
            register, because if we take a fault while we're in the middle
            of ihandle, ihandle itself will pop the register and cause
            a recursive crash loop.
    */
    if( opcode == 0x07 ) {      /* POP ES */
        client->es = 0;
coverup:
        poke32( client->esp, client->ss, &zero, 2 );
        return( 1 );
    }
    if( opcode == 0x1F ) {      /* POP DS */
        client->ds = 0;
        goto coverup;
    }
    if( opcodew == 0xA10F ) {   /* POP FS */
        client->fs = 0;
        goto coverup;
    }
    if( opcodew == 0xA90F ) {   /* POP GS */
        client->gs = 0;
        goto coverup;
    }

    /* Attempt to fix up the Microsoft floating point emulator,
            which overstores FWAIT instructions with "mov ax,ax"
            using the instruction mov ds:[si],C089h and does lots of
            other sneaky tricks
    */
    if( fix_fpe_fault( opcodew, client ) ) {
        return( 1 );
    }
#if 0
    /* Attempt to fix up references to Phar Lap selector 0x34
    */
    int fixed = 0;
    if( client->es == 0x34 ) client->es = client->ds, fixed++;
    if( client->fs == 0x34 ) client->fs = client->ds, fixed++;
    if( client->gs == 0x34 ) client->gs = client->ds, fixed++;
    if( fixed ) return( 1 );
#endif
    return( 0 );
}
Exemplo n.º 14
0
/*
 * This function enable/disable the 2D engine.
 */
void sm750_enable_2d_engine(unsigned int enable)
{
	u32 gate;

	gate = peek32(CURRENT_GATE);
	if (enable)
		gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC);
	else
		gate &= ~(CURRENT_GATE_DE | CURRENT_GATE_CSC);

	sm750_set_current_gate(gate);
}
Exemplo n.º 15
0
/*
 * Return memory size of sm750 in bytes
 */
int hw_get_memsize(struct ufb_data * ufb)
{	
	uint32_t ulreg;	
	ENTER();

	ulreg = peek32(ufb,MODE0_GATE);
	ulreg = FIELD_SET(ulreg,MODE0_GATE,GPIO,ON);
	poke32(ufb,MODE0_GATE,ulreg);
	
	ulreg = ddk750_getFrameBufSize(ufb);
	LEAVE ((int)ulreg);
}
Exemplo n.º 16
0
static int fix_fpe_fault( unsigned short opcodew, TSF32 FarPtr client )
{
    static unsigned char imm8, val8;
    static unsigned short imm16;

    switch( opcodew ) {
    case 0x04C7 :           /* mov ds:[si], imm16 */
        peek32( client->eip + 2, client->cs, &imm16, 2 );
        poke32( client->esi, client->ds, &imm16, 2 );
        client->eip += 4;
        break;
    case 0x0429 :            /* sub ds:[si], ax */
        peek32( client->esi, client->ds, &imm16, 2 );
        imm16 -= (int)client->eax;
        poke32( client->esi, client->ds, &imm16, 2 );
        client->eip += 2;
        break;
    case 0x04C6 :       /*  mov ds:[si], imm8 */
        peek32( client->eip + 2, client->cs, &imm8, 1 );
        poke32( client->esi, client->ds, &imm8, 1 );
        client->eip += 3;
        break;
    case 0x0C80 :       /* or  byte ptr[si], C0 */
        peek32( client->esi, client->ds, &val8, 1 );
        peek32( client->eip + 2, client->cs, &imm8, 1 );
        val8 |= imm8;
        poke32( client->esi, client->ds, &val8, 1 );
        client->eip += 3;
        break;
    case 0x0489 :       /* mov ds:[si], ax */
        imm16 = (int)client->eax;
        poke32( client->esi, client->ds, &imm16, 2 );
        client->eip += 2;
        break;
    default :
        return( 0 );
        break;
    }
    return( 1 );
}
Exemplo n.º 17
0
void sm750_enable_dma(unsigned int enable)
{
	u32 gate;

	/* Enable DMA Gate */
	gate = peek32(CURRENT_GATE);
	if (enable)
		gate |= CURRENT_GATE_DMA;
	else
		gate &= ~CURRENT_GATE_DMA;

	sm750_set_current_gate(gate);
}
Exemplo n.º 18
0
/*
 * This function enable/disable the GPIO Engine
 */
void sm750_enable_gpio(unsigned int enable)
{
	u32 gate;

	/* Enable GPIO Gate */
	gate = peek32(CURRENT_GATE);
	if (enable)
		gate |= CURRENT_GATE_GPIO;
	else
		gate &= ~CURRENT_GATE_GPIO;

	sm750_set_current_gate(gate);
}
Exemplo n.º 19
0
/*
 * This function enable/disable the I2C Engine
 */
void sm750_enable_i2c(unsigned int enable)
{
	u32 gate;

	/* Enable I2C Gate */
	gate = peek32(CURRENT_GATE);
	if (enable)
		gate |= CURRENT_GATE_I2C;
	else
		gate &= ~CURRENT_GATE_I2C;

	sm750_set_current_gate(gate);
}
Exemplo n.º 20
0
static long hw_i2c_wait_tx_done(void)
{
	unsigned int timeout;

	/* Wait until the transfer is completed. */
	timeout = HWI2C_WAIT_TIMEOUT;
	while (!(peek32(I2C_STATUS) & I2C_STATUS_TX) && (timeout != 0))
		timeout--;

	if (timeout == 0)
		return -1;

	return 0;
}
Exemplo n.º 21
0
/*
 *  This function writes data to the i2c slave device registers.
 *
 *  Parameters:
 *      addr            - i2c Slave device address
 *      length          - Total number of bytes to be written to the device
 *      buf             - The buffer that contains the data to be written to the
 *                     i2c device.
 *
 *  Return Value:
 *      Total number of bytes those are actually written.
 */
static unsigned int hw_i2c_write_data(unsigned char addr,
				      unsigned int length,
				      unsigned char *buf)
{
	unsigned char count, i;
	unsigned int total_bytes = 0;

	/* Set the Device Address */
	poke32(I2C_SLAVE_ADDRESS, addr & ~0x01);

	/*
	 * Write data.
	 * Note:
	 *      Only 16 byte can be accessed per i2c start instruction.
	 */
	do {
		/*
		 * Reset I2C by writing 0 to I2C_RESET register to
		 * clear the previous status.
		 */
		poke32(I2C_RESET, 0);

		/* Set the number of bytes to be written */
		if (length < MAX_HWI2C_FIFO)
			count = length - 1;
		else
			count = MAX_HWI2C_FIFO - 1;
		poke32(I2C_BYTE_COUNT, count);

		/* Move the data to the I2C data register */
		for (i = 0; i <= count; i++)
			poke32(I2C_DATA0 + i, *buf++);

		/* Start the I2C */
		poke32(I2C_CTRL, peek32(I2C_CTRL) | I2C_CTRL_CTRL);

		/* Wait until the transfer is completed. */
		if (hw_i2c_wait_tx_done() != 0)
			break;

		/* Subtract length */
		length -= (count + 1);

		/* Total byte written */
		total_bytes += (count + 1);

	} while (length > 0);

	return total_bytes;
}
Exemplo n.º 22
0
/*
 *  This function set/reset the SDA GPIO pin
 *
 *  Parameters:
 *      value    - Bit value to set to the SCL or SDA (0 = low, 1 = high)
 *
 *  Notes:
 *      When setting SCL to high, just set the GPIO as input where the pull up
 *      resistor will pull the signal up. Do not use software to pull up the
 *      signal because the i2c will fail when other device try to drive the
 *      signal due to SM50x will drive the signal to always high.
 */
static void sw_i2c_sda(unsigned char value)
{
	unsigned long gpio_data;
	unsigned long gpio_dir;

	gpio_dir = peek32(sw_i2c_data_gpio_data_dir_reg);
	if (value) {    /* High */
		/*
		 * Set direction as input. This will automatically
		 * pull the signal up.
		 */
		gpio_dir &= ~(1 << sw_i2c_data_gpio);
		poke32(sw_i2c_data_gpio_data_dir_reg, gpio_dir);
	} else {        /* Low */
		/* Set the signal down */
		gpio_data = peek32(sw_i2c_data_gpio_data_reg);
		gpio_data &= ~(1 << sw_i2c_data_gpio);
		poke32(sw_i2c_data_gpio_data_reg, gpio_data);

		/* Set direction as output */
		gpio_dir |= (1 << sw_i2c_data_gpio);
		poke32(sw_i2c_data_gpio_data_dir_reg, gpio_dir);
	}
}
Exemplo n.º 23
0
static void primary_wait_vertical_sync(int delay)
{
	unsigned int status;

	/*
	 * Do not wait when the Primary PLL is off or display control is
	 * already off. This will prevent the software to wait forever.
	 */
	if (!(peek32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
	    !(peek32(PANEL_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING))
		return;

	while (delay-- > 0) {
		/* Wait for end of vsync. */
		do {
			status = peek32(SYSTEM_CTRL);
		} while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);

		/* Wait for start of vsync. */
		do {
			status = peek32(SYSTEM_CTRL);
		} while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
	}
}
Exemplo n.º 24
0
static unsigned int get_mxclk_freq(void)
{
	unsigned int pll_reg;
	unsigned int M, N, OD, POD;

	if (sm750_get_chip_type() == SM750LE)
		return MHz(130);

	pll_reg = peek32(MXCLK_PLL_CTRL);
	M = (pll_reg & PLL_CTRL_M_MASK) >> PLL_CTRL_M_SHIFT;
	N = (pll_reg & PLL_CTRL_N_MASK) >> PLL_CTRL_M_SHIFT;
	OD = (pll_reg & PLL_CTRL_OD_MASK) >> PLL_CTRL_OD_SHIFT;
	POD = (pll_reg & PLL_CTRL_POD_MASK) >> PLL_CTRL_POD_SHIFT;

	return DEFAULT_INPUT_CLOCK * M / N / (1 << OD) / (1 << POD);
}
Exemplo n.º 25
0
static void set_memory_clock(unsigned int frequency)
{
	unsigned int reg, divisor;

	/*
	 * Cheok_0509: For SM750LE, the memory clock is fixed.
	 * Nothing to set.
	 */
	if (sm750_get_chip_type() == SM750LE)
		return;

	if (frequency) {
		/*
		 * Set the frequency to the maximum frequency
		 * that the DDR Memory can take which is 336MHz.
		 */
		if (frequency > MHz(336))
			frequency = MHz(336);

		/* Calculate the divisor */
		divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency);

		/* Set the corresponding divisor in the register. */
		reg = peek32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK;
		switch (divisor) {
		default:
		case 1:
			reg |= CURRENT_GATE_M2XCLK_DIV_1;
			break;
		case 2:
			reg |= CURRENT_GATE_M2XCLK_DIV_2;
			break;
		case 3:
			reg |= CURRENT_GATE_M2XCLK_DIV_3;
			break;
		case 4:
			reg |= CURRENT_GATE_M2XCLK_DIV_4;
			break;
		}

		sm750_set_current_gate(reg);
	}
}
Exemplo n.º 26
0
/*
 * SM50x can operate in one of three modes: 0, 1 or Sleep.
 * On hardware reset, power mode 0 is default.
 */
void sm750_set_power_mode(unsigned int mode)
{
	unsigned int ctrl = 0;

	ctrl = peek32(POWER_MODE_CTRL) & ~POWER_MODE_CTRL_MODE_MASK;

	if (sm750_get_chip_type() == SM750LE)
		return;

	switch (mode) {
	case POWER_MODE_CTRL_MODE_MODE0:
		ctrl |= POWER_MODE_CTRL_MODE_MODE0;
		break;

	case POWER_MODE_CTRL_MODE_MODE1:
		ctrl |= POWER_MODE_CTRL_MODE_MODE1;
		break;

	case POWER_MODE_CTRL_MODE_SLEEP:
		ctrl |= POWER_MODE_CTRL_MODE_SLEEP;
		break;

	default:
		break;
	}

	/* Set up other fields in Power Control Register */
	if (mode == POWER_MODE_CTRL_MODE_SLEEP) {
		ctrl &= ~POWER_MODE_CTRL_OSC_INPUT;
#ifdef VALIDATION_CHIP
		ctrl &= ~POWER_MODE_CTRL_336CLK;
#endif
	} else {
		ctrl |= POWER_MODE_CTRL_OSC_INPUT;
#ifdef VALIDATION_CHIP
		ctrl |= POWER_MODE_CTRL_336CLK;
#endif
	}

	/* Program new power mode. */
	poke32(POWER_MODE_CTRL, ctrl);
}
Exemplo n.º 27
0
void D32DebugSetBreak( OFFSET32 off, SELECTOR sel, int translate, unsigned char far *to, unsigned char far *from )
{
    Fptr32  fp;
    char    temp[4];

    if( translate ) {
        fp.sel = sel;
        fp.off = off;
        D32Relocate( &fp );
        sel = fp.sel;
        off = fp.off;
    }
    peek32( off, sel, temp, 1 );

    /* Don't set a breakpoint if there's already one there, or we lose
            the previously saved byte.
    */
    if( *temp != *to ) {
        *from = *temp;
        poke32( off, sel, to, 1 );
    }
}
Exemplo n.º 28
0
static unsigned int get_power_mode(void)
{
	if (sm750_get_chip_type() == SM750LE)
		return 0;
	return peek32(POWER_MODE_CTRL) & POWER_MODE_CTRL_MODE_MASK;
}
Exemplo n.º 29
0
int ddk750_init_hw(struct initchip_param *pInitParam)
{
	unsigned int reg;

	if (pInitParam->powerMode != 0)
		pInitParam->powerMode = 0;
	sm750_set_power_mode(pInitParam->powerMode);

	/* Enable display power gate & LOCALMEM power gate*/
	reg = peek32(CURRENT_GATE);
	reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM);
	sm750_set_current_gate(reg);

	if (sm750_get_chip_type() != SM750LE) {
		/*	set panel pll and graphic mode via mmio_88 */
		reg = peek32(VGA_CONFIGURATION);
		reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE);
		poke32(VGA_CONFIGURATION, reg);
	} else {
#if defined(__i386__) || defined(__x86_64__)
		/* set graphic mode via IO method */
		outb_p(0x88, 0x3d4);
		outb_p(0x06, 0x3d5);
#endif
	}

	/* Set the Main Chip Clock */
	set_chip_clock(MHz((unsigned int)pInitParam->chipClock));

	/* Set up memory clock. */
	set_memory_clock(MHz(pInitParam->memClock));

	/* Set up master clock */
	set_master_clock(MHz(pInitParam->masterClock));

	/*
	 * Reset the memory controller.
	 * If the memory controller is not reset in SM750,
	 * the system might hang when sw accesses the memory.
	 * The memory should be resetted after changing the MXCLK.
	 */
	if (pInitParam->resetMemory == 1) {
		reg = peek32(MISC_CTRL);
		reg &= ~MISC_CTRL_LOCALMEM_RESET;
		poke32(MISC_CTRL, reg);

		reg |= MISC_CTRL_LOCALMEM_RESET;
		poke32(MISC_CTRL, reg);
	}

	if (pInitParam->setAllEngOff == 1) {
		sm750_enable_2d_engine(0);

		/* Disable Overlay, if a former application left it on */
		reg = peek32(VIDEO_DISPLAY_CTRL);
		reg &= ~DISPLAY_CTRL_PLANE;
		poke32(VIDEO_DISPLAY_CTRL, reg);

		/* Disable video alpha, if a former application left it on */
		reg = peek32(VIDEO_ALPHA_DISPLAY_CTRL);
		reg &= ~DISPLAY_CTRL_PLANE;
		poke32(VIDEO_ALPHA_DISPLAY_CTRL, reg);

		/* Disable alpha plane, if a former application left it on */
		reg = peek32(ALPHA_DISPLAY_CTRL);
		reg &= ~DISPLAY_CTRL_PLANE;
		poke32(ALPHA_DISPLAY_CTRL, reg);

		/* Disable DMA Channel, if a former application left it on */
		reg = peek32(DMA_ABORT_INTERRUPT);
		reg |= DMA_ABORT_INTERRUPT_ABORT_1;
		poke32(DMA_ABORT_INTERRUPT, reg);

		/* Disable DMA Power, if a former application left it on */
		sm750_enable_dma(0);
	}

	/* We can add more initialization as needed. */

	return 0;
}