static inline void user_cpufreq_perf_lock(int level, int val)
{
if (val == 1 && !is_perf_lock_active(&user_perf_lock[level]))
perf_lock(&user_perf_lock[level]);
if (val == 0 && is_perf_lock_active(&user_perf_lock[level]))
perf_unlock(&user_perf_lock[level]);
}
static int mipi_himax_lcd_off(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
mfd = platform_get_drvdata(pdev);
PR_DISP_DEBUG("%s\n", __func__);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
mutex_lock(&cmdlock);
#if defined CONFIG_FB_MSM_SELF_REFRESH
#ifdef CONFIG_PERFLOCK
if (!is_perf_lock_active(&himax_perf_lock))
perf_lock(&himax_perf_lock);
#endif
#endif
mipi_dsi_cmds_tx(&himax_tx_buf, himax_display_off_cmd1,
ARRAY_SIZE(himax_display_off_cmd1));
mipi_dsi_cmds_tx(&himax_tx_buf, himax_display_off_cmd2,
ARRAY_SIZE(himax_display_off_cmd2));
#if defined CONFIG_FB_MSM_SELF_REFRESH
#ifdef CONFIG_PERFLOCK
if (is_perf_lock_active(&himax_perf_lock))
perf_unlock(&himax_perf_lock);
#endif
#endif
mutex_unlock(&cmdlock);
return 0;
}
static ssize_t
cpufreq_ceiling_store(struct kobject *kobj, struct kobj_attribute *attr,
const char *buf, size_t n)
{
int val, ret = -EINVAL;
if (sscanf(buf, "%d", &val) > 0) {
if (val == 11 && !is_perf_lock_active(&user_cpu_ceiling_lock)) {
perf_lock(&user_cpu_ceiling_lock);
ret = n;
} else if (val == 10 && is_perf_lock_active(&user_cpu_ceiling_lock)) {
perf_unlock(&user_cpu_ceiling_lock);
ret = n;
} else {
switch (val){
ceiling_level_wrapper(0, 1, PERF_LOCK_LOWEST);
ceiling_level_wrapper(2, 3, PERF_LOCK_LOW);
ceiling_level_wrapper(4, 5, PERF_LOCK_MEDIUM);
ceiling_level_wrapper(6, 7, PERF_LOCK_HIGH);
ceiling_level_wrapper(8, 9, PERF_LOCK_HIGHEST);
default:
break;
}
ret = n;
}
}
return ret;
}
static void usbnet_lock_perf(void)
{
pr_info("[USBNET] %s\n", __func__);
#ifdef CONFIG_PERFLOCK
if (!is_perf_lock_active(&usbnet_perf_lock))
perf_lock(&usbnet_perf_lock);
#endif
pm_qos_update_request(&usbnet_req_freq, (s32)PM_QOS_USBNET_CPU_FREQ_MIN_VALUE);
pm_qos_update_request(&usbnet_req_cpus, (s32)PM_QOS_USBNET_MIN_ONLINE_CPUS);
is_usbnet_perf_locked = 1;
}
static int perflock_open(struct inode *inode, struct file *file)
{
mutex_lock(&lock);
if (num == 0) {
perf_lock(&media_perf_lock);
printk(KERN_DEBUG "[perflock] Perflock enabled.\n");
}
num++;
printk(KERN_DEBUG "[perflock] Perflock node is opened by [%s]/[PID=%d],numbers of opened nodes = [%d].\n",
current->comm, current->pid, num);
mutex_unlock(&lock);
return 0;
}
void shextdev_SetFlipInformation(shextdet_form_position_result_t state)
{
#ifdef FLIP_USE
#if defined(CONFIG_SENSORS_AMI602) || defined(CONFIG_SENSORS_AMI603)
switch(state)
{
case SHEXTDET_FORM_POSITION_OPEN:
AMI602_SetFlipInformation(MS_POSITION_OPEN);
break;
case SHEXTDET_FORM_POSITION_CLOSE:
AMI602_SetFlipInformation(MS_POSITION_CLOSE);
break;
case SHEXTDET_FORM_POSITION_SWIVEL:
AMI602_SetFlipInformation(MS_POSITION_SWIVEL);
break;
}
#endif /* CONFIG_SENSORS_AMI602 */
#ifdef CONFIG_SH_YAS530
switch(state)
{
case SHEXTDET_FORM_POSITION_OPEN:
YAS530_SetShape(YAS_POSITION_OPEN);
break;
case SHEXTDET_FORM_POSITION_CLOSE:
YAS530_SetShape(YAS_POSITION_CLOSE);
break;
}
#endif /* CONFIG_SH_YAS530 */
#if defined( CONFIG_SHTPS_SY3000_TM1918_001 ) | defined( CONFIG_SHTPS_SY3000_TM1963_001 ) | defined( CONFIG_SHTPS_TMA3XX_TMA340_005 )
switch(state)
{
case SHEXTDET_FORM_POSITION_OPEN:
shtps_setFlipInformation(TPS_POSITION_OPEN);
break;
case SHEXTDET_FORM_POSITION_CLOSE:
shtps_setFlipInformation(TPS_POSITION_CLOSE);
break;
}
#endif /* #if defined( CONFIG_SHTPS_SY3000_TM1918_001 ) | defined( CONFIG_SHTPS_SY3000_TM1963_001 ) | defined( CONFIG_SHTPS_TMA3XX_TMA340_005 ) */
#ifdef CONFIG_PERF_LOCK_ENABLE
perf_lock(&flip_perf_lock);
perf_unlock(&flip_perf_lock);
#endif /* CONFIG_PERF_LOCK_ENABLE */
#endif /* FLIP_USE */
}
static ssize_t
perflock_store(struct kobject *kobj, struct kobj_attribute *attr,
const char *buf, size_t n)
{
int val;
if (sscanf(buf, "%d", &val) > 0) {
if (val == 1 && !is_perf_lock_active(&user_perf_lock))
perf_lock(&user_perf_lock);
if (val == 0 && is_perf_lock_active(&user_perf_lock))
perf_unlock(&user_perf_lock);
return n;
}
return -EINVAL;
}
static void himax_self_refresh_switch(int on)
{
int vsync_timeout;
mutex_lock(&cmdlock);
wake_lock(&himax_idle_wake_lock);
#ifdef CONFIG_PERFLOCK
if (!is_perf_lock_active(&himax_perf_lock))
perf_lock(&himax_perf_lock);
#endif
if (on) {
mipi_set_tx_power_mode(0);
mipi_dsi_cmds_tx(&himax_tx_buf, video_to_cmd,
ARRAY_SIZE(video_to_cmd));
mipi_set_tx_power_mode(1);
disable_video_mode_clk();
} else {
mipi_set_tx_power_mode(0);
enable_irq(vsync_irq);
mipi_dsi_cmds_tx(&himax_tx_buf, cmd_to_video,
ARRAY_SIZE(cmd_to_video));
wait_vsync = 1;
udelay(300);
vsync_timeout = wait_event_timeout(himax_vsync_wait, himax_vsync_gpio ||
gpio_get_value(28), HZ/2);
if (vsync_timeout == 0)
PR_DISP_DEBUG("Lost vsync!\n");
disable_irq(vsync_irq);
wait_vsync = 0;
himax_vsync_gpio = 0;
udelay(300);
mipi_dsi_cmds_tx(&himax_tx_buf, vsync_hsync_cmds,
ARRAY_SIZE(vsync_hsync_cmds));
enable_video_mode_clk();
if (vsync_timeout == 0)
mipi_himax_panel_recover();
}
#ifdef CONFIG_PERFLOCK
if (is_perf_lock_active(&himax_perf_lock))
perf_unlock(&himax_perf_lock);
#endif
wake_unlock(&himax_idle_wake_lock);
PR_DISP_DEBUG("[SR] %d\n", on);
mutex_unlock(&cmdlock);
}
static inline void user_perflock(int level, int val)
{
mutex_lock(&user_lock_mutex);
if (val == 1) {
if (!is_perf_locked())
pm_qos_update_request(&user_perf_lock_qos, SHSYS_PM_QOS_USER_PERFLOCK_LATENCY);
if (!is_perf_lock_active(&user_perf_lock[level]))
perf_lock(&user_perf_lock[level]);
user_perf_lock_num[level]++;
}
if (val == 0) {
if(user_perf_lock_num[level] > 0)
user_perf_lock_num[level]--;
if (user_perf_lock_num[level] == 0 && is_perf_lock_active(&user_perf_lock[level]))
perf_unlock(&user_perf_lock[level]);
if (!is_perf_locked())
pm_qos_update_request(&user_perf_lock_qos, PM_QOS_DEFAULT_VALUE);
}
mutex_unlock(&user_lock_mutex);
}
static void mipi_himax_cmi_display_on(struct msm_fb_data_type *mfd)
{
PR_DISP_DEBUG("%s+\n", __func__);
mutex_lock(&cmdlock);
#if defined CONFIG_FB_MSM_SELF_REFRESH
#ifdef CONFIG_PERFLOCK
if (!is_perf_lock_active(&himax_perf_lock))
perf_lock(&himax_perf_lock);
#endif
#endif
mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_display_on_cmds,
ARRAY_SIZE(himax_CMI_display_on_cmds));
#if defined CONFIG_FB_MSM_SELF_REFRESH
#ifdef CONFIG_PERFLOCK
if (is_perf_lock_active(&himax_perf_lock))
perf_unlock(&himax_perf_lock);
#endif
#endif
mutex_unlock(&cmdlock);
}
void shextdev_SetFlipInformation(shextdet_form_position_result_t state)
{
#ifdef FLIP_USE
#ifdef CONFIG_SENSORS_AMI602
switch(state)
{
case SHEXTDET_FORM_POSITION_OPEN:
AMI602_SetFlipInformation(MS_POSITION_OPEN);
break;
case SHEXTDET_FORM_POSITION_CLOSE:
AMI602_SetFlipInformation(MS_POSITION_CLOSE);
break;
case SHEXTDET_FORM_POSITION_SWIVEL:
AMI602_SetFlipInformation(MS_POSITION_SWIVEL);
break;
}
#endif /* CONFIG_SENSORS_AMI602 */
#ifdef CONFIG_SH_YAS530
switch(state)
{
case SHEXTDET_FORM_POSITION_OPEN:
YAS530_SetShape(YAS_POSITION_OPEN);
break;
case SHEXTDET_FORM_POSITION_CLOSE:
YAS530_SetShape(YAS_POSITION_CLOSE);
break;
}
#endif /* CONFIG_SH_YAS530 */
#ifdef CONFIG_PERF_LOCK_ENABLE
perf_lock(&flip_perf_lock);
perf_unlock(&flip_perf_lock);
#endif /* CONFIG_PERF_LOCK_ENABLE */
#endif /* FLIP_USE */
}
int32_t imx081_sensor_power_up(struct msm_sensor_ctrl_t *s_ctrl)
{
int32_t rc = 0;
CDBG("%s\n", __func__);
CDBG("%s MSM_TLMM_BASE + 0x2024 = 0x%0x\n", __func__, (unsigned int)MSM_TLMM_BASE + 0x2024);
CDBG("%s __raw_readl = 0x%0x\n", __func__, __raw_readl((MSM_TLMM_BASE + 0x2024)));
__raw_writel(__raw_readl((MSM_TLMM_BASE + 0x2024)) | 0x01, (MSM_TLMM_BASE + 0x2024));
s_ctrl->clk_info = imx081_clk_info;
s_ctrl->clk_info_size = ARRAY_SIZE(imx081_clk_info);
rc = msm_sensor_power_up(s_ctrl);
if (rc < 0) {
pr_err("%s: msm_sensor_power_up failed\n",
__func__);
return 0;
}
perf_lock(&imx081_perf_lock);
return rc;
}
/* -----------------------------------------------------------------------------
// Common Routine Implementation
// -----------------------------------------------------------------------------
*/
static int mipi_himax_lcd_on(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
struct mipi_panel_info *mipi;
static int turn_on_logo = 1;
mfd = platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
mipi = &mfd->panel_info.mipi;
mutex_lock(&cmdlock);
#if defined CONFIG_FB_MSM_SELF_REFRESH
#ifdef CONFIG_PERFLOCK
if (!is_perf_lock_active(&himax_perf_lock))
perf_lock(&himax_perf_lock);
#endif
#endif
if (mipi->mode == DSI_VIDEO_MODE) {
PR_DISP_DEBUG("DSI_VIDEO_MODE.%s", __func__);
if (panel_type == PANEL_ID_VIG_CHIMEI_HX) {
PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_CHIMEI_HX\n");
mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_video_on_cmds,
ARRAY_SIZE(himax_CMI_video_on_cmds));
} else if (panel_type == PANEL_ID_VIG_CHIMEI_HX_C25) {
PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_CHIMEI_HX_C25\n");
mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_video_on_c25_cmds,
ARRAY_SIZE(himax_CMI_video_on_c25_cmds));
} else if (panel_type == PANEL_ID_VIG_CHIMEI_HX_C3) {
PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_CHIMEI_HX_C3\n");
mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_video_on_c3_cmds,
ARRAY_SIZE(himax_CMI_video_on_c3_cmds));
} else if (panel_type == PANEL_ID_VIG_SHARP_HX_C3) {
PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_SHARP_HX_C3\n");
mipi_dsi_cmds_tx(&himax_tx_buf, himax_video_on_c3_cmds,
ARRAY_SIZE(himax_video_on_c3_cmds));
} else if (panel_type == PANEL_ID_VIG_SHARP_HX_C25) {
PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_SHARP_HX_C25\n");
mipi_dsi_cmds_tx(&himax_tx_buf, himax_video_on_c2_cmds,
ARRAY_SIZE(himax_video_on_c2_cmds));
} else if (panel_type == PANEL_ID_VIG_SHARP_HX_C2) {
PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_SHARP_HX_C2\n");
mipi_dsi_cmds_tx(&himax_tx_buf, himax_video_on_c2_cmds,
ARRAY_SIZE(himax_video_on_c2_cmds));
} else {
PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_SHARP_HX\n");
mipi_dsi_cmds_tx(&himax_tx_buf, himax_video_on_cmds,
ARRAY_SIZE(himax_video_on_cmds));
}
if (turn_on_logo && board_mfg_mode() == 0) {
mipi_dsi_cmds_tx(&himax_tx_buf, himax_show_logo_cmds,
ARRAY_SIZE(himax_show_logo_cmds));
turn_on_logo = 0;
}
} else {
PR_DISP_DEBUG("DSI_CMD_MODE.%s", __func__);
if (panel_type == PANEL_ID_VIG_CHIMEI_HX) {
mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_cmd_on_cmds,
ARRAY_SIZE(himax_CMI_cmd_on_cmds));
} else {
mipi_dsi_cmds_tx(&himax_tx_buf, himax_cmd_on_cmds,
ARRAY_SIZE(himax_cmd_on_cmds));
}
mipi_dsi_cmd_bta_sw_trigger();
mipi_himax_manufacture_id();
}
#if defined CONFIG_FB_MSM_SELF_REFRESH
#ifdef CONFIG_PERFLOCK
if (is_perf_lock_active(&himax_perf_lock))
perf_unlock(&himax_perf_lock);
#endif
#endif
mutex_unlock(&cmdlock);
return 0;
}