int board_init(void) { gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; #ifdef CONFIG_ETH_DESIGNWARE const char *phy_mode; int node; node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,stm32-dwmac"); if (node < 0) return -1; phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); switch (phy_get_interface_by_name(phy_mode)) { case PHY_INTERFACE_MODE_RMII: STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; break; case PHY_INTERFACE_MODE_MII: STM32_SYSCFG->pmc &= ~SYSCFG_PMC_MII_RMII_SEL; break; default: printf("PHY interface %s not supported !\n", phy_mode); } #endif #if defined(CONFIG_CMD_BMP) bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle, BMP_ALIGN_CENTER, BMP_ALIGN_CENTER); #endif /* CONFIG_CMD_BMP */ return 0; }
static int zynq_gem_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct zynq_gem_priv *priv = dev_get_priv(dev); int offset = 0; const char *phy_mode; pdata->iobase = (phys_addr_t)dev_get_addr(dev); priv->iobase = (struct zynq_gem_regs *)pdata->iobase; /* Hardcode for now */ priv->emio = 0; priv->phyaddr = -1; offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phy-handle"); if (offset > 0) priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } priv->interface = pdata->phy_interface; priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio"); printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, priv->phyaddr, phy_string_for_interface(priv->interface)); return 0; }
static int ftgmac100_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct ftgmac100_data *priv = dev_get_priv(dev); const char *phy_mode; pdata->iobase = devfdt_get_addr(dev); pdata->phy_interface = -1; phy_mode = dev_read_string(dev, "phy-mode"); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode); return -EINVAL; } pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) { priv->rxdes0_edorr_mask = BIT(30); priv->txdes0_edotr_mask = BIT(30); } else { priv->rxdes0_edorr_mask = BIT(15); priv->txdes0_edotr_mask = BIT(15); } return clk_get_bulk(dev, &priv->clks); }
static int fecmxc_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct fec_priv *priv = dev_get_priv(dev); const char *phy_mode; pdata->iobase = (phys_addr_t)dev_get_addr(dev); priv->eth = (struct ethernet_regs *)pdata->iobase; pdata->phy_interface = -1; phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } /* TODO * Need to get the reset-gpio and related properties from DT * and implemet the enet reset code on .probe call */ return 0; }
static int axi_emac_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct axidma_priv *priv = dev_get_priv(dev); int node = dev_of_offset(dev); int offset = 0; const char *phy_mode; pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); priv->iobase = (struct axi_regs *)pdata->iobase; offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "axistream-connected"); if (offset <= 0) { printf("%s: axistream is not found\n", __func__); return -EINVAL; } priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob, offset, "reg"); if (!priv->dmatx) { printf("%s: axi_dma register space not found\n", __func__); return -EINVAL; } /* RX channel offset is 0x30 */ priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30); priv->phyaddr = -1; offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); if (offset > 0) priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } priv->interface = pdata->phy_interface; priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, "xlnx,eth-hasnobuf"); printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, priv->phyaddr, phy_string_for_interface(priv->interface)); return 0; }
static int pic32_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct pic32eth_dev *priv = dev_get_priv(dev); const char *phy_mode; void __iomem *iobase; fdt_addr_t addr; fdt_size_t size; int offset = 0; int phy_addr = -1; addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg", &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; iobase = ioremap(addr, size); pdata->iobase = (phys_addr_t)addr; /* get phy mode */ pdata->phy_interface = -1; phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } /* get phy addr */ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy-handle"); if (offset > 0) phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); /* phy reset gpio */ gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0, &priv->rst_gpio, GPIOD_IS_OUT); priv->phyif = pdata->phy_interface; priv->phy_addr = phy_addr; priv->ectl_regs = iobase; priv->emac_regs = iobase + PIC32_EMAC1CFG1; pic32_mii_init(priv); return pic32_phy_init(priv, dev); }
static int altera_tse_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); const char *phy_mode; pdata->phy_interface = -1; phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } return 0; }
static int macb_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct macb_device *macb = dev_get_priv(dev); const char *phy_mode; __maybe_unused int ret; phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL); if (phy_mode) macb->phy_interface = phy_get_interface_by_name(phy_mode); if (macb->phy_interface == -1) { debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } macb->regs = (void *)pdata->iobase; #ifdef CONFIG_CLK ret = macb_enable_clk(dev); if (ret) return ret; #endif _macb_eth_initialize(macb); #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) macb->bus = mdio_alloc(); if (!macb->bus) return -ENOMEM; strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN); macb->bus->read = macb_miiphy_read; macb->bus->write = macb_miiphy_write; ret = mdio_register(macb->bus); if (ret < 0) return ret; macb->bus = miiphy_get_dev_by_name(dev->name); #endif return 0; }
static int zynq_gem_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct zynq_gem_priv *priv = dev_get_priv(dev); struct ofnode_phandle_args phandle_args; const char *phy_mode; pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->iobase = (struct zynq_gem_regs *)pdata->iobase; /* Hardcode for now */ priv->phyaddr = -1; if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args)) { debug("phy-handle does exist %s\n", dev->name); priv->phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1); priv->phy_of_node = phandle_args.node; priv->max_speed = ofnode_read_u32_default(phandle_args.node, "max-speed", SPEED_1000); } phy_mode = dev_read_prop(dev, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } priv->interface = pdata->phy_interface; priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, priv->phyaddr, phy_string_for_interface(priv->interface)); return 0; }
static int zynq_gem_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct zynq_gem_priv *priv = dev_get_priv(dev); int node = dev_of_offset(dev); const char *phy_mode; pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); priv->iobase = (struct zynq_gem_regs *)pdata->iobase; /* Hardcode for now */ priv->phyaddr = -1; priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); if (priv->phy_of_handle > 0) priv->phyaddr = fdtdec_get_int(gd->fdt_blob, priv->phy_of_handle, "reg", -1); phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } priv->interface = pdata->phy_interface; priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle, "max-speed", SPEED_1000); priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node, "is-internal-pcspma"); printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, priv->phyaddr, phy_string_for_interface(priv->interface)); return 0; }