void pic_unmask_all(void)
{
int i;
for (i = 0 + PIC1_OFFSET; i < 16 + PIC1_OFFSET; i++) {
pic_unmask_irq(i);
}
}
int kmain(void* UNUSED(mbd), unsigned int UNUSED(magic))
{
cpu_init(); //set up GDT
idt_install(); //set up IDT
interrupts_init(); //set up callback table
pic_init(); //set up PIC
print_clear();
print_string_static("Hello... I'm a C Kernel!1!!\nAnd I have a PIC and PIT intialized.\n");
interrupts_enable();
interrupts_registerHandler(IRQ_TIMER, timerHandler);
pit_init(50);
pic_unmask_irq(IRQ_TIMER);
for(;;);
return 0;
}
static void __init intcp_init_irq(void)
{
unsigned int i;
/*
* Disable all interrupt sources
*/
pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
if (i == 11)
i = 22;
if (i == IRQ_CP_CPPLDINT)
i++;
if (i == 29)
break;
set_irq_chip(i, &pic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
set_irq_chip(i, &cic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID);
}
sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
set_irq_chip(i, &sic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
pic_unmask_irq(IRQ_CP_CPPLDINT);
}
