void enet_mac_init_pins()
{
printf("enet_mac_init_pins()\r\n");
pin_set_alternate_function(GPIOA, PORTA_ETH_REFCLK, AF_ENET);
pin_set_alternate_function(GPIOA, PORTA_ETH_MDIO , AF_ENET);
pin_set_alternate_function(GPIOC, PORTC_ETH_MDC , AF_ENET);
pin_set_alternate_function(GPIOB, PORTB_ETH_TXEN , AF_ENET);
pin_set_alternate_function(GPIOB, PORTB_ETH_TXD0 , AF_ENET);
pin_set_alternate_function(GPIOB, PORTB_ETH_TXD1 , AF_ENET);
pin_set_alternate_function(GPIOA, PORTA_ETH_CRSDV , AF_ENET);
pin_set_alternate_function(GPIOC, PORTC_ETH_RXD0 , AF_ENET);
pin_set_alternate_function(GPIOC, PORTC_ETH_RXD1 , AF_ENET);
pin_set_output_speed(GPIOB, PORTB_ETH_TXEN, 3); // max beef
pin_set_output_speed(GPIOB, PORTB_ETH_TXD0, 3); // max beef
pin_set_output_speed(GPIOB, PORTB_ETH_TXD1, 3); // max beef
pin_set_output(GPIOE, PORTE_PHY_RESET, 1);
delay_ms(100);
pin_set_output_state(GPIOE, PORTE_PHY_RESET, 0);
delay_ms(100);
pin_set_output_state(GPIOE, PORTE_PHY_RESET, 1);
delay_ms(100);
}
void imu_init(void)
{
printf("imu init\r\n");
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
pin_set_output(GPIOE, PORTE_CS, 1);
pin_set_alternate_function(GPIOA, PORTA_SCLK, 5);
pin_set_alternate_function(GPIOA, PORTA_MISO, 5);
pin_set_alternate_function(GPIOB, PORTB_MOSI, 5);
pin_set_output_speed(GPIOA, PORTA_SCLK, 3);
pin_set_output_speed(GPIOB, PORTB_MOSI, 3);
pin_set_output_speed(GPIOE, PORTE_CS , 3);
SPI1->CR1 = SPI_CR1_SSM | // software slave select management
SPI_CR1_SSI | // assert software select state
SPI_CR1_CPHA | // clock phase: cpha = 1, cpol = 1
SPI_CR1_CPOL | // ditto
SPI_CR1_MSTR | // master mode
SPI_CR1_BR_0 | // baud rate sel. need to calculate.
SPI_CR1_BR_1 | // ditto
SPI_CR1_SPE ; // enable SPI
delay_us(100);
accel_write_reg(0x20, 0x87); // set max beef (1600 Hz)
delay_us(100); // wake up plz
#ifdef PRINT_REGISTER_TABLE
uint8_t info1 = accel_read_reg(0x0d);
printf("info1 = 0x%02x\r\n", (unsigned)info1);
#endif
float test_accel[3] = {0};
for (int i = 0; i < 10; i++)
{
delay_ms(10);
imu_poll_accels(test_accel);
}
}
void usb_fs_init_pins(void){
pin_set_alternate_function(GPIOA, PORTA_USB_FS_DP, AF_USB_FS);
pin_set_alternate_function(GPIOA, PORTA_USB_FS_DM, AF_USB_FS);
pin_set_alternate_function(GPIOA, PORTA_USB_FS_ID, AF_USB_FS);
// Output type ? Push Pull ok?
// pin_set_output_type(GPIOD, PORTD_USB_FS_OVERCURRENT, PIN_OUTPUT_TYPE_OPEN_DRAIN);
// pin_set_output_type(GPIOC, PORTC_USB_FS_PWR_SWITCH_ON, PIN_OUTPUT_TYPE_OPEN_DRAIN);
// pin_set_output_type(GPIOA, PORTA_USB_FS_VBUS, PIN_OUTPUT_TYPE_OPEN_DRAIN);
pin_set_output_speed(GPIOA, PORTA_USB_FS_DM, 3);
pin_set_output_speed(GPIOA, PORTA_USB_FS_DP, 3);
}
void enc_init()
{
printf("enc_init()\r\n");
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
/*
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
pin_set_alternate_function(GPIOA, PORTA_ENC_A, 1); // TIM1 = AF1
//pin_set_alternate_function(GPIOA, PORTA_ENC_B, 1); // TIM1 = AF1
TIM1->PSC = 9; // divide inbound clock by 10
TIM1->CCMR1 |= TIM_CCMR1_CC1S_0 | // select capture mode on TI1
(3 << 4); // set filter=3, meaning, N=8
TIM1->CCER = TIM_CCER_CC1P; // falling edge capture
TIM1->CCER |= TIM_CCER_CC1E; // enable capture
TIM1->SMCR |= (5 << 4) | // filtered timer input 1 as sync trigger
4; // reset mode: trigger input resets counter
TIM1->CR1 |= TIM_CR1_CEN; // turn on counter
*/
pin_set_output(GPIOA, PORTA_ENC_CS, 1);
pin_set_alternate_function(GPIOA, PORTA_ENC_SCLK, 5);
pin_set_alternate_function(GPIOA, PORTA_ENC_MISO, 5);
pin_set_alternate_function(GPIOA, PORTA_ENC_MOSI, 5);
pin_set_output_speed(GPIOA, PORTA_ENC_CS , 3); // max beef
pin_set_output_speed(GPIOA, PORTA_ENC_SCLK, 3); // max beef
pin_set_output_speed(GPIOA, PORTA_ENC_MISO, 3); // max beef
pin_set_output_speed(GPIOA, PORTA_ENC_MOSI, 3); // max beef
SPI1->CR1 = SPI_CR1_SSM | // software slave select management
SPI_CR1_SSI | // assert software select state
SPI_CR1_CPHA | // clock phase: cpol=0, cpha=1
SPI_CR1_MSTR | // master mode
SPI_CR1_BR_1 | // baud rate = pclk / 8 = 48/8 = 6 mhz
SPI_CR1_DFF | // set to 16-bit data frames
SPI_CR1_SPE ; // spi enable
// todo: if we want to be fancy, set up a RX interrupt...
/*
enc_txrx(0x0019); // write reg 0x19 (settings2);
enc_txrx(5 << 5); // set A/B/I res to 200
*/
}
void enet_mac_init_pins(void)
{
printf("enet_init_pins()\r\n");
pin_set_alternate_function(GPIOA, PORTA_ETH_REFCLK, AF_ENET);
pin_set_alternate_function(GPIOA, PORTA_ETH_MDIO , AF_ENET);
pin_set_alternate_function(GPIOC, PORTC_ETH_MDC , AF_ENET);
pin_set_alternate_function(GPIOG, PORTG_ETH_TXEN , AF_ENET);
pin_set_alternate_function(GPIOC, PORTC_ETH_TXCLK , AF_ENET);
pin_set_alternate_function(GPIOG, PORTG_ETH_TXD0 , AF_ENET);
pin_set_alternate_function(GPIOG, PORTG_ETH_TXD1 , AF_ENET);
pin_set_alternate_function(GPIOC, PORTC_ETH_TXD2 , AF_ENET);
pin_set_alternate_function(GPIOB, PORTB_ETH_TXD3 , AF_ENET);
pin_set_alternate_function(GPIOA, PORTA_ETH_CRSDV , AF_ENET);
pin_set_alternate_function(GPIOC, PORTC_ETH_RXD0 , AF_ENET);
pin_set_alternate_function(GPIOC, PORTC_ETH_RXD1 , AF_ENET);
pin_set_alternate_function(GPIOH, PORTH_ETH_RXD2 , AF_ENET);
pin_set_alternate_function(GPIOH, PORTH_ETH_RXD3 , AF_ENET);
pin_set_output_speed(GPIOG, PORTG_ETH_TXEN , 3); // max beef
pin_set_output_speed(GPIOC, PORTC_ETH_TXCLK, 3); // max beef
pin_set_output_speed(GPIOG, PORTG_ETH_TXD0 , 3); // max beef
pin_set_output_speed(GPIOG, PORTG_ETH_TXD1 , 3); // max beef
pin_set_output_speed(GPIOC, PORTC_ETH_TXD2 , 3); // max beef
pin_set_output_speed(GPIOB, PORTB_ETH_TXD3 , 3); // max beef
}
