Exemplo n.º 1
0
static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
{
  //#
  //# Set the Synchronous clock division ratio for each clock domain
  //#
  pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);

  //#
  //# Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
  //#
#if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
    ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__)  )))
    flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
#elif ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
  ||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
    flashc_set_flash_waitstate_and_readmode(param->cpu_f);
#endif


  //#
  //# Switch the main clock source to the selected clock.
  //#
  pm_set_mclk_source(main_clk_src);

  return PASS;
}
Exemplo n.º 2
0
static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
{
  //#
  //# Set the Synchronous clock division ratio for each clock domain
  //#
  pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);

  //#
  //# Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
  //#
#if UC3L
    flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
#elif UC3C
    flashc_set_flash_waitstate_and_readmode(param->cpu_f);
#endif


  //#
  //# Switch the main clock source to the selected clock.
  //#
  pm_set_mclk_source(main_clk_src);

  return PASS;
}