void pmc_sleep(int sleep_mode)
{
switch (sleep_mode) {
case SAM_PM_SMODE_SLEEP_WFI:
case SAM_PM_SMODE_SLEEP_WFE:
#if (SAM4S || SAM4E)
SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;
cpu_irq_enable();
__WFI();
break;
#else
PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM;
SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;
cpu_irq_enable();
if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI)
__WFI();
else
__WFE();
break;
#endif
case SAM_PM_SMODE_WAIT: {
uint32_t mor, pllr0, pllr1, mckr;
cpu_irq_disable();
b_is_fastrc_used = true;
pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr);
/* Enter wait mode */
cpu_irq_enable();
pmc_enable_waitmode();
cpu_irq_disable();
pmc_restore_clock_setting(mor, pllr0, pllr1, mckr);
b_is_fastrc_used = false;
if (callback_clocks_restored) {
callback_clocks_restored();
callback_clocks_restored = NULL;
}
cpu_irq_enable();
break;
}
case SAM_PM_SMODE_BACKUP:
SCB->SCR |= SCR_SLEEPDEEP;
#if (SAM4S || SAM4E)
SUPC->SUPC_CR = SUPC_CR_KEY(0xA5u) | SUPC_CR_VROFF_STOP_VREG;
cpu_irq_enable();
__WFI() ;
#else
cpu_irq_enable();
__WFE() ;
#endif
break;
}
}
/**
* \brief Test wait mode.
*/
static void test_wait_mode(void)
{
puts(STRING_WAIT);
#if SAMG55
/* Wait for the transmission done before changing clock */
while (!usart_is_tx_empty(CONSOLE_UART)) {
}
#else
/* Wait for the transmission done before changing clock */
while (!uart_is_tx_empty(CONSOLE_UART)) {
}
#endif
/* Configure fast RC oscillator */
pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1);
#if (SAMG)
pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
#else
pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
#endif
pmc_switch_mck_to_mainck(PMC_PCK_PRES_CLK_1);
#if (SAMG)
g_ul_current_mck = 8000000; /* 8MHz */
#else
g_ul_current_mck = 4000000; /* 4MHz */
#endif
/* Disable unused clock to save power */
pmc_osc_disable_xtal(0);
example_disable_pll();
/* Set wakeup input for fast startup */
example_set_wakeup_from_wait_mode();
/* Enter into wait Mode */
pmc_enable_waitmode();
/* Set default clock and re-configure UART */
set_default_working_clock();
reconfigure_console(g_ul_current_mck, CONF_UART_BAUDRATE);
puts("Exit from wait Mode.\r");
}
void pmc_sleep(int sleep_mode)
{
switch (sleep_mode) {
#if (!(SAMG51 || SAMG53 || SAMG54))
case SAM_PM_SMODE_SLEEP_WFI:
case SAM_PM_SMODE_SLEEP_WFE:
#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70)
SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;
cpu_irq_enable();
__WFI();
break;
#else
PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM;
SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;
cpu_irq_enable();
if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI)
__WFI();
else
__WFE();
break;
#endif
#endif
case SAM_PM_SMODE_WAIT_FAST:
case SAM_PM_SMODE_WAIT: {
uint32_t mor, pllr0, pllr1, mckr;
uint32_t fmr;
#if defined(EFC1)
uint32_t fmr1;
#endif
#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70)
(sleep_mode == SAM_PM_SMODE_WAIT_FAST) ?
pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_STANDBY) :
pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN);
#endif
cpu_irq_disable();
b_is_sleep_clock_used = true;
#if (SAM4C || SAM4CM || SAM4CP)
/* Backup the sub-system 1 status and stop sub-system 1 */
uint32_t cpclk_backup = PMC->PMC_SCSR &
(PMC_SCSR_CPCK | PMC_SCSR_CPBMCK);
PMC->PMC_SCDR = cpclk_backup | PMC_SCDR_CPKEY_PASSWD;
#endif
pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr, &fmr,
#if defined(EFC1)
&fmr1,
#endif
(sleep_mode == SAM_PM_SMODE_WAIT));
/* Enter wait mode */
cpu_irq_enable();
pmc_enable_waitmode();
cpu_irq_disable();
pmc_restore_clock_setting(mor, pllr0, pllr1, mckr, fmr
#if defined(EFC1)
, fmr1
#endif
);
#if (SAM4C || SAM4CM || SAM4CP)
/* Restore the sub-system 1 */
PMC->PMC_SCER = cpclk_backup | PMC_SCER_CPKEY_PASSWD;
#endif
b_is_sleep_clock_used = false;
if (callback_clocks_restored) {
callback_clocks_restored();
callback_clocks_restored = NULL;
}
cpu_irq_enable();
break;
}
#if (!(SAMG51 || SAMG53 || SAMG54))
case SAM_PM_SMODE_BACKUP:
SCB->SCR |= SCR_SLEEPDEEP;
#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70)
SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
cpu_irq_enable();
__WFI() ;
#else
cpu_irq_enable();
__WFE() ;
#endif
break;
#endif
}
}
