void xbus_cfg(pnp_devfn_t dev)
{
u8 i;
u16 xbus_index;
pnp_set_logical_device(dev);
/* Select proper BIOS size (4MB). */
pnp_write_config(dev, PC87417_XMEMCNF2,
(pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04);
xbus_index = pnp_read_iobase(dev, 0x60);
/* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
for (i = 0; i <= 0xf; i++)
outb((i << 4), xbus_index + PC87417_HAP0);
}
static void mainboard_set_e7520_pll(unsigned bits)
{
uint16_t gpio_index;
uint8_t data;
device_t dev;
/* currently only handle the Jarrell/PC87427 case */
dev = PC87427_GPIO_DEV;
pnp_set_logical_device(dev);
gpio_index = pnp_read_iobase(dev, 0x60);
/* select SIO GPIO port 4, pin 2 */
pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x42));
/* set to push-pull, enable output */
pnp_write_config(dev, PC87427_GPCFG1, 0x03);
/* select SIO GPIO port 4, pin 4 */
pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x44));
/* set to push-pull, enable output */
pnp_write_config(dev, PC87427_GPCFG1, 0x03);
/* set gpio 42,44 signal levels */
data = inb(gpio_index + PC87427_GPDO_4);
if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
print_debug("set_pllsel: correct settings detected!\n");
return; /* settings already configured */
} else {
outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
/* reset */
print_debug("set_pllsel: settings adjusted, now resetting...\n");
// hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
// mch_reset();
full_reset();
}
return;
}
