static void
ppc_linux_sigtramp_cache (struct frame_info *next_frame,
struct trad_frame_cache *this_cache,
CORE_ADDR func, LONGEST offset,
int bias)
{
CORE_ADDR base;
CORE_ADDR regs;
CORE_ADDR gpregs;
CORE_ADDR fpregs;
int i;
struct gdbarch *gdbarch = get_frame_arch (next_frame);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
base = frame_unwind_register_unsigned (next_frame,
gdbarch_sp_regnum (current_gdbarch));
if (bias > 0 && frame_pc_unwind (next_frame) != func)
/* See below, some signal trampolines increment the stack as their
first instruction, need to compensate for that. */
base -= bias;
/* Find the address of the register buffer pointer. */
regs = base + offset;
/* Use that to find the address of the corresponding register
buffers. */
gpregs = read_memory_unsigned_integer (regs, tdep->wordsize);
fpregs = gpregs + 48 * tdep->wordsize;
/* General purpose. */
for (i = 0; i < 32; i++)
{
int regnum = i + tdep->ppc_gp0_regnum;
trad_frame_set_reg_addr (this_cache, regnum, gpregs + i * tdep->wordsize);
}
trad_frame_set_reg_addr (this_cache,
gdbarch_pc_regnum (current_gdbarch),
gpregs + 32 * tdep->wordsize);
trad_frame_set_reg_addr (this_cache, tdep->ppc_ctr_regnum,
gpregs + 35 * tdep->wordsize);
trad_frame_set_reg_addr (this_cache, tdep->ppc_lr_regnum,
gpregs + 36 * tdep->wordsize);
trad_frame_set_reg_addr (this_cache, tdep->ppc_xer_regnum,
gpregs + 37 * tdep->wordsize);
trad_frame_set_reg_addr (this_cache, tdep->ppc_cr_regnum,
gpregs + 38 * tdep->wordsize);
if (ppc_floating_point_unit_p (gdbarch))
{
/* Floating point registers. */
for (i = 0; i < 32; i++)
{
int regnum = i + gdbarch_fp0_regnum (current_gdbarch);
trad_frame_set_reg_addr (this_cache, regnum,
fpregs + i * tdep->wordsize);
}
trad_frame_set_reg_addr (this_cache, tdep->ppc_fpscr_regnum,
fpregs + 32 * tdep->wordsize);
}
trad_frame_set_id (this_cache, frame_id_build (base, func));
}
void
ppcfbsd_fill_fpreg (char *fpregs, int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
int i;
/* FIXME: jimb/2004-05-05: Some PPC variants don't have floating
point registers. Traditionally, GDB's register set has still
listed the floating point registers for such machines, so this
code is harmless. However, the new E500 port actually omits the
floating point registers entirely from the register set --- they
don't even have register numbers assigned to them.
It's not clear to me how best to update this code, so this assert
will alert the first person to encounter the NetBSD/E500
combination to the problem. */
gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
for (i = FP0_REGNUM; i <= FPLAST_REGNUM; i++)
{
if (regno == i || regno == -1)
regcache_raw_collect (current_regcache, i, fpregs +
FPREG_FPR_OFFSET (i - FP0_REGNUM));
}
if (regno == tdep->ppc_fpscr_regnum || regno == -1)
regcache_raw_collect (current_regcache, tdep->ppc_fpscr_regnum,
fpregs + FPREG_FPSCR_OFFSET);
}
static void
bdm_ppc_store_registers (int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
int i;
int first_regno, last_regno;
int first_bdm_regno, last_bdm_regno;
if (regno == -1)
{
first_regno = 0;
last_regno = NUM_REGS - 1;
first_bdm_regno = 0;
last_bdm_regno = BDM_NUM_REGS - 1;
}
else
{
first_regno = regno;
last_regno = regno;
first_bdm_regno = bdm_regmap[regno];
last_bdm_regno = bdm_regmap[regno];
}
if (first_bdm_regno == -1)
return; /* Unsupported register */
/* FIXME: jimb/2004-05-04: I'm not sure how to adapt this code to
processors that lack floating point registers, and I don't have
have the equipment to test it. So we'll leave that case for the
next person who encounters it. */
gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
for (i = first_regno; i <= last_regno; i++)
{
int bdm_regno;
bdm_regno = bdm_regmap[i];
/* only attempt to write if it's a valid ppc 8xx register */
/* (need to avoid FP regs and MQ reg) */
if ((i != gdbarch_tdep (current_gdbarch)->ppc_mq_regnum)
&& (i != gdbarch_tdep (current_gdbarch)->ppc_fpscr_regnum)
&& ((i < tdep->ppc_fp0_regnum)
|| (i >= tdep->ppc_fp0_regnum + ppc_num_fprs)))
{
/* printf("write valid reg %d\n", bdm_regno); */
ocd_write_bdm_registers (bdm_regno, deprecated_registers + DEPRECATED_REGISTER_BYTE (i), 4);
}
/*
else if (i == gdbarch_tdep (current_gdbarch)->ppc_mq_regnum)
printf("don't write invalid reg %d (PPC_MQ_REGNUM)\n", bdm_regno);
else
printf("don't write invalid reg %d\n", bdm_regno);
*/
}
}
/* Given a pointer to a floating point register set in /proc format
(fpregset_t *), update the register specified by REGNO from gdb's
idea of the current floating point register set. If REGNO is -1,
update them all. */
void
fill_fpregset (gdb_fpregset_t *fpregsetp, int regno)
{
int regi;
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
bfd_byte *fpp = (void *) fpregsetp;
if (ppc_floating_point_unit_p (current_gdbarch))
{
for (regi = 0; regi < ppc_num_fprs; regi++)
{
if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi))
regcache_raw_collect (current_regcache, tdep->ppc_fp0_regnum + regi,
fpp + 8 * regi);
}
if (regno == -1 || regno == tdep->ppc_fpscr_regnum)
right_fill_reg (tdep->ppc_fpscr_regnum, (fpp + 8 * 32));
}
}
/* Like above, but for PT_GETFPREGS. */
static int
getfpregs_supplies (int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
/* FIXME: jimb/2004-05-05: Some PPC variants don't have floating
point registers. Traditionally, GDB's register set has still
listed the floating point registers for such machines, so this
code is harmless. However, the new E500 port actually omits the
floating point registers entirely from the register set --- they
don't even have register numbers assigned to them.
It's not clear to me how best to update this code, so this assert
will alert the first person to encounter the NetBSD/E500
combination to the problem. */
gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
return ((regno >= FP0_REGNUM && regno <= FPLAST_REGNUM)
|| regno == tdep->ppc_fpscr_regnum);
}
static CORE_ADDR
rs6000_lynx178_push_dummy_call (struct gdbarch *gdbarch,
struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int ii;
int len = 0;
int argno; /* current argument number */
int argbytes; /* current argument byte */
gdb_byte tmp_buffer[50];
int f_argno = 0; /* current floating point argno */
int wordsize = gdbarch_tdep (gdbarch)->wordsize;
CORE_ADDR func_addr = find_function_addr (function, NULL);
struct value *arg = 0;
struct type *type;
ULONGEST saved_sp;
/* The calling convention this function implements assumes the
processor has floating-point registers. We shouldn't be using it
on PPC variants that lack them. */
gdb_assert (ppc_floating_point_unit_p (gdbarch));
/* The first eight words of ther arguments are passed in registers.
Copy them appropriately. */
ii = 0;
/* If the function is returning a `struct', then the first word
(which will be passed in r3) is used for struct return address.
In that case we should advance one word and start from r4
register to copy parameters. */
if (struct_return)
{
regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
struct_addr);
ii++;
}
/* Effectively indirect call... gcc does...
return_val example( float, int);
eabi:
float in fp0, int in r3
offset of stack on overflow 8/16
for varargs, must go by type.
power open:
float in r3&r4, int in r5
offset of stack on overflow different
both:
return in r3 or f0. If no float, must study how gcc emulates floats;
pay attention to arg promotion.
User may have to cast\args to handle promotion correctly
since gdb won't know if prototype supplied or not. */
for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
{
int reg_size = register_size (gdbarch, ii + 3);
arg = args[argno];
type = check_typedef (value_type (arg));
len = TYPE_LENGTH (type);
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
/* Floating point arguments are passed in fpr's, as well as gpr's.
There are 13 fpr's reserved for passing parameters. At this point
there is no way we would run out of them.
Always store the floating point value using the register's
floating-point format. */
const int fp_regnum = tdep->ppc_fp0_regnum + 1 + f_argno;
gdb_byte reg_val[MAX_REGISTER_SIZE];
struct type *reg_type = register_type (gdbarch, fp_regnum);
gdb_assert (len <= 8);
convert_typed_floating (value_contents (arg), type,
reg_val, reg_type);
regcache_cooked_write (regcache, fp_regnum, reg_val);
++f_argno;
}
if (len > reg_size)
{
/* Argument takes more than one register. */
while (argbytes < len)
{
gdb_byte word[MAX_REGISTER_SIZE];
memset (word, 0, reg_size);
memcpy (word,
((char *) value_contents (arg)) + argbytes,
(len - argbytes) > reg_size
? reg_size : len - argbytes);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + 3 + ii,
word);
++ii, argbytes += reg_size;
if (ii >= 8)
goto ran_out_of_registers_for_arguments;
}
argbytes = 0;
--ii;
}
else
{
/* Argument can fit in one register. No problem. */
int adj = gdbarch_byte_order (gdbarch)
== BFD_ENDIAN_BIG ? reg_size - len : 0;
gdb_byte word[MAX_REGISTER_SIZE];
memset (word, 0, reg_size);
memcpy (word, value_contents (arg), len);
regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
}
++argno;
}
ran_out_of_registers_for_arguments:
regcache_cooked_read_unsigned (regcache,
gdbarch_sp_regnum (gdbarch),
&saved_sp);
/* Location for 8 parameters are always reserved. */
sp -= wordsize * 8;
/* Another six words for back chain, TOC register, link register, etc. */
sp -= wordsize * 6;
/* Stack pointer must be quadword aligned. */
sp = align_down (sp, 16);
/* If there are more arguments, allocate space for them in
the stack, then push them starting from the ninth one. */
if ((argno < nargs) || argbytes)
{
int space = 0, jj;
if (argbytes)
{
space += align_up (len - argbytes, 4);
jj = argno + 1;
}
else
jj = argno;
for (; jj < nargs; ++jj)
{
struct value *val = args[jj];
space += align_up (TYPE_LENGTH (value_type (val)), 4);
}
/* Add location required for the rest of the parameters. */
space = align_up (space, 16);
sp -= space;
/* This is another instance we need to be concerned about
securing our stack space. If we write anything underneath %sp
(r1), we might conflict with the kernel who thinks he is free
to use this area. So, update %sp first before doing anything
else. */
regcache_raw_write_signed (regcache,
gdbarch_sp_regnum (gdbarch), sp);
/* If the last argument copied into the registers didn't fit there
completely, push the rest of it into stack. */
if (argbytes)
{
write_memory (sp + 24 + (ii * 4),
value_contents (arg) + argbytes,
len - argbytes);
++argno;
ii += align_up (len - argbytes, 4) / 4;
}
/* Push the rest of the arguments into stack. */
for (; argno < nargs; ++argno)
{
arg = args[argno];
type = check_typedef (value_type (arg));
len = TYPE_LENGTH (type);
/* Float types should be passed in fpr's, as well as in the
stack. */
if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
{
gdb_assert (len <= 8);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + 1 + f_argno,
value_contents (arg));
++f_argno;
}
write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
ii += align_up (len, 4) / 4;
}
}
/* Set the stack pointer. According to the ABI, the SP is meant to
be set _before_ the corresponding stack space is used. On AIX,
this even applies when the target has been completely stopped!
Not doing this can lead to conflicts with the kernel which thinks
that it still has control over this not-yet-allocated stack
region. */
regcache_raw_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp);
/* Set back chain properly. */
store_unsigned_integer (tmp_buffer, wordsize, byte_order, saved_sp);
write_memory (sp, tmp_buffer, wordsize);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
target_store_registers (regcache, -1);
return sp;
}
static enum return_value_convention
rs6000_lynx178_return_value (struct gdbarch *gdbarch, struct value *function,
struct type *valtype, struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
/* The calling convention this function implements assumes the
processor has floating-point registers. We shouldn't be using it
on PowerPC variants that lack them. */
gdb_assert (ppc_floating_point_unit_p (gdbarch));
/* AltiVec extension: Functions that declare a vector data type as a
return value place that return value in VR2. */
if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype)
&& TYPE_LENGTH (valtype) == 16)
{
if (readbuf)
regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
if (writebuf)
regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* If the called subprogram returns an aggregate, there exists an
implicit first argument, whose value is the address of a caller-
allocated buffer into which the callee is assumed to store its
return value. All explicit parameters are appropriately
relabeled. */
if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
|| TYPE_CODE (valtype) == TYPE_CODE_UNION
|| TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
return RETURN_VALUE_STRUCT_CONVENTION;
/* Scalar floating-point values are returned in FPR1 for float or
double, and in FPR1:FPR2 for quadword precision. Fortran
complex*8 and complex*16 are returned in FPR1:FPR2, and
complex*32 is returned in FPR1:FPR4. */
if (TYPE_CODE (valtype) == TYPE_CODE_FLT
&& (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8))
{
struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
gdb_byte regval[8];
/* FIXME: kettenis/2007-01-01: Add support for quadword
precision and complex. */
if (readbuf)
{
regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
convert_typed_floating (regval, regtype, readbuf, valtype);
}
if (writebuf)
{
convert_typed_floating (writebuf, valtype, regval, regtype);
regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* Values of the types int, long, short, pointer, and char (length
is less than or equal to four bytes), as well as bit values of
lengths less than or equal to 32 bits, must be returned right
justified in GPR3 with signed values sign extended and unsigned
values zero extended, as necessary. */
if (TYPE_LENGTH (valtype) <= tdep->wordsize)
{
if (readbuf)
{
ULONGEST regval;
/* For reading we don't have to worry about sign extension. */
regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
®val);
store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), byte_order,
regval);
}
if (writebuf)
{
/* For writing, use unpack_long since that should handle any
required sign extension. */
regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
unpack_long (valtype, writebuf));
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* Eight-byte non-floating-point scalar values must be returned in
GPR3:GPR4. */
if (TYPE_LENGTH (valtype) == 8)
{
gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT);
gdb_assert (tdep->wordsize == 4);
if (readbuf)
{
gdb_byte regval[8];
regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval);
regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
regval + 4);
memcpy (readbuf, regval, 8);
}
if (writebuf)
{
regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
writebuf + 4);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
return RETURN_VALUE_STRUCT_CONVENTION;
}
CORE_ADDR
ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
CORE_ADDR func_addr = find_function_addr (function, NULL);
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
/* By this stage in the proceedings, SP has been decremented by "red
zone size" + "struct return size". Fetch the stack-pointer from
before this and use that as the BACK_CHAIN. */
const CORE_ADDR back_chain = read_sp ();
/* See for-loop comment below. */
int write_pass;
/* Size of the Altivec's vector parameter region, the final value is
computed in the for-loop below. */
LONGEST vparam_size = 0;
/* Size of the general parameter region, the final value is computed
in the for-loop below. */
LONGEST gparam_size = 0;
/* Kevin writes ... I don't mind seeing tdep->wordsize used in the
calls to align_up(), align_down(), etc. because this makes it
easier to reuse this code (in a copy/paste sense) in the future,
but it is a 64-bit ABI and asserting that the wordsize is 8 bytes
at some point makes it easier to verify that this function is
correct without having to do a non-local analysis to figure out
the possible values of tdep->wordsize. */
gdb_assert (tdep->wordsize == 8);
/* Go through the argument list twice.
Pass 1: Compute the function call's stack space and register
requirements.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-vector (but possibly
float) arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* The address, at which the next general purpose parameter
(integer, struct, float, ...) should be saved. */
CORE_ADDR gparam;
/* Address, at which the next Altivec vector parameter should be
saved. */
CORE_ADDR vparam;
if (!write_pass)
{
/* During the first pass, GPARAM and VPARAM are more like
offsets (start address zero) than addresses. That way
the accumulate the total stack space each region
requires. */
gparam = 0;
vparam = 0;
}
else
{
/* Decrement the stack pointer making space for the Altivec
and general on-stack parameters. Set vparam and gparam
to their corresponding regions. */
vparam = align_down (sp - vparam_size, 16);
gparam = align_down (vparam - gparam_size, 16);
/* Add in space for the TOC, link editor double word,
compiler double word, LR save area, CR save area. */
sp = align_down (gparam - 48, 16);
}
/* If the function is returning a `struct', then there is an
extra hidden parameter (which will be passed in r3)
containing the address of that struct.. In that case we
should advance one word and start from r4 register to copy
parameters. This also consumes one on-stack parameter slot. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
gparam = align_up (gparam + tdep->wordsize, tdep->wordsize);
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (value_type (arg));
const bfd_byte *val = value_contents (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) <= 8)
{
/* Floats and Doubles go in f1 .. f13. They also
consume a left aligned GREG,, and can end up in
memory. */
if (write_pass)
{
if (ppc_floating_point_unit_p (current_gdbarch)
&& freg <= 13)
{
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
if (greg <= 10)
{
/* The ABI states "Single precision floating
point values are mapped to the first word in
a single doubleword" and "... floating point
values mapped to the first eight doublewords
of the parameter save area are also passed in
general registers").
This code interprets that to mean: store it,
left aligned, in the general register. */
gdb_byte regval[MAX_REGISTER_SIZE];
memset (regval, 0, sizeof regval);
memcpy (regval, val, TYPE_LENGTH (type));
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg,
regval);
}
write_memory (gparam, val, TYPE_LENGTH (type));
}
/* Always consume parameter stack space. */
freg++;
greg++;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else if (TYPE_LENGTH (type) == 16 && TYPE_VECTOR (type)
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& tdep->ppc_vr0_regnum >= 0)
{
/* In the Altivec ABI, vectors go in the vector
registers v2 .. v13, or when that runs out, a vector
annex which goes above all the normal parameters.
NOTE: cagney/2003-09-21: This is a guess based on the
PowerOpen Altivec ABI. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
if (write_pass)
write_memory (vparam, val, TYPE_LENGTH (type));
vparam = align_up (vparam + TYPE_LENGTH (type), 16);
}
}
else if ((TYPE_CODE (type) == TYPE_CODE_INT
|| TYPE_CODE (type) == TYPE_CODE_ENUM
|| TYPE_CODE (type) == TYPE_CODE_PTR)
&& TYPE_LENGTH (type) <= 8)
{
/* Scalars and Pointers get sign[un]extended and go in
gpr3 .. gpr10. They can also end up in memory. */
if (write_pass)
{
/* Sign extend the value, then store it unsigned. */
ULONGEST word = unpack_long (type, val);
/* Convert any function code addresses into
descriptors. */
if (TYPE_CODE (type) == TYPE_CODE_PTR
&& TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
{
CORE_ADDR desc = word;
convert_code_addr_to_desc_addr (word, &desc);
word = desc;
}
if (greg <= 10)
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum +
greg, word);
write_memory_unsigned_integer (gparam, tdep->wordsize,
word);
}
greg++;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else
{
int byte;
for (byte = 0; byte < TYPE_LENGTH (type);
byte += tdep->wordsize)
{
if (write_pass && greg <= 10)
{
gdb_byte regval[MAX_REGISTER_SIZE];
int len = TYPE_LENGTH (type) - byte;
if (len > tdep->wordsize)
len = tdep->wordsize;
memset (regval, 0, sizeof regval);
/* WARNING: cagney/2003-09-21: As best I can
tell, the ABI specifies that the value should
be left aligned. Unfortunately, GCC doesn't
do this - it instead right aligns even sized
values and puts odd sized values on the
stack. Work around that by putting both a
left and right aligned value into the
register (hopefully no one notices :-^).
Arrrgh! */
/* Left aligned (8 byte values such as pointers
fill the buffer). */
memcpy (regval, val + byte, len);
/* Right aligned (but only if even). */
if (len == 1 || len == 2 || len == 4)
memcpy (regval + tdep->wordsize - len,
val + byte, len);
regcache_cooked_write (regcache, greg, regval);
}
greg++;
}
if (write_pass)
/* WARNING: cagney/2003-09-21: Strictly speaking, this
isn't necessary, unfortunately, GCC appears to get
"struct convention" parameter passing wrong putting
odd sized structures in memory instead of in a
register. Work around this by always writing the
value to memory. Fortunately, doing this
simplifies the code. */
write_memory (gparam, val, TYPE_LENGTH (type));
if (write_pass)
/* WARNING: cagney/2004-06-20: It appears that GCC
likes to put structures containing a single
floating-point member in an FP register instead of
general general purpose. */
/* Always consume parameter stack space. */
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
}
if (!write_pass)
{
/* Save the true region sizes ready for the second pass. */
vparam_size = vparam;
/* Make certain that the general parameter save area is at
least the minimum 8 registers (or doublewords) in size. */
if (greg < 8)
gparam_size = 8 * tdep->wordsize;
else
gparam_size = gparam;
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, back_chain);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
/* Use the func_addr to find the descriptor, and use that to find
the TOC. */
{
CORE_ADDR desc_addr;
if (convert_code_addr_to_desc_addr (func_addr, &desc_addr))
{
/* The TOC is the second double word in the descriptor. */
CORE_ADDR toc =
read_memory_unsigned_integer (desc_addr + tdep->wordsize,
tdep->wordsize);
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum + 2, toc);
}
}
return sp;
}
static enum return_value_convention
do_ppc_sysv_return_value (struct gdbarch *gdbarch, struct type *type,
/* APPLE LOCAL gdb_byte */
struct regcache *regcache, gdb_byte *readbuf,
/* APPLE LOCAL gdb_byte */
const gdb_byte *writebuf, int broken_gcc)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
gdb_assert (tdep->wordsize == 4);
if (TYPE_CODE (type) == TYPE_CODE_FLT
&& TYPE_LENGTH (type) <= 8
&& ppc_floating_point_unit_p (gdbarch))
{
if (readbuf)
{
/* Floats and doubles stored in "f1". Convert the value to
the required type. */
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype = register_type (gdbarch,
tdep->ppc_fp0_regnum + 1);
regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
convert_typed_floating (regval, regtype, readbuf, type);
}
if (writebuf)
{
/* Floats and doubles stored in "f1". Convert the value to
the register's "double" type. */
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
convert_typed_floating (writebuf, type, regval, regtype);
regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* APPLE LOCAL: gcc 3.3 had 8 byte long doubles, but gcc 4.0 uses 16 byte
long doubles even for 32 bit ppc. They are stored across f1 & f2. */
/* Big floating point values get stored in adjacent floating
point registers. */
if (TYPE_CODE (type) == TYPE_CODE_FLT
&& (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 32))
{
if (writebuf || readbuf != NULL)
{
int i;
for (i = 0; i < TYPE_LENGTH (type) / 8; i++)
{
if (writebuf != NULL)
regcache_cooked_write (regcache, FP0_REGNUM + 1 + i,
(const bfd_byte *) writebuf + i * 8);
if (readbuf != NULL)
regcache_cooked_read (regcache, FP0_REGNUM + 1 + i,
(bfd_byte *) readbuf + i * 8);
}
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* END APPLE LOCAL */
if ((TYPE_CODE (type) == TYPE_CODE_INT && TYPE_LENGTH (type) == 8)
|| (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8))
{
if (readbuf)
{
/* A long long, or a double stored in the 32 bit r3/r4. */
ppc_copy_from_greg (regcache, tdep->ppc_gp0_regnum + 3,
tdep->wordsize, 8, (bfd_byte *) readbuf);
}
if (writebuf)
{
/* A long long, or a double stored in the 32 bit r3/r4. */
ppc_copy_into_greg (regcache, tdep->ppc_gp0_regnum + 3,
tdep->wordsize, 8, writebuf);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
if (TYPE_CODE (type) == TYPE_CODE_INT
&& TYPE_LENGTH (type) <= tdep->wordsize)
{
if (readbuf)
{
/* Some sort of integer stored in r3. Since TYPE isn't
bigger than the register, sign extension isn't a problem
- just do everything unsigned. */
ULONGEST regval;
regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
®val);
store_unsigned_integer (readbuf, TYPE_LENGTH (type), regval);
}
if (writebuf)
{
/* Some sort of integer stored in r3. Use unpack_long since
that should handle any required sign extension. */
regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
unpack_long (type, writebuf));
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
if (TYPE_LENGTH (type) == 16
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type) && tdep->ppc_vr0_regnum >= 0)
{
if (readbuf)
{
/* Altivec places the return value in "v2". */
regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
}
if (writebuf)
{
/* Altivec places the return value in "v2". */
regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
if (TYPE_LENGTH (type) == 8
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type) && tdep->ppc_ev0_regnum >= 0)
{
/* The e500 ABI places return values for the 64-bit DSP types
(__ev64_opaque__) in r3. However, in GDB-speak, ev3
corresponds to the entire r3 value for e500, whereas GDB's r3
only corresponds to the least significant 32-bits. So place
the 64-bit DSP type's value in ev3. */
if (readbuf)
regcache_cooked_read (regcache, tdep->ppc_ev0_regnum + 3, readbuf);
if (writebuf)
regcache_cooked_write (regcache, tdep->ppc_ev0_regnum + 3, writebuf);
return RETURN_VALUE_REGISTER_CONVENTION;
}
if (broken_gcc && TYPE_LENGTH (type) <= 8)
{
if (readbuf)
{
/* GCC screwed up. The last register isn't "left" aligned.
Need to extract the least significant part of each
register and then store that. */
/* Transfer any full words. */
int word = 0;
while (1)
{
ULONGEST reg;
int len = TYPE_LENGTH (type) - word * tdep->wordsize;
if (len <= 0)
break;
if (len > tdep->wordsize)
len = tdep->wordsize;
regcache_cooked_read_unsigned (regcache,
tdep->ppc_gp0_regnum + 3 + word,
®);
store_unsigned_integer (((bfd_byte *) readbuf
+ word * tdep->wordsize), len, reg);
word++;
}
}
if (writebuf)
{
/* GCC screwed up. The last register isn't "left" aligned.
Need to extract the least significant part of each
register and then store that. */
/* Transfer any full words. */
int word = 0;
while (1)
{
ULONGEST reg;
int len = TYPE_LENGTH (type) - word * tdep->wordsize;
if (len <= 0)
break;
if (len > tdep->wordsize)
len = tdep->wordsize;
reg = extract_unsigned_integer (((const bfd_byte *) writebuf
+ word * tdep->wordsize), len);
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum + 3 + word,
reg);
word++;
}
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
if (TYPE_LENGTH (type) <= 8)
{
if (readbuf)
{
/* This matches SVr4 PPC, it does not match GCC. */
/* The value is right-padded to 8 bytes and then loaded, as
two "words", into r3/r4. */
ppc_copy_from_greg (regcache, tdep->ppc_gp0_regnum + 3,
tdep->wordsize, TYPE_LENGTH (type), readbuf);
}
if (writebuf)
{
/* This matches SVr4 PPC, it does not match GCC. */
/* The value is padded out to 8 bytes and then loaded, as
two "words" into r3/r4. */
gdb_byte regvals[MAX_REGISTER_SIZE * 2];
memset (regvals, 0, sizeof regvals);
memcpy (regvals, writebuf, TYPE_LENGTH (type));
regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3,
regvals + 0 * tdep->wordsize);
if (TYPE_LENGTH (type) > tdep->wordsize)
regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
regvals + 1 * tdep->wordsize);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
return RETURN_VALUE_STRUCT_CONVENTION;
}
/* The 64 bit ABI retun value convention.
Return non-zero if the return-value is stored in a register, return
0 if the return-value is instead stored on the stack (a.k.a.,
struct return convention).
For a return-value stored in a register: when WRITEBUF is non-NULL,
copy the buffer to the corresponding register return-value location
location; when READBUF is non-NULL, fill the buffer from the
corresponding register return-value location. */
enum return_value_convention
ppc64_sysv_abi_return_value (struct gdbarch *gdbarch, struct type *valtype,
struct regcache *regcache, gdb_byte *readbuf,
const gdb_byte *writebuf)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* This function exists to support a calling convention that
requires floating-point registers. It shouldn't be used on
processors that lack them. */
gdb_assert (ppc_floating_point_unit_p (gdbarch));
/* Floats and doubles in F1. */
if (TYPE_CODE (valtype) == TYPE_CODE_FLT && TYPE_LENGTH (valtype) <= 8)
{
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
if (writebuf != NULL)
{
convert_typed_floating (writebuf, valtype, regval, regtype);
regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
}
if (readbuf != NULL)
{
regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
convert_typed_floating (regval, regtype, readbuf, valtype);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
if ((TYPE_CODE (valtype) == TYPE_CODE_INT
|| TYPE_CODE (valtype) == TYPE_CODE_ENUM)
&& TYPE_LENGTH (valtype) <= 8)
{
/* Integers in r3. */
if (writebuf != NULL)
{
/* Be careful to sign extend the value. */
regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
unpack_long (valtype, writebuf));
}
if (readbuf != NULL)
{
/* Extract the integer from r3. Since this is truncating the
value, there isn't a sign extension problem. */
ULONGEST regval;
regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
®val);
store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* All pointers live in r3. */
if (TYPE_CODE (valtype) == TYPE_CODE_PTR)
{
/* All pointers live in r3. */
if (writebuf != NULL)
regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
if (readbuf != NULL)
regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, readbuf);
return RETURN_VALUE_REGISTER_CONVENTION;
}
if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
&& TYPE_LENGTH (valtype) <= 8
&& TYPE_CODE (TYPE_TARGET_TYPE (valtype)) == TYPE_CODE_INT
&& TYPE_LENGTH (TYPE_TARGET_TYPE (valtype)) == 1)
{
/* Small character arrays are returned, right justified, in r3. */
int offset = (register_size (gdbarch, tdep->ppc_gp0_regnum + 3)
- TYPE_LENGTH (valtype));
if (writebuf != NULL)
regcache_cooked_write_part (regcache, tdep->ppc_gp0_regnum + 3,
offset, TYPE_LENGTH (valtype), writebuf);
if (readbuf != NULL)
regcache_cooked_read_part (regcache, tdep->ppc_gp0_regnum + 3,
offset, TYPE_LENGTH (valtype), readbuf);
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* Big floating point values get stored in adjacent floating
point registers. */
if (TYPE_CODE (valtype) == TYPE_CODE_FLT
&& (TYPE_LENGTH (valtype) == 16 || TYPE_LENGTH (valtype) == 32))
{
if (writebuf || readbuf != NULL)
{
int i;
for (i = 0; i < TYPE_LENGTH (valtype) / 8; i++)
{
if (writebuf != NULL)
regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1 + i,
(const bfd_byte *) writebuf + i * 8);
if (readbuf != NULL)
regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1 + i,
(bfd_byte *) readbuf + i * 8);
}
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* Complex values get returned in f1:f2, need to convert. */
if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX
&& (TYPE_LENGTH (valtype) == 8 || TYPE_LENGTH (valtype) == 16))
{
if (regcache != NULL)
{
int i;
for (i = 0; i < 2; i++)
{
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype =
register_type (current_gdbarch, tdep->ppc_fp0_regnum);
if (writebuf != NULL)
{
convert_typed_floating ((const bfd_byte *) writebuf +
i * (TYPE_LENGTH (valtype) / 2),
valtype, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + 1 + i,
regval);
}
if (readbuf != NULL)
{
regcache_cooked_read (regcache,
tdep->ppc_fp0_regnum + 1 + i,
regval);
convert_typed_floating (regval, regtype,
(bfd_byte *) readbuf +
i * (TYPE_LENGTH (valtype) / 2),
valtype);
}
}
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* Big complex values get stored in f1:f4. */
if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX && TYPE_LENGTH (valtype) == 32)
{
if (regcache != NULL)
{
int i;
for (i = 0; i < 4; i++)
{
if (writebuf != NULL)
regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1 + i,
(const bfd_byte *) writebuf + i * 8);
if (readbuf != NULL)
regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1 + i,
(bfd_byte *) readbuf + i * 8);
}
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
return RETURN_VALUE_STRUCT_CONVENTION;
}
static void
bdm_ppc_fetch_registers (int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
int i;
unsigned char *regs;
int first_regno, last_regno;
int first_bdm_regno, last_bdm_regno;
int reglen;
if (regno == -1)
{
first_regno = 0;
last_regno = NUM_REGS - 1;
first_bdm_regno = 0;
last_bdm_regno = BDM_NUM_REGS - 1;
}
else
{
first_regno = regno;
last_regno = regno;
first_bdm_regno = bdm_regmap[regno];
last_bdm_regno = bdm_regmap[regno];
}
if (first_bdm_regno == -1)
{
regcache_raw_supply (current_regcache, first_regno, NULL);
return; /* Unsupported register */
}
/* FIXME: jimb/2004-05-04: I'm not sure how to adapt this code to
processors that lack floating point registers, and I don't have
have the equipment to test it. So we'll leave that case for the
next person who encounters it. */
gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
#if 1
/* Can't ask for floating point regs on ppc 8xx, also need to
avoid asking for the mq register. */
if (first_regno == last_regno) /* only want one reg */
{
/* printf("Asking for register %d\n", first_regno); */
/* if asking for an invalid register */
if ((first_regno == gdbarch_tdep (current_gdbarch)->ppc_mq_regnum)
|| (first_regno == gdbarch_tdep (current_gdbarch)->ppc_fpscr_regnum)
|| ((first_regno >= tdep->ppc_fp0_regnum)
&& (first_regno < tdep->ppc_fp0_regnum + ppc_num_fprs)))
{
/* printf("invalid reg request!\n"); */
regcache_raw_supply (current_regcache, first_regno, NULL);
return; /* Unsupported register */
}
else
{
regs = ocd_read_bdm_registers (first_bdm_regno,
last_bdm_regno, ®len);
}
}
else
internal_error (__FILE__, __LINE__,
"ppc_bdm_fetch_registers: "
"'all registers' case not implemented");
#endif
#if 0
regs = ocd_read_bdm_registers (first_bdm_regno, last_bdm_regno, ®len);
#endif
for (i = first_regno; i <= last_regno; i++)
{
int bdm_regno, regoffset;
bdm_regno = bdm_regmap[i];
if (bdm_regno != -1)
{
regoffset = bdm_regno - first_bdm_regno;
if (regoffset >= reglen / 4)
continue;
regcache_raw_supply (current_regcache, i, regs + 4 * regoffset);
}
else
regcache_raw_supply (current_regcache, i, NULL); /* Unsupported register */
}
}
CORE_ADDR
ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
CORE_ADDR func_addr = find_function_addr (function, NULL);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST back_chain;
/* See for-loop comment below. */
int write_pass;
/* Size of the Altivec's vector parameter region, the final value is
computed in the for-loop below. */
LONGEST vparam_size = 0;
/* Size of the general parameter region, the final value is computed
in the for-loop below. */
LONGEST gparam_size = 0;
/* Kevin writes ... I don't mind seeing tdep->wordsize used in the
calls to align_up(), align_down(), etc. because this makes it
easier to reuse this code (in a copy/paste sense) in the future,
but it is a 64-bit ABI and asserting that the wordsize is 8 bytes
at some point makes it easier to verify that this function is
correct without having to do a non-local analysis to figure out
the possible values of tdep->wordsize. */
gdb_assert (tdep->wordsize == 8);
/* This function exists to support a calling convention that
requires floating-point registers. It shouldn't be used on
processors that lack them. */
gdb_assert (ppc_floating_point_unit_p (gdbarch));
/* By this stage in the proceedings, SP has been decremented by "red
zone size" + "struct return size". Fetch the stack-pointer from
before this and use that as the BACK_CHAIN. */
regcache_cooked_read_unsigned (regcache, gdbarch_sp_regnum (gdbarch),
&back_chain);
/* Go through the argument list twice.
Pass 1: Compute the function call's stack space and register
requirements.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-vector (but possibly
float) arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* The address, at which the next general purpose parameter
(integer, struct, float, ...) should be saved. */
CORE_ADDR gparam;
/* Address, at which the next Altivec vector parameter should be
saved. */
CORE_ADDR vparam;
if (!write_pass)
{
/* During the first pass, GPARAM and VPARAM are more like
offsets (start address zero) than addresses. That way
they accumulate the total stack space each region
requires. */
gparam = 0;
vparam = 0;
}
else
{
/* Decrement the stack pointer making space for the Altivec
and general on-stack parameters. Set vparam and gparam
to their corresponding regions. */
vparam = align_down (sp - vparam_size, 16);
gparam = align_down (vparam - gparam_size, 16);
/* Add in space for the TOC, link editor double word,
compiler double word, LR save area, CR save area. */
sp = align_down (gparam - 48, 16);
}
/* If the function is returning a `struct', then there is an
extra hidden parameter (which will be passed in r3)
containing the address of that struct.. In that case we
should advance one word and start from r4 register to copy
parameters. This also consumes one on-stack parameter slot. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
gparam = align_up (gparam + tdep->wordsize, tdep->wordsize);
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (value_type (arg));
const bfd_byte *val = value_contents (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) <= 8)
{
/* Floats and Doubles go in f1 .. f13. They also
consume a left aligned GREG,, and can end up in
memory. */
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
const gdb_byte *p;
/* Version 1.7 of the 64-bit PowerPC ELF ABI says:
"Single precision floating point values are mapped to
the first word in a single doubleword."
And version 1.9 says:
"Single precision floating point values are mapped to
the second word in a single doubleword."
GDB then writes single precision floating point values
at both words in a doubleword, to support both ABIs. */
if (TYPE_LENGTH (type) == 4)
{
memcpy (regval, val, 4);
memcpy (regval + 4, val, 4);
p = regval;
}
else
p = val;
/* Write value in the stack's parameter save area. */
write_memory (gparam, p, 8);
if (freg <= 13)
{
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
if (greg <= 10)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg,
regval);
}
freg++;
greg++;
/* Always consume parameter stack space. */
gparam = align_up (gparam + 8, tdep->wordsize);
}
else if (TYPE_CODE (type) == TYPE_CODE_FLT
&& TYPE_LENGTH (type) == 16
&& (gdbarch_long_double_format (gdbarch)
== floatformats_ibm_long_double))
{
/* IBM long double stored in two doublewords of the
parameter save area and corresponding registers. */
if (write_pass)
{
if (!tdep->soft_float && freg <= 13)
{
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
val);
if (freg <= 12)
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg + 1,
val + 8);
}
if (greg <= 10)
{
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg,
val);
if (greg <= 9)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 1,
val + 8);
}
write_memory (gparam, val, TYPE_LENGTH (type));
}
freg += 2;
greg += 2;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type) <= 8)
{
/* 32-bit and 64-bit decimal floats go in f1 .. f13. They can
end up in memory. */
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
const gdb_byte *p;
/* 32-bit decimal floats are right aligned in the
doubleword. */
if (TYPE_LENGTH (type) == 4)
{
memcpy (regval + 4, val, 4);
p = regval;
}
else
p = val;
/* Write value in the stack's parameter save area. */
write_memory (gparam, p, 8);
if (freg <= 13)
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg, p);
}
freg++;
greg++;
/* Always consume parameter stack space. */
gparam = align_up (gparam + 8, tdep->wordsize);
}
else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT &&
TYPE_LENGTH (type) == 16)
{
/* 128-bit decimal floats go in f2 .. f12, always in even/odd
pairs. They can end up in memory, using two doublewords. */
if (write_pass)
{
if (freg <= 12)
{
/* Make sure freg is even. */
freg += freg & 1;
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg, val);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg + 1, val + 8);
}
write_memory (gparam, val, TYPE_LENGTH (type));
}
freg += 2;
greg += 2;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else if (TYPE_LENGTH (type) == 16 && TYPE_VECTOR (type)
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& tdep->ppc_vr0_regnum >= 0)
{
/* In the Altivec ABI, vectors go in the vector
registers v2 .. v13, or when that runs out, a vector
annex which goes above all the normal parameters.
NOTE: cagney/2003-09-21: This is a guess based on the
PowerOpen Altivec ABI. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
if (write_pass)
write_memory (vparam, val, TYPE_LENGTH (type));
vparam = align_up (vparam + TYPE_LENGTH (type), 16);
}
}
else if ((TYPE_CODE (type) == TYPE_CODE_INT
|| TYPE_CODE (type) == TYPE_CODE_ENUM
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_PTR
|| TYPE_CODE (type) == TYPE_CODE_REF)
&& TYPE_LENGTH (type) <= 8)
{
/* Scalars and Pointers get sign[un]extended and go in
gpr3 .. gpr10. They can also end up in memory. */
if (write_pass)
{
/* Sign extend the value, then store it unsigned. */
ULONGEST word = unpack_long (type, val);
/* Convert any function code addresses into
descriptors. */
if (TYPE_CODE (type) == TYPE_CODE_PTR
|| TYPE_CODE (type) == TYPE_CODE_REF)
{
struct type *target_type;
target_type = check_typedef (TYPE_TARGET_TYPE (type));
if (TYPE_CODE (target_type) == TYPE_CODE_FUNC
|| TYPE_CODE (target_type) == TYPE_CODE_METHOD)
{
CORE_ADDR desc = word;
convert_code_addr_to_desc_addr (word, &desc);
word = desc;
}
}
if (greg <= 10)
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum +
greg, word);
write_memory_unsigned_integer (gparam, tdep->wordsize,
byte_order, word);
}
greg++;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else
{
int byte;
for (byte = 0; byte < TYPE_LENGTH (type);
byte += tdep->wordsize)
{
if (write_pass && greg <= 10)
{
gdb_byte regval[MAX_REGISTER_SIZE];
int len = TYPE_LENGTH (type) - byte;
if (len > tdep->wordsize)
len = tdep->wordsize;
memset (regval, 0, sizeof regval);
/* The ABI (version 1.9) specifies that values
smaller than one doubleword are right-aligned
and those larger are left-aligned. GCC
versions before 3.4 implemented this
incorrectly; see
<http://gcc.gnu.org/gcc-3.4/powerpc-abi.html>. */
if (byte == 0)
memcpy (regval + tdep->wordsize - len,
val + byte, len);
else
memcpy (regval, val + byte, len);
regcache_cooked_write (regcache, greg, regval);
}
greg++;
}
if (write_pass)
{
/* WARNING: cagney/2003-09-21: Strictly speaking, this
isn't necessary, unfortunately, GCC appears to get
"struct convention" parameter passing wrong putting
odd sized structures in memory instead of in a
register. Work around this by always writing the
value to memory. Fortunately, doing this
simplifies the code. */
int len = TYPE_LENGTH (type);
if (len < tdep->wordsize)
write_memory (gparam + tdep->wordsize - len, val, len);
else
write_memory (gparam, val, len);
}
if (freg <= 13
&& TYPE_CODE (type) == TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type) == 1
&& TYPE_LENGTH (type) <= 16)
{
/* The ABI (version 1.9) specifies that structs
containing a single floating-point value, at any
level of nesting of single-member structs, are
passed in floating-point registers. */
while (TYPE_CODE (type) == TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type) == 1)
type = check_typedef (TYPE_FIELD_TYPE (type, 0));
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
if (TYPE_LENGTH (type) <= 8)
{
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch,
tdep->ppc_fp0_regnum);
convert_typed_floating (val, type, regval,
regtype);
regcache_cooked_write (regcache,
(tdep->ppc_fp0_regnum
+ freg),
regval);
}
freg++;
}
else if (TYPE_LENGTH (type) == 16
&& (gdbarch_long_double_format (gdbarch)
== floatformats_ibm_long_double))
{
if (write_pass)
{
regcache_cooked_write (regcache,
(tdep->ppc_fp0_regnum
+ freg),
val);
if (freg <= 12)
regcache_cooked_write (regcache,
(tdep->ppc_fp0_regnum
+ freg + 1),
val + 8);
}
freg += 2;
}
}
}
/* Always consume parameter stack space. */
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
}
if (!write_pass)
{
/* Save the true region sizes ready for the second pass. */
vparam_size = vparam;
/* Make certain that the general parameter save area is at
least the minimum 8 registers (or doublewords) in size. */
if (greg < 8)
gparam_size = 8 * tdep->wordsize;
else
gparam_size = gparam;
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, byte_order, back_chain);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
/* Use the func_addr to find the descriptor, and use that to find
the TOC. If we're calling via a function pointer, the pointer
itself identifies the descriptor. */
{
struct type *ftype = check_typedef (value_type (function));
CORE_ADDR desc_addr = value_as_address (function);
if (TYPE_CODE (ftype) == TYPE_CODE_PTR
|| convert_code_addr_to_desc_addr (func_addr, &desc_addr))
{
/* The TOC is the second double word in the descriptor. */
CORE_ADDR toc =
read_memory_unsigned_integer (desc_addr + tdep->wordsize,
tdep->wordsize, byte_order);
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum + 2, toc);
}
}
return sp;
}
CORE_ADDR
ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
const CORE_ADDR saved_sp = read_sp ();
int argspace = 0; /* 0 is an initial wrong guess. */
int write_pass;
/* Go through the argument list twice.
Pass 1: Figure out how much new stack space is required for
arguments and pushed values. Unlike the PowerOpen ABI, the SysV
ABI doesn't reserve any extra space for parameters which are put
in registers, but does always push structures and then pass their
address.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-float, non-vector
arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* Arguments start above the "LR save word" and "Back chain". */
int argoffset = 2 * tdep->wordsize;
/* Structures start after the arguments. */
int structoffset = argoffset + argspace;
/* If the function is returning a `struct', then the first word
(which will be passed in r3) is used for struct return
address. In that case we should advance one word and start
from r4 register to copy parameters. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (VALUE_TYPE (arg));
int len = TYPE_LENGTH (type);
char *val = VALUE_CONTENTS (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT
&& ppc_floating_point_unit_p (current_gdbarch) && len <= 8)
{
/* Floating point value converted to "double" then
passed in an FP register, when the registers run out,
8 byte aligned stack is used. */
if (freg <= 8)
{
if (write_pass)
{
/* Always store the floating point value using
the register's floating-point format. */
char regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum + freg);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
freg++;
}
else
{
/* SysV ABI converts floats to doubles before
writing them to an 8 byte aligned stack location. */
argoffset = align_up (argoffset, 8);
if (write_pass)
{
char memval[8];
struct type *memtype;
switch (TARGET_BYTE_ORDER)
{
case BFD_ENDIAN_BIG:
memtype = builtin_type_ieee_double_big;
break;
case BFD_ENDIAN_LITTLE:
memtype = builtin_type_ieee_double_little;
break;
default:
internal_error (__FILE__, __LINE__, "bad switch");
}
convert_typed_floating (val, type, memval, memtype);
write_memory (sp + argoffset, val, len);
}
argoffset += 8;
}
}
else if (len == 8 && (TYPE_CODE (type) == TYPE_CODE_INT /* long long */
|| (!ppc_floating_point_unit_p (current_gdbarch) && TYPE_CODE (type) == TYPE_CODE_FLT))) /* double */
{
/* "long long" or "double" passed in an odd/even
register pair with the low addressed word in the odd
register and the high addressed word in the even
register, or when the registers run out an 8 byte
aligned stack location. */
if (greg > 9)
{
/* Just in case GREG was 10. */
greg = 11;
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += 8;
}
else if (tdep->wordsize == 8)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg, val);
greg += 1;
}
else
{
/* Must start on an odd register - r3/r4 etc. */
if ((greg & 1) == 0)
greg++;
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 0,
val + 0);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 1,
val + 4);
}
greg += 2;
}
}
else if (len == 16
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type) && tdep->ppc_vr0_regnum >= 0)
{
/* Vector parameter passed in an Altivec register, or
when that runs out, 16 byte aligned stack location. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (current_regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
argoffset = align_up (argoffset, 16);
if (write_pass)
write_memory (sp + argoffset, val, 16);
argoffset += 16;
}
}
else if (len == 8
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type) && tdep->ppc_ev0_regnum >= 0)
{
/* Vector parameter passed in an e500 register, or when
that runs out, 8 byte aligned stack location. Note
that since e500 vector and general purpose registers
both map onto the same underlying register set, a
"greg" and not a "vreg" is consumed here. A cooked
write stores the value in the correct locations
within the raw register cache. */
if (greg <= 10)
{
if (write_pass)
regcache_cooked_write (current_regcache,
tdep->ppc_ev0_regnum + greg, val);
greg++;
}
else
{
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, 8);
argoffset += 8;
}
}
else
{
/* Reduce the parameter down to something that fits in a
"word". */
char word[MAX_REGISTER_SIZE];
memset (word, 0, MAX_REGISTER_SIZE);
if (len > tdep->wordsize
|| TYPE_CODE (type) == TYPE_CODE_STRUCT
|| TYPE_CODE (type) == TYPE_CODE_UNION)
{
/* Structs and large values are put on an 8 byte
aligned stack ... */
structoffset = align_up (structoffset, 8);
if (write_pass)
write_memory (sp + structoffset, val, len);
/* ... and then a "word" pointing to that address is
passed as the parameter. */
store_unsigned_integer (word, tdep->wordsize,
sp + structoffset);
structoffset += len;
}
else if (TYPE_CODE (type) == TYPE_CODE_INT)
/* Sign or zero extend the "int" into a "word". */
store_unsigned_integer (word, tdep->wordsize,
unpack_long (type, val));
else
/* Always goes in the low address. */
memcpy (word, val, len);
/* Store that "word" in a register, or on the stack.
The words have "4" byte alignment. */
if (greg <= 10)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg, word);
greg++;
}
else
{
argoffset = align_up (argoffset, tdep->wordsize);
if (write_pass)
write_memory (sp + argoffset, word, tdep->wordsize);
argoffset += tdep->wordsize;
}
}
}
/* Compute the actual stack space requirements. */
if (!write_pass)
{
/* Remember the amount of space needed by the arguments. */
argspace = argoffset;
/* Allocate space for both the arguments and the structures. */
sp -= (argoffset + structoffset);
/* Ensure that the stack is still 16 byte aligned. */
sp = align_down (sp, 16);
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, saved_sp);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
return sp;
}
