void VM_Version::initialize() {
  ResourceMark rm;

  // Create the processor info stub
  BufferBlob* blob = BufferBlob::create("getPsrInfo stub", 160);
  if (blob == NULL) {
    vm_exit_during_initialization("Unable to allocate getPsrInfo stub");
  }
  CodeBuffer* buffer = new CodeBuffer(blob->instructions_begin(),
                                      blob->instructions_size());
  VM_Version_StubGenerator g(buffer);
  getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, g.generate_getPsrInfo());

  // Get raw processor info
  getPsrInfo_stub(&_cpuid_info);

  // We know 64-bit x86's support cmpxchg8
  _supports_cx8 = true;

  // Prefetch settings
  PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
  PrefetchCopyIntervalInBytes = prefetch_scan_interval_in_bytes();
  PrefetchFieldsAhead         = prefetch_fields_ahead();
}
void VM_Version::initialize() {
  _features = determine_features();
  PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
  PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
  PrefetchFieldsAhead         = prefetch_fields_ahead();

  assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
  if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
  if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;

  // Allocation prefetch settings
  intx cache_line_size = prefetch_data_size();
  if( cache_line_size > AllocatePrefetchStepSize )
    AllocatePrefetchStepSize = cache_line_size;

  assert(AllocatePrefetchLines > 0, "invalid value");
  if( AllocatePrefetchLines < 1 )     // set valid value in product VM
    AllocatePrefetchLines = 3;
  assert(AllocateInstancePrefetchLines > 0, "invalid value");
  if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
    AllocateInstancePrefetchLines = 1;

  AllocatePrefetchDistance = allocate_prefetch_distance();
  AllocatePrefetchStyle    = allocate_prefetch_style();

  assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
         (AllocatePrefetchDistance > 0), "invalid value");
  if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
      (AllocatePrefetchDistance <= 0)) {
    AllocatePrefetchDistance = AllocatePrefetchStepSize;
  }

  if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
    warning("BIS instructions are not available on this CPU");
    FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
  }

  guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");

  assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
  if (ArraycopySrcPrefetchDistance >= 4096)
    ArraycopySrcPrefetchDistance = 4064;
  assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
  if (ArraycopyDstPrefetchDistance >= 4096)
    ArraycopyDstPrefetchDistance = 4064;

  UseSSE = 0; // Only on x86 and x64

  _supports_cx8 = has_v9();
  _supports_atomic_getset4 = true; // swap instruction

  // There are Fujitsu Sparc64 CPUs which support blk_init as well so
  // we have to take this check out of the 'is_niagara()' block below.
  if (has_blk_init()) {
    // When using CMS or G1, we cannot use memset() in BOT updates
    // because the sun4v/CMT version in libc_psr uses BIS which
    // exposes "phantom zeros" to concurrent readers. See 6948537.
    if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
      FLAG_SET_DEFAULT(UseMemSetInBOT, false);
    }
    // Issue a stern warning if the user has explicitly set
    // UseMemSetInBOT (it is known to cause issues), but allow
    // use for experimentation and debugging.
    if (UseConcMarkSweepGC || UseG1GC) {
      if (UseMemSetInBOT) {
        assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
        warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
                " on sun4v; please understand that you are using at your own risk!");
      }
    }
  }

  if (is_niagara()) {
    // Indirect branch is the same cost as direct
    if (FLAG_IS_DEFAULT(UseInlineCaches)) {
      FLAG_SET_DEFAULT(UseInlineCaches, false);
    }
    // Align loops on a single instruction boundary.
    if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
      FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
    }
#ifdef _LP64
    // 32-bit oops don't make sense for the 64-bit VM on sparc
    // since the 32-bit VM has the same registers and smaller objects.
    Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
    Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
#endif // _LP64
#ifdef COMPILER2
    // Indirect branch is the same cost as direct
    if (FLAG_IS_DEFAULT(UseJumpTables)) {
      FLAG_SET_DEFAULT(UseJumpTables, true);
    }
    // Single-issue, so entry and loop tops are
    // aligned on a single instruction boundary
    if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
      FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
    }
    if (is_niagara_plus()) {
      if (has_blk_init() && UseTLAB &&
          FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
        // Use BIS instruction for TLAB allocation prefetch.
        FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
        if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
          FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
        }
        if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
          // Use smaller prefetch distance with BIS
          FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
        }
      }
      if (is_T4()) {
        // Double number of prefetched cache lines on T4
        // since L2 cache line size is smaller (32 bytes).
        if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
          FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
        }
        if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
          FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
        }
      }
      if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
        // Use different prefetch distance without BIS
        FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
      }
      if (AllocatePrefetchInstr == 1) {
        // Need a space at the end of TLAB for BIS since it
        // will fault when accessing memory outside of heap.

        // +1 for rounding up to next cache line, +1 to be safe
        int lines = AllocatePrefetchLines + 2;
        int step_size = AllocatePrefetchStepSize;
        int distance = AllocatePrefetchDistance;
        _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
      }
    }
#endif
  }

  // Use hardware population count instruction if available.
  if (has_hardware_popc()) {
    if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
      FLAG_SET_DEFAULT(UsePopCountInstruction, true);
    }
  } else if (UsePopCountInstruction) {
    warning("POPC instruction is not available on this CPU");
    FLAG_SET_DEFAULT(UsePopCountInstruction, false);
  }

  // T4 and newer Sparc cpus have new compare and branch instruction.
  if (has_cbcond()) {
    if (FLAG_IS_DEFAULT(UseCBCond)) {
      FLAG_SET_DEFAULT(UseCBCond, true);
    }
  } else if (UseCBCond) {
    warning("CBCOND instruction is not available on this CPU");
    FLAG_SET_DEFAULT(UseCBCond, false);
  }

  assert(BlockZeroingLowLimit > 0, "invalid value");
  if (has_block_zeroing()) {
    if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
      FLAG_SET_DEFAULT(UseBlockZeroing, true);
    }
  } else if (UseBlockZeroing) {
    warning("BIS zeroing instructions are not available on this CPU");
    FLAG_SET_DEFAULT(UseBlockZeroing, false);
  }

  assert(BlockCopyLowLimit > 0, "invalid value");
  if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache
    if (FLAG_IS_DEFAULT(UseBlockCopy)) {
      FLAG_SET_DEFAULT(UseBlockCopy, true);
    }
  } else if (UseBlockCopy) {
    warning("BIS instructions are not available or expensive on this CPU");
    FLAG_SET_DEFAULT(UseBlockCopy, false);
  }

#ifdef COMPILER2
  // T4 and newer Sparc cpus have fast RDPC.
  if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
    FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
  }

  // Currently not supported anywhere.
  FLAG_SET_DEFAULT(UseFPUForSpilling, false);

  MaxVectorSize = 8;

  assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
#endif

  assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
  assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");

  char buf[512];
  jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
               (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
               (has_hardware_popc() ? ", popc" : ""),
               (has_vis1() ? ", vis1" : ""),
               (has_vis2() ? ", vis2" : ""),
               (has_vis3() ? ", vis3" : ""),
               (has_blk_init() ? ", blk_init" : ""),
               (has_cbcond() ? ", cbcond" : ""),
               (has_aes() ? ", aes" : ""),
               (is_ultra3() ? ", ultra3" : ""),
               (is_sun4v() ? ", sun4v" : ""),
               (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
               (is_sparc64() ? ", sparc64" : ""),
               (!has_hardware_mul32() ? ", no-mul32" : ""),
               (!has_hardware_div32() ? ", no-div32" : ""),
               (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));

  // buf is started with ", " or is empty
  _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);

  // UseVIS is set to the smallest of what hardware supports and what
  // the command line requires.  I.e., you cannot set UseVIS to 3 on
  // older UltraSparc which do not support it.
  if (UseVIS > 3) UseVIS=3;
  if (UseVIS < 0) UseVIS=0;
  if (!has_vis3()) // Drop to 2 if no VIS3 support
    UseVIS = MIN2((intx)2,UseVIS);
  if (!has_vis2()) // Drop to 1 if no VIS2 support
    UseVIS = MIN2((intx)1,UseVIS);
  if (!has_vis1()) // Drop to 0 if no VIS1 support
    UseVIS = 0;

  // T2 and above should have support for AES instructions
  if (has_aes()) {
    if (UseVIS > 0) { // AES intrinsics use FXOR instruction which is VIS1
      if (FLAG_IS_DEFAULT(UseAES)) {
        FLAG_SET_DEFAULT(UseAES, true);
      }
      if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
        FLAG_SET_DEFAULT(UseAESIntrinsics, true);
      }
      // we disable both the AES flags if either of them is disabled on the command line
      if (!UseAES || !UseAESIntrinsics) {
        FLAG_SET_DEFAULT(UseAES, false);
        FLAG_SET_DEFAULT(UseAESIntrinsics, false);
      }
    } else {
        if (UseAES || UseAESIntrinsics) {
          warning("SPARC AES intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
          if (UseAES) {
            FLAG_SET_DEFAULT(UseAES, false);
          }
          if (UseAESIntrinsics) {
            FLAG_SET_DEFAULT(UseAESIntrinsics, false);
          }
        }
    }
  } else if (UseAES || UseAESIntrinsics) {
    warning("AES instructions are not available on this CPU");
    if (UseAES) {
      FLAG_SET_DEFAULT(UseAES, false);
    }
    if (UseAESIntrinsics) {
      FLAG_SET_DEFAULT(UseAESIntrinsics, false);
    }
  }

  if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
    (cache_line_size > ContendedPaddingWidth))
    ContendedPaddingWidth = cache_line_size;

#ifndef PRODUCT
  if (PrintMiscellaneous && Verbose) {
    tty->print("Allocation");
    if (AllocatePrefetchStyle <= 0) {
      tty->print_cr(": no prefetching");
    } else {
      tty->print(" prefetching: ");
      if (AllocatePrefetchInstr == 0) {
          tty->print("PREFETCH");
      } else if (AllocatePrefetchInstr == 1) {
          tty->print("BIS");
      }
      if (AllocatePrefetchLines > 1) {
        tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
      } else {
        tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
      }
    }
    if (PrefetchCopyIntervalInBytes > 0) {
      tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
    }
    if (PrefetchScanIntervalInBytes > 0) {
      tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
    }
    if (PrefetchFieldsAhead > 0) {
      tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
    }
    if (ContendedPaddingWidth > 0) {
      tty->print_cr("ContendedPaddingWidth %d", ContendedPaddingWidth);
    }
  }
#endif // PRODUCT
}
Exemplo n.º 3
0
void VM_Version::initialize() {
  _features = determine_features();
  PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
  PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
  PrefetchFieldsAhead         = prefetch_fields_ahead();

  // Allocation prefetch settings
  intx cache_line_size = L1_data_cache_line_size();
  if( cache_line_size > AllocatePrefetchStepSize )
    AllocatePrefetchStepSize = cache_line_size;
  if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
    AllocatePrefetchLines = 3; // Optimistic value
  assert( AllocatePrefetchLines > 0, "invalid value");
  if( AllocatePrefetchLines < 1 ) // set valid value in product VM
    AllocatePrefetchLines = 1; // Conservative value

  AllocatePrefetchDistance = allocate_prefetch_distance();
  AllocatePrefetchStyle    = allocate_prefetch_style();

  assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");

  UseSSE = 0; // Only on x86 and x64

  _supports_cx8               = has_v9();

  if (is_niagara1()) {
    // Indirect branch is the same cost as direct
    if (FLAG_IS_DEFAULT(UseInlineCaches)) {
      FLAG_SET_DEFAULT(UseInlineCaches, false);
    }
#ifdef _LP64
    // Single issue niagara1 is slower for CompressedOops
    // but niagaras after that it's fine.
    if (!is_niagara1_plus()) {
      if (FLAG_IS_DEFAULT(UseCompressedOops)) {
        FLAG_SET_ERGO(bool, UseCompressedOops, false);
      }
    }
    // 32-bit oops don't make sense for the 64-bit VM on sparc
    // since the 32-bit VM has the same registers and smaller objects.
    Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
#endif // _LP64
#ifdef COMPILER2
    // Indirect branch is the same cost as direct
    if (FLAG_IS_DEFAULT(UseJumpTables)) {
      FLAG_SET_DEFAULT(UseJumpTables, true);
    }
    // Single-issue, so entry and loop tops are
    // aligned on a single instruction boundary
    if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
      FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
    }
    if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
      FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
    }
    if (is_niagara1_plus() && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
      // Use smaller prefetch distance on N2
      FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
    }
#endif
  }

  // Use hardware population count instruction if available.
  if (has_hardware_popc()) {
    if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
      FLAG_SET_DEFAULT(UsePopCountInstruction, true);
    }
  }

  char buf[512];
  jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s",
               (has_v8() ? ", has_v8" : ""),
               (has_v9() ? ", has_v9" : ""),
               (has_hardware_popc() ? ", popc" : ""),
               (has_vis1() ? ", has_vis1" : ""),
               (has_vis2() ? ", has_vis2" : ""),
               (is_ultra3() ? ", is_ultra3" : ""),
               (is_sun4v() ? ", is_sun4v" : ""),
               (is_niagara1() ? ", is_niagara1" : ""),
               (is_niagara1_plus() ? ", is_niagara1_plus" : ""),
               (!has_hardware_mul32() ? ", no-mul32" : ""),
               (!has_hardware_div32() ? ", no-div32" : ""),
               (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));

  // buf is started with ", " or is empty
  _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);

#ifndef PRODUCT
  if (PrintMiscellaneous && Verbose) {
    tty->print("Allocation: ");
    if (AllocatePrefetchStyle <= 0) {
      tty->print_cr("no prefetching");
    } else {
      if (AllocatePrefetchLines > 1) {
        tty->print_cr("PREFETCH %d, %d lines of size %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
      } else {
        tty->print_cr("PREFETCH %d, one line", AllocatePrefetchDistance);
      }
    }
    if (PrefetchCopyIntervalInBytes > 0) {
      tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
    }
    if (PrefetchScanIntervalInBytes > 0) {
      tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
    }
    if (PrefetchFieldsAhead > 0) {
      tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
    }
  }
#endif // PRODUCT
}
Exemplo n.º 4
0
void VM_Version::initialize() {
  _features = determine_features();
  PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
  PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
  PrefetchFieldsAhead         = prefetch_fields_ahead();

  // Allocation prefetch settings
  intx cache_line_size = prefetch_data_size();
  if( cache_line_size > AllocatePrefetchStepSize )
    AllocatePrefetchStepSize = cache_line_size;

  assert(AllocatePrefetchLines > 0, "invalid value");
  if( AllocatePrefetchLines < 1 )     // set valid value in product VM
    AllocatePrefetchLines = 3;
  assert(AllocateInstancePrefetchLines > 0, "invalid value");
  if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
    AllocateInstancePrefetchLines = 1;

  AllocatePrefetchDistance = allocate_prefetch_distance();
  AllocatePrefetchStyle    = allocate_prefetch_style();

  if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
    warning("BIS instructions are not available on this CPU");
    FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
  }

  guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");

  UseSSE = 0; // Only on x86 and x64

  _supports_cx8 = has_v9();
  _supports_atomic_getset4 = true; // swap instruction

  if (is_niagara()) {
    // Indirect branch is the same cost as direct
    if (FLAG_IS_DEFAULT(UseInlineCaches)) {
      FLAG_SET_DEFAULT(UseInlineCaches, false);
    }
    // Align loops on a single instruction boundary.
    if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
      FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
    }
#ifdef _LP64
    // 32-bit oops don't make sense for the 64-bit VM on sparc
    // since the 32-bit VM has the same registers and smaller objects.
    Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
    Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
#endif // _LP64
#ifdef COMPILER2
    // Indirect branch is the same cost as direct
    if (FLAG_IS_DEFAULT(UseJumpTables)) {
      FLAG_SET_DEFAULT(UseJumpTables, true);
    }
    // Single-issue, so entry and loop tops are
    // aligned on a single instruction boundary
    if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
      FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
    }
    if (is_niagara_plus()) {
      if (has_blk_init() && UseTLAB &&
          FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
        // Use BIS instruction for TLAB allocation prefetch.
        FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
        if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
          FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
        }
        if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
          // Use smaller prefetch distance with BIS
          FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
        }
      }
      if (is_T4()) {
        // Double number of prefetched cache lines on T4
        // since L2 cache line size is smaller (32 bytes).
        if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
          FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
        }
        if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
          FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
        }
      }
      if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
        // Use different prefetch distance without BIS
        FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
      }
      if (AllocatePrefetchInstr == 1) {
        // Need a space at the end of TLAB for BIS since it
        // will fault when accessing memory outside of heap.

        // +1 for rounding up to next cache line, +1 to be safe
        int lines = AllocatePrefetchLines + 2;
        int step_size = AllocatePrefetchStepSize;
        int distance = AllocatePrefetchDistance;
        _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
      }
    }
#endif
  }

  // Use hardware population count instruction if available.
  if (has_hardware_popc()) {
    if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
      FLAG_SET_DEFAULT(UsePopCountInstruction, true);
    }
  } else if (UsePopCountInstruction) {
    warning("POPC instruction is not available on this CPU");
    FLAG_SET_DEFAULT(UsePopCountInstruction, false);
  }

  // T4 and newer Sparc cpus have new compare and branch instruction.
  if (has_cbcond()) {
    if (FLAG_IS_DEFAULT(UseCBCond)) {
      FLAG_SET_DEFAULT(UseCBCond, true);
    }
  } else if (UseCBCond) {
    warning("CBCOND instruction is not available on this CPU");
    FLAG_SET_DEFAULT(UseCBCond, false);
  }

  assert(BlockZeroingLowLimit > 0, "invalid value");
  if (has_block_zeroing() && cache_line_size > 0) {
    if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
      FLAG_SET_DEFAULT(UseBlockZeroing, true);
    }
  } else if (UseBlockZeroing) {
    warning("BIS zeroing instructions are not available on this CPU");
    FLAG_SET_DEFAULT(UseBlockZeroing, false);
  }

  assert(BlockCopyLowLimit > 0, "invalid value");
  if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
    if (FLAG_IS_DEFAULT(UseBlockCopy)) {
      FLAG_SET_DEFAULT(UseBlockCopy, true);
    }
  } else if (UseBlockCopy) {
    warning("BIS instructions are not available or expensive on this CPU");
    FLAG_SET_DEFAULT(UseBlockCopy, false);
  }

#ifdef COMPILER2
  // T4 and newer Sparc cpus have fast RDPC.
  if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
    FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
  }

  // Currently not supported anywhere.
  FLAG_SET_DEFAULT(UseFPUForSpilling, false);

  MaxVectorSize = 8;

  assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
#endif

  assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
  assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");

  char buf[512];
  jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
               (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
               (has_hardware_popc() ? ", popc" : ""),
               (has_vis1() ? ", vis1" : ""),
               (has_vis2() ? ", vis2" : ""),
               (has_vis3() ? ", vis3" : ""),
               (has_blk_init() ? ", blk_init" : ""),
               (has_cbcond() ? ", cbcond" : ""),
               (has_aes() ? ", aes" : ""),
               (has_sha1() ? ", sha1" : ""),
               (has_sha256() ? ", sha256" : ""),
               (has_sha512() ? ", sha512" : ""),
               (has_crc32c() ? ", crc32c" : ""),
               (is_ultra3() ? ", ultra3" : ""),
               (is_sun4v() ? ", sun4v" : ""),
               (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
               (is_sparc64() ? ", sparc64" : ""),
               (!has_hardware_mul32() ? ", no-mul32" : ""),
               (!has_hardware_div32() ? ", no-div32" : ""),
               (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));

  // buf is started with ", " or is empty
  _features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);

  // UseVIS is set to the smallest of what hardware supports and what
  // the command line requires.  I.e., you cannot set UseVIS to 3 on
  // older UltraSparc which do not support it.
  if (UseVIS > 3) UseVIS=3;
  if (UseVIS < 0) UseVIS=0;
  if (!has_vis3()) // Drop to 2 if no VIS3 support
    UseVIS = MIN2((intx)2,UseVIS);
  if (!has_vis2()) // Drop to 1 if no VIS2 support
    UseVIS = MIN2((intx)1,UseVIS);
  if (!has_vis1()) // Drop to 0 if no VIS1 support
    UseVIS = 0;

  // SPARC T4 and above should have support for AES instructions
  if (has_aes()) {
    if (FLAG_IS_DEFAULT(UseAES)) {
      FLAG_SET_DEFAULT(UseAES, true);
    }
    if (!UseAES) {
      if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
        warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
      }
      FLAG_SET_DEFAULT(UseAESIntrinsics, false);
    } else {
      // The AES intrinsic stubs require AES instruction support (of course)
      // but also require VIS3 mode or higher for instructions it use.
      if (UseVIS > 2) {
        if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
          FLAG_SET_DEFAULT(UseAESIntrinsics, true);
        }
      } else {
        if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
          warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
        }
        FLAG_SET_DEFAULT(UseAESIntrinsics, false);
      }
    }
  } else if (UseAES || UseAESIntrinsics) {
    if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
      warning("AES instructions are not available on this CPU");
      FLAG_SET_DEFAULT(UseAES, false);
    }
    if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
      warning("AES intrinsics are not available on this CPU");
      FLAG_SET_DEFAULT(UseAESIntrinsics, false);
    }
  }

  // GHASH/GCM intrinsics
  if (has_vis3() && (UseVIS > 2)) {
    if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
      UseGHASHIntrinsics = true;
    }
  } else if (UseGHASHIntrinsics) {
    if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
      warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
    FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
  }

  // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
  if (has_sha1() || has_sha256() || has_sha512()) {
    if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
      if (FLAG_IS_DEFAULT(UseSHA)) {
        FLAG_SET_DEFAULT(UseSHA, true);
      }
    } else {
      if (UseSHA) {
        warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
        FLAG_SET_DEFAULT(UseSHA, false);
      }
    }
  } else if (UseSHA) {
    warning("SHA instructions are not available on this CPU");
    FLAG_SET_DEFAULT(UseSHA, false);
  }

  if (UseSHA && has_sha1()) {
    if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
      FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
    }
  } else if (UseSHA1Intrinsics) {
    warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
    FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
  }

  if (UseSHA && has_sha256()) {
    if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
      FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
    }
  } else if (UseSHA256Intrinsics) {
    warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
    FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
  }

  if (UseSHA && has_sha512()) {
    if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
      FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
    }
  } else if (UseSHA512Intrinsics) {
    warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
    FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
  }

  if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
    FLAG_SET_DEFAULT(UseSHA, false);
  }

  // SPARC T4 and above should have support for CRC32C instruction
  if (has_crc32c()) {
    if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
      if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
        FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
      }
    } else {
      if (UseCRC32CIntrinsics) {
        warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
        FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
      }
    }
  } else if (UseCRC32CIntrinsics) {
    warning("CRC32C instruction is not available on this CPU");
    FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
  }

  if (UseVIS > 2) {
    if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
      FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
    }
  } else if (UseAdler32Intrinsics) {
    warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
    FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
  }

  if (UseVIS > 2) {
    if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
      FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
    }
  } else if (UseCRC32Intrinsics) {
    warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled");
    FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
  }

  if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
    (cache_line_size > ContendedPaddingWidth))
    ContendedPaddingWidth = cache_line_size;

  // This machine does not allow unaligned memory accesses
  if (UseUnalignedAccesses) {
    if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
      warning("Unaligned memory access is not available on this CPU");
    FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
  }

  if (PrintMiscellaneous && Verbose) {
    tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
    tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
    tty->print("Allocation");
    if (AllocatePrefetchStyle <= 0) {
      tty->print_cr(": no prefetching");
    } else {
      tty->print(" prefetching: ");
      if (AllocatePrefetchInstr == 0) {
          tty->print("PREFETCH");
      } else if (AllocatePrefetchInstr == 1) {
          tty->print("BIS");
      }
      if (AllocatePrefetchLines > 1) {
        tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
      } else {
        tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
      }
    }
    if (PrefetchCopyIntervalInBytes > 0) {
      tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
    }
    if (PrefetchScanIntervalInBytes > 0) {
      tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
    }
    if (PrefetchFieldsAhead > 0) {
      tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
    }
    if (ContendedPaddingWidth > 0) {
      tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
    }
  }
}
Exemplo n.º 5
0
void VM_Version::get_processor_features() {

    _cpu = 4; // 486 by default
    _model = 0;
    _stepping = 0;
    _cpuFeatures = 0;
    _logical_processors_per_package = 1;

    if (!Use486InstrsOnly) {
        // Get raw processor info
        getPsrInfo_stub(&_cpuid_info);
        assert_is_initialized();
        _cpu = extended_cpu_family();
        _model = extended_cpu_model();
        _stepping = cpu_stepping();

        if (cpu_family() > 4) { // it supports CPUID
            _cpuFeatures = feature_flags();
            // Logical processors are only available on P4s and above,
            // and only if hyperthreading is available.
            _logical_processors_per_package = logical_processor_count();
        }
    }

    _supports_cx8 = supports_cmpxchg8();

#ifdef _LP64
    // OS should support SSE for x64 and hardware should support at least SSE2.
    if (!VM_Version::supports_sse2()) {
        vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
    }
    // in 64 bit the use of SSE2 is the minimum
    if (UseSSE < 2) UseSSE = 2;
#endif

#ifdef AMD64
    // flush_icache_stub have to be generated first.
    // That is why Icache line size is hard coded in ICache class,
    // see icache_x86.hpp. It is also the reason why we can't use
    // clflush instruction in 32-bit VM since it could be running
    // on CPU which does not support it.
    //
    // The only thing we can do is to verify that flushed
    // ICache::line_size has correct value.
    guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
    // clflush_size is size in quadwords (8 bytes).
    guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
#endif

    // If the OS doesn't support SSE, we can't use this feature even if the HW does
    if (!os::supports_sse())
        _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);

    if (UseSSE < 4) {
        _cpuFeatures &= ~CPU_SSE4_1;
        _cpuFeatures &= ~CPU_SSE4_2;
    }

    if (UseSSE < 3) {
        _cpuFeatures &= ~CPU_SSE3;
        _cpuFeatures &= ~CPU_SSSE3;
        _cpuFeatures &= ~CPU_SSE4A;
    }

    if (UseSSE < 2)
        _cpuFeatures &= ~CPU_SSE2;

    if (UseSSE < 1)
        _cpuFeatures &= ~CPU_SSE;

    if (UseAVX < 2)
        _cpuFeatures &= ~CPU_AVX2;

    if (UseAVX < 1)
        _cpuFeatures &= ~CPU_AVX;

    if (logical_processors_per_package() == 1) {
        // HT processor could be installed on a system which doesn't support HT.
        _cpuFeatures &= ~CPU_HT;
    }

    char buf[256];
    jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
                 cores_per_cpu(), threads_per_core(),
                 cpu_family(), _model, _stepping,
                 (supports_cmov() ? ", cmov" : ""),
                 (supports_cmpxchg8() ? ", cx8" : ""),
                 (supports_fxsr() ? ", fxsr" : ""),
                 (supports_mmx()  ? ", mmx"  : ""),
                 (supports_sse()  ? ", sse"  : ""),
                 (supports_sse2() ? ", sse2" : ""),
                 (supports_sse3() ? ", sse3" : ""),
                 (supports_ssse3()? ", ssse3": ""),
                 (supports_sse4_1() ? ", sse4.1" : ""),
                 (supports_sse4_2() ? ", sse4.2" : ""),
                 (supports_popcnt() ? ", popcnt" : ""),
                 (supports_avx()    ? ", avx" : ""),
                 (supports_avx2()   ? ", avx2" : ""),
                 (supports_mmx_ext() ? ", mmxext" : ""),
                 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
                 (supports_lzcnt()   ? ", lzcnt": ""),
                 (supports_sse4a()   ? ", sse4a": ""),
                 (supports_ht() ? ", ht": ""),
                 (supports_tsc() ? ", tsc": ""),
                 (supports_tscinv_bit() ? ", tscinvbit": ""),
                 (supports_tscinv() ? ", tscinv": ""));
    _features_str = strdup(buf);

    // UseSSE is set to the smaller of what hardware supports and what
    // the command line requires.  I.e., you cannot set UseSSE to 2 on
    // older Pentiums which do not support it.
    if (UseSSE > 4) UseSSE=4;
    if (UseSSE < 0) UseSSE=0;
    if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
        UseSSE = MIN2((intx)3,UseSSE);
    if (!supports_sse3()) // Drop to 2 if no SSE3 support
        UseSSE = MIN2((intx)2,UseSSE);
    if (!supports_sse2()) // Drop to 1 if no SSE2 support
        UseSSE = MIN2((intx)1,UseSSE);
    if (!supports_sse ()) // Drop to 0 if no SSE  support
        UseSSE = 0;

    if (UseAVX > 2) UseAVX=2;
    if (UseAVX < 0) UseAVX=0;
    if (!supports_avx2()) // Drop to 1 if no AVX2 support
        UseAVX = MIN2((intx)1,UseAVX);
    if (!supports_avx ()) // Drop to 0 if no AVX  support
        UseAVX = 0;

    // On new cpus instructions which update whole XMM register should be used
    // to prevent partial register stall due to dependencies on high half.
    //
    // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
    // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
    // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
    // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).

    if( is_amd() ) { // AMD cpus specific settings
        if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
            // Use it on new AMD cpus starting from Opteron.
            UseAddressNop = true;
        }
        if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
            // Use it on new AMD cpus starting from Opteron.
            UseNewLongLShift = true;
        }
        if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
            if( supports_sse4a() ) {
                UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
            } else {
                UseXmmLoadAndClearUpper = false;
            }
        }
        if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
            if( supports_sse4a() ) {
                UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
            } else {
                UseXmmRegToRegMoveAll = false;
            }
        }
        if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
            if( supports_sse4a() ) {
                UseXmmI2F = true;
            } else {
                UseXmmI2F = false;
            }
        }
        if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
            if( supports_sse4a() ) {
                UseXmmI2D = true;
            } else {
                UseXmmI2D = false;
            }
        }
        if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
            if( supports_sse4_2() && UseSSE >= 4 ) {
                UseSSE42Intrinsics = true;
            }
        }

        // Use count leading zeros count instruction if available.
        if (supports_lzcnt()) {
            if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
                UseCountLeadingZerosInstruction = true;
            }
        }

        // some defaults for AMD family 15h
        if ( cpu_family() == 0x15 ) {
            // On family 15h processors default is no sw prefetch
            if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
                AllocatePrefetchStyle = 0;
            }
            // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
            if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
                AllocatePrefetchInstr = 3;
            }
            // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
            if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
                UseXMMForArrayCopy = true;
            }
            if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
                UseUnalignedLoadStores = true;
            }
        }

    }

    if( is_intel() ) { // Intel cpus specific settings
        if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
            UseStoreImmI16 = false; // don't use it on Intel cpus
        }
        if( cpu_family() == 6 || cpu_family() == 15 ) {
            if( FLAG_IS_DEFAULT(UseAddressNop) ) {
                // Use it on all Intel cpus starting from PentiumPro
                UseAddressNop = true;
            }
        }
        if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
            UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
        }
        if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
            if( supports_sse3() ) {
                UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
            } else {
                UseXmmRegToRegMoveAll = false;
            }
        }
        if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
#ifdef COMPILER2
            if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
                // For new Intel cpus do the next optimization:
                // don't align the beginning of a loop if there are enough instructions
                // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
                // in current fetch line (OptoLoopAlignment) or the padding
                // is big (> MaxLoopPad).
                // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
                // generated NOP instructions. 11 is the largest size of one
                // address NOP instruction '0F 1F' (see Assembler::nop(i)).
                MaxLoopPad = 11;
            }
#endif // COMPILER2
            if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
                UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
            }
            if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
                if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
                    UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
                }
            }
            if( supports_sse4_2() && UseSSE >= 4 ) {
                if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
                    UseSSE42Intrinsics = true;
                }
            }
        }
    }

    // Use population count instruction if available.
    if (supports_popcnt()) {
        if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
            UsePopCountInstruction = true;
        }
    } else if (UsePopCountInstruction) {
        warning("POPCNT instruction is not available on this CPU");
        FLAG_SET_DEFAULT(UsePopCountInstruction, false);
    }

#ifdef COMPILER2
    if (UseFPUForSpilling) {
        if (UseSSE < 2) {
            // Only supported with SSE2+
            FLAG_SET_DEFAULT(UseFPUForSpilling, false);
        }
    }
#endif

    assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
    assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");

    // set valid Prefetch instruction
    if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
    if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
    if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
    if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;

    if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
    if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
    if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
    if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;

    // Allocation prefetch settings
    intx cache_line_size = prefetch_data_size();
    if( cache_line_size > AllocatePrefetchStepSize )
        AllocatePrefetchStepSize = cache_line_size;

    assert(AllocatePrefetchLines > 0, "invalid value");
    if( AllocatePrefetchLines < 1 )     // set valid value in product VM
        AllocatePrefetchLines = 3;
    assert(AllocateInstancePrefetchLines > 0, "invalid value");
    if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
        AllocateInstancePrefetchLines = 1;

    AllocatePrefetchDistance = allocate_prefetch_distance();
    AllocatePrefetchStyle    = allocate_prefetch_style();

    if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
        if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
#ifdef _LP64
            AllocatePrefetchDistance = 384;
#else
            AllocatePrefetchDistance = 320;
#endif
        }
        if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
            AllocatePrefetchDistance = 192;
            AllocatePrefetchLines = 4;
#ifdef COMPILER2
            if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
                FLAG_SET_DEFAULT(UseFPUForSpilling, true);
            }
#endif
        }
    }
    assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");

#ifdef _LP64
    // Prefetch settings
    PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
    PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
    PrefetchFieldsAhead         = prefetch_fields_ahead();
#endif

#ifndef PRODUCT
    if (PrintMiscellaneous && Verbose) {
        tty->print_cr("Logical CPUs per core: %u",
                      logical_processors_per_package());
        tty->print("UseSSE=%d",UseSSE);
        if (UseAVX > 0) {
            tty->print("  UseAVX=%d",UseAVX);
        }
        tty->cr();
        tty->print("Allocation");
        if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
            tty->print_cr(": no prefetching");
        } else {
            tty->print(" prefetching: ");
            if (UseSSE == 0 && supports_3dnow_prefetch()) {
                tty->print("PREFETCHW");
            } else if (UseSSE >= 1) {
                if (AllocatePrefetchInstr == 0) {
                    tty->print("PREFETCHNTA");
                } else if (AllocatePrefetchInstr == 1) {
                    tty->print("PREFETCHT0");
                } else if (AllocatePrefetchInstr == 2) {
                    tty->print("PREFETCHT2");
                } else if (AllocatePrefetchInstr == 3) {
                    tty->print("PREFETCHW");
                }
            }
            if (AllocatePrefetchLines > 1) {
                tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
            } else {
                tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
            }
        }

        if (PrefetchCopyIntervalInBytes > 0) {
            tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
        }
        if (PrefetchScanIntervalInBytes > 0) {
            tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
        }
        if (PrefetchFieldsAhead > 0) {
            tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
        }
    }
#endif // !PRODUCT
}