int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
bd_t *bd = gd->bd;
print_num("boot_params", (ulong)bd->bi_boot_params);
print_num("bi_memstart", bd->bi_memstart);
print_num("bi_memsize", bd->bi_memsize);
print_num("bi_flashstart", bd->bi_flashstart);
print_num("bi_flashsize", bd->bi_flashsize);
print_num("bi_flashoffset", bd->bi_flashoffset);
print_num("bi_sramstart", bd->bi_sramstart);
print_num("bi_sramsize", bd->bi_sramsize);
print_num("bi_bootflags", bd->bi_bootflags);
print_mhz("cpufreq", bd->bi_intfreq);
print_mhz("busfreq", bd->bi_busfreq);
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
print_num("DRAM bank", i);
print_num("-> start", bd->bi_dram[i].start);
print_num("-> size", bd->bi_dram[i].size);
}
#if defined(CONFIG_CMD_NET)
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
void __init_or_cpufreq s3c2412_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long tmp;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
clk_mpll.rate = fclk;
tmp = __raw_readl(S3C2410_CLKDIVN);
hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
void __init_or_cpufreq s3c2443_setup_clocks(void)
{
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
struct clk *xtal_clk;
unsigned long xtal;
unsigned long pll;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
pll = s3c2443_get_mpll(mpllcon, xtal);
clk_msysclk.rate = pll;
fclk = pll / s3c2443_fclk_div(clkdiv0);
hclk = s3c2443_prediv_getrate(&clk_prediv);
hclk /= s3c2443_get_hdiv(clkdiv0);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
s3c24xx_setup_clocks(fclk, hclk, pclk);
printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(pll), print_mhz(fclk),
print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
void __init_or_cpufreq s3c2412_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long tmp;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
clk_mpll.rate = fclk;
tmp = __raw_readl(S3C2410_CLKDIVN);
/* work out clock scalings */
hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
/* print brieft summary of clocks, etc */
printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
void __init s3c2410_map_io(struct map_desc *mach_desc, int size)
{
unsigned long tmp;
/* register our io-tables */
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
iotable_init(mach_desc, size);
/* now we've got our machine bits initialised, work out what
* clocks we've got */
s3c2410_fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), 12*MHZ);
tmp = __raw_readl(S3C2410_CLKDIVN);
//printk("tmp=%08x, fclk=%d\n", tmp, s3c2410_fclk);
/* work out clock scalings */
s3c2410_hclk = s3c2410_fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
s3c2410_pclk = s3c2410_hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
/* print brieft summary of clocks, etc */
printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(s3c2410_fclk), print_mhz(s3c2410_hclk),
print_mhz(s3c2410_pclk));
}
void __init s3c2410_init_clocks(int xtal)
{
unsigned long tmp;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
tmp = __raw_readl(S3C2410_CLKDIVN);
/* work out clock scalings */
hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
/* print brieft summary of clocks, etc */
printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
/* initialise the clocks here, to allow other things like the
* console to use them
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c2410_baseclk_add();
}
void __init s3c2412_init_clocks(int xtal)
{
unsigned long clkdiv;
unsigned long hclk, fclk, pclk;
int hdiv = 1;
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
clkdiv = __raw_readl(S3C2410_CLKDIVN);
/* work out clock scalings */
switch (clkdiv & S3C2412_CLKDIVN_HCLKDIV_MASK) {
case S3C2412_CLKDIVN_HCLKDIV_1_2:
hdiv = 1;
break;
case S3C2412_CLKDIVN_HCLKDIV_2_4:
hdiv = 2;
break;
case S3C2412_CLKDIVN_HCLKDIV_3_6:
hdiv = 3;
break;
case S3C2412_CLKDIVN_HCLKDIV_4_8:
hdiv = 4;
break;
}
if (!(clkdiv & S3C2412_CLKDIVN_ARMDIV))
fclk *= 2;
hclk = fclk / hdiv;
pclk = hclk / ((clkdiv & S3C2412_CLKDIVN_PCLKDIV)? 2 : 1);
if (clkdiv & S3C2412_CLKDIVN_DVSEN)
fclk = hclk;
/* print brief summary of clocks, etc */
printk("S3C2412: core %lu.%03lu MHz, memory %lu.%03lu MHz, peripheral %lu.%03lu MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
/* initialise the clocks here, to allow other things like the
* console to use them, and to add new ones after the initialisation
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
#if defined CONFIG_CPU_FREQ && defined CONFIG_S3C24XX_DFS_CPUFREQ
/* Setup the uartclk. Needs to be done this early so the console can use it. */
s3c2412_setup_uart_clk( xtal );
#endif
}
void __init s3c244x_init_clocks(int xtal)
{
unsigned long clkdiv;
unsigned long camdiv;
unsigned long hclk, fclk, pclk;
int hdiv = 1;
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
clkdiv = __raw_readl(S3C2410_CLKDIVN);
camdiv = __raw_readl(S3C2440_CAMDIVN);
/* work out clock scalings */
switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
case S3C2440_CLKDIVN_HDIVN_1:
hdiv = 1;
break;
case S3C2440_CLKDIVN_HDIVN_2:
hdiv = 2;
break;
case S3C2440_CLKDIVN_HDIVN_4_8:
hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
break;
case S3C2440_CLKDIVN_HDIVN_3_6:
hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
break;
}
hclk = fclk / hdiv;
pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
/* print brief summary of clocks, etc */
printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
/* initialise the clocks here, to allow other things like the
* console to use them, and to add new ones after the initialisation
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c2410_baseclk_add();
}
void __init_or_cpufreq s3c244x_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long clkdiv;
unsigned long camdiv;
unsigned long xtal;
unsigned long hclk, fclk, pclk;
int hdiv = 1;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
clkdiv = __raw_readl(S3C2410_CLKDIVN);
camdiv = __raw_readl(S3C2440_CAMDIVN);
/* work out clock scalings */
switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
case S3C2440_CLKDIVN_HDIVN_1:
hdiv = 1;
break;
case S3C2440_CLKDIVN_HDIVN_2:
hdiv = 2;
break;
case S3C2440_CLKDIVN_HDIVN_4_8:
hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
break;
case S3C2440_CLKDIVN_HDIVN_3_6:
hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
break;
}
hclk = fclk / hdiv;
pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
/* print brief summary of clocks, etc */
printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
int __init s3c2410_baseclk_add(void)
{
unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
struct clk *xtal;
int ret;
int ptr;
clk_upll.enable = s3c2410_upll_enable;
if (s3c24xx_register_clock(&clk_usb_bus) < 0)
printk(KERN_ERR "failed to register usb bus clock\n");
/* register clocks from clock array */
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
struct clk *clkp = init_clocks[ptr];
/* ensure that we note the clock state */
clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
/* We must be careful disabling the clocks we are not intending to
* be using at boot time, as subsystems such as the LCD which do
* their own DMA requests to the bus can cause the system to lockup
* if they where in the middle of requesting bus access.
*
* Disabling the LCD clock if the LCD is active is very dangerous,
* and therefore the bootloader should be careful to not enable
* the LCD clock if it is not needed.
*/
/* install (and disable) the clocks we do not need immediately */
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
/* show the clock-slow value */
xtal = clk_get(NULL, "xtal");
printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
print_mhz(clk_get_rate(xtal) /
( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
(clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
(clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
(clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
s3c_pwmclk_init();
return 0;
}
void __init_or_cpufreq s5p6440_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long hclk_low;
unsigned long pclk;
unsigned long pclk_low;
unsigned long apll;
unsigned long mpll;
unsigned long epll;
unsigned int ptr;
/* */
clk_fout_epll.enable = s5p_epll_enable;
clk_fout_epll.ops = &s5p6440_epll_ops;
clk_48m.enable = s5p64x0_clk48m_ctrl;
xtal_clk = clk_get(NULL, "ext_xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
__raw_readl(S5P64X0_EPLL_CON_K));
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
" E=%ld.%ldMHz\n",
print_mhz(apll), print_mhz(mpll), print_mhz(epll));
fclk = clk_get_rate(&clk_armclk.clk);
hclk = clk_get_rate(&clk_hclk.clk);
pclk = clk_get_rate(&clk_pclk.clk);
hclk_low = clk_get_rate(&clk_hclk_low.clk);
pclk_low = clk_get_rate(&clk_pclk_low.clk);
printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
print_mhz(hclk), print_mhz(hclk_low),
print_mhz(pclk), print_mhz(pclk_low));
clk_f.rate = fclk;
clk_h.rate = hclk;
clk_p.rate = pclk;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
}
void __init_or_cpufreq s5pc100_setup_clocks(void)
{
unsigned long xtal;
unsigned long arm;
unsigned long hclkd0;
unsigned long hclkd1;
unsigned long pclkd0;
unsigned long pclkd1;
unsigned long apll;
unsigned long mpll;
unsigned long epll;
unsigned long hpll;
unsigned int ptr;
/* Set S5PC100 functions for clk_fout_epll */
clk_fout_epll.enable = s5pc100_epll_enable;
clk_fout_epll.ops = &s5pc100_epll_ops;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
xtal = clk_get_rate(&clk_xtal);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_mout_hpll.clk.rate = hpll;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
arm = clk_get_rate(&clk_div_arm.clk);
hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
clk_f.rate = arm;
clk_h.rate = hclkd1;
clk_p.rate = pclkd1;
}
void
oki_fixup(struct machine_desc *mdesc,
struct param_struct *param,
char **arg,
struct meminfo *meminfo)
{
unsigned int bwc, tmp;
unsigned int clk;
/* need to determine which version of the cpu this is */
bwc = __raw_readl(OKI_BWC);
tmp = bwc & ~(3<<8); /* IO23BW */
if (tmp != bwc) {
printk("CPU is ML67400x series\n");
oki_ml67400x = 1;
oki_ml67500x = 0;
oki_clk = 25*1000*1000;
} else {
printk("CPU is ML67500x series\n");
oki_ml67400x = 0;
oki_ml67500x = 1;
oki_clk = 7372800*8;
oki_ml67500x_init_cache();
}
clk = __raw_readl(OKI_CGBCNT0);
oki_hclk = oki_clk / OKI_CLKGR_H(clk);
oki_cclk = oki_clk / OKI_CLKGR_C(clk);
#define print_mhz(x) ((x) / 1000000), (((x) / 1000) % 1000)
printk("OKI: Clk %d.%3d MHz, HClk %d.%3d MHz, CCLk %d.%3d MHz\n",
print_mhz(oki_clk), print_mhz(oki_hclk), print_mhz(oki_cclk));
}
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
print_bi_mem(bd);
print_bi_flash(bd);
#if defined(CONFIG_SYS_INIT_RAM_ADDR)
print_num("sramstart", (ulong)bd->bi_sramstart);
print_num("sramsize", (ulong)bd->bi_sramsize);
#endif
#if defined(CONFIG_SYS_MBAR)
print_num("mbar", bd->bi_mbar_base);
#endif
print_mhz("cpufreq", bd->bi_intfreq);
print_mhz("busfreq", bd->bi_busfreq);
#ifdef CONFIG_PCI
print_mhz("pcifreq", bd->bi_pcifreq);
#endif
#ifdef CONFIG_EXTRA_CLOCK
print_mhz("flbfreq", bd->bi_flbfreq);
print_mhz("inpfreq", bd->bi_inpfreq);
print_mhz("vcofreq", bd->bi_vcofreq);
#endif
print_eth_ip_addr();
print_baudrate();
return 0;
}
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
printf("U-Boot = %s\n", bd->bi_r_version);
printf("CPU = %s\n", bd->bi_cpu);
printf("Board = %s\n", bd->bi_board_name);
print_mhz("VCO", bd->bi_vco);
print_mhz("CCLK", bd->bi_cclk);
print_mhz("SCLK", bd->bi_sclk);
print_num("boot_params", (ulong)bd->bi_boot_params);
print_num("memstart", (ulong)bd->bi_memstart);
print_lnum("memsize", (u64)bd->bi_memsize);
print_num("flashstart", (ulong)bd->bi_flashstart);
print_num("flashsize", (ulong)bd->bi_flashsize);
print_num("flashoffset", (ulong)bd->bi_flashoffset);
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
static int s3c2440_clk_add(struct sys_device *sysdev)
{
struct clk *clk_xtal;
struct clk *clk_h;
struct clk *clk_p;
int i;
struct clk *clkp;
clk_xtal = clk_get(NULL, "xtal");
if (IS_ERR(clk_xtal)) {
printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");
return -EINVAL;
}
s3c2440_clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), clk_xtal->rate);
printk("S3C2440: Clock Support, UPLL %lu.%03lu MHz\n",
print_mhz(s3c2440_clk_upll.rate));
clk_h = clk_get(NULL, "hclk");
clk_p = clk_get(NULL, "pclk");
if (IS_ERR(clk_h) || IS_ERR(clk_p)) {
printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
return -EINVAL;
}
s3c24xx_register_clock(&s3c2440_clk_upll);
for (i = 0; i < ARRAY_SIZE(s3c2440_init_clocks); ++i) {
clkp = &s3c2440_init_clocks[i];
switch ((int)clkp->parent) {
case (int)CLK_H:
clkp->parent = clk_h;
break;
case (int)CLK_P:
clkp->parent = clk_p;
break;
default:
clkp->parent = NULL;
break;
}
s3c24xx_register_clock(clkp);
}
return 0;
}
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
print_bi_boot_params(bd);
print_bi_dram(bd);
print_num("relocaddr", gd->relocaddr);
print_num("reloc off", gd->reloc_off);
#if defined(CONFIG_CMD_NET)
print_eth_ip_addr();
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
print_baudrate();
return 0;
}
void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
fdiv_fn get_fdiv)
{
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
struct clk *xtal_clk;
unsigned long xtal;
unsigned long pll;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
int ptr;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
pll = get_mpll(mpllcon, xtal);
clk_msysclk.clk.rate = pll;
fclk = pll / get_fdiv(clkdiv0);
hclk = s3c2443_prediv_getrate(&clk_prediv);
hclk /= s3c2443_get_hdiv(clkdiv0);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
s3c24xx_setup_clocks(fclk, hclk, pclk);
printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(pll), print_mhz(fclk),
print_mhz(hclk), print_mhz(pclk));
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
s3c_set_clksrc(&clksrc_clks[ptr], true);
/* ensure usb bus clock is within correct rate of 48MHz */
if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
}
printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
(epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(clk_get_rate(&clk_epll)),
print_mhz(clk_get_rate(&clk_usb_bus)));
}
static int s3c64xx_setrate_sclk_cam(struct clk *clk, unsigned long rate)
{
u32 shift = 20;
u32 cam_div, cfg;
unsigned long src_clk = clk_get_rate(clk->parent);
cam_div = src_clk / rate;
if (cam_div > 32)
cam_div = 32;
cfg = __raw_readl(S3C_CLK_DIV0);
cfg &= ~(0xf << shift);
cfg |= ((cam_div - 1) << shift);
__raw_writel(cfg, S3C_CLK_DIV0);
printk("parent clock for camera: %ld.%03ld MHz, divisor: %d\n", \
print_mhz(src_clk), cam_div);
return 0;
}
static int s3c2440_clk_add(struct sys_device *sysdev)
{
unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
struct clk *clk_h;
struct clk *clk_p;
struct clk *clk_xtal;
clk_xtal = clk_get(NULL, "xtal");
if (IS_ERR(clk_xtal)) {
printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");
return -EINVAL;
}
s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n",
print_mhz(s3c2440_clk_upll.rate));
clk_p = clk_get(NULL, "pclk");
clk_h = clk_get(NULL, "hclk");
if (IS_ERR(clk_p) || IS_ERR(clk_h)) {
printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
return -EINVAL;
}
s3c2440_clk_cam.parent = clk_h;
s3c2440_clk_ac97.parent = clk_p;
s3c24xx_register_clock(&s3c2440_clk_ac97);
s3c24xx_register_clock(&s3c2440_clk_cam);
s3c24xx_register_clock(&s3c2440_clk_upll);
clk_disable(&s3c2440_clk_ac97);
clk_disable(&s3c2440_clk_cam);
return 0;
}
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
print_num("memstart", (ulong)bd->bi_memstart);
print_lnum("memsize", (u64)bd->bi_memsize);
print_num("flashstart", (ulong)bd->bi_flashstart);
print_num("flashsize", (ulong)bd->bi_flashsize);
print_num("flashoffset", (ulong)bd->bi_flashoffset);
#if defined(CONFIG_SYS_INIT_RAM_ADDR)
print_num("sramstart", (ulong)bd->bi_sramstart);
print_num("sramsize", (ulong)bd->bi_sramsize);
#endif
#if defined(CONFIG_SYS_MBAR)
print_num("mbar", bd->bi_mbar_base);
#endif
print_mhz("cpufreq", bd->bi_intfreq);
print_mhz("busfreq", bd->bi_busfreq);
#ifdef CONFIG_PCI
print_mhz("pcifreq", bd->bi_pcifreq);
#endif
#ifdef CONFIG_EXTRA_CLOCK
print_mhz("flbfreq", bd->bi_flbfreq);
print_mhz("inpfreq", bd->bi_inpfreq);
print_mhz("vcofreq", bd->bi_vcofreq);
#endif
#if defined(CONFIG_CMD_NET)
print_eth(0);
#if defined(CONFIG_HAS_ETH1)
print_eth(1);
#endif
#if defined(CONFIG_HAS_ETH2)
print_eth(2);
#endif
#if defined(CONFIG_HAS_ETH3)
print_eth(3);
#endif
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
#ifdef DEBUG
print_num("bd address", (ulong)bd);
#endif
print_bi_mem(bd);
print_bi_flash(bd);
print_num("sramstart", bd->bi_sramstart);
print_num("sramsize", bd->bi_sramsize);
#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
print_num("immr_base", bd->bi_immr_base);
#endif
print_num("bootflags", bd->bi_bootflags);
#if defined(CONFIG_CPM2)
print_mhz("vco", bd->bi_vco);
print_mhz("sccfreq", bd->bi_sccfreq);
print_mhz("brgfreq", bd->bi_brgfreq);
#endif
print_mhz("intfreq", bd->bi_intfreq);
#if defined(CONFIG_CPM2)
print_mhz("cpmfreq", bd->bi_cpmfreq);
#endif
print_mhz("busfreq", bd->bi_busfreq);
#ifdef CONFIG_ENABLE_36BIT_PHYS
#ifdef CONFIG_PHYS_64BIT
puts("addressing = 36-bit\n");
#else
puts("addressing = 32-bit\n");
#endif
#endif
print_eth_ip_addr();
print_baudrate();
print_num("relocaddr", gd->relocaddr);
board_detail();
return 0;
}
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
#ifdef DEBUG
print_num("bd address", (ulong)bd);
#endif
print_num("memstart", bd->bi_memstart);
print_lnum("memsize", bd->bi_memsize);
print_num("flashstart", bd->bi_flashstart);
print_num("flashsize", bd->bi_flashsize);
print_num("flashoffset", bd->bi_flashoffset);
print_num("sramstart", bd->bi_sramstart);
print_num("sramsize", bd->bi_sramsize);
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \
defined(CONFIG_8260) || defined(CONFIG_E500)
print_num("immr_base", bd->bi_immr_base);
#endif
print_num("bootflags", bd->bi_bootflags);
#if defined(CONFIG_405EP) || \
defined(CONFIG_405GP) || \
defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_XILINX_405)
print_mhz("procfreq", bd->bi_procfreq);
print_mhz("plb_busfreq", bd->bi_plb_busfreq);
#if defined(CONFIG_405EP) || defined(CONFIG_405GP) || \
defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405)
print_mhz("pci_busfreq", bd->bi_pci_busfreq);
#endif
#else /* ! CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
#if defined(CONFIG_CPM2)
print_mhz("vco", bd->bi_vco);
print_mhz("sccfreq", bd->bi_sccfreq);
print_mhz("brgfreq", bd->bi_brgfreq);
#endif
print_mhz("intfreq", bd->bi_intfreq);
#if defined(CONFIG_CPM2)
print_mhz("cpmfreq", bd->bi_cpmfreq);
#endif
print_mhz("busfreq", bd->bi_busfreq);
#endif /* CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
#ifdef CONFIG_ENABLE_36BIT_PHYS
#ifdef CONFIG_PHYS_64BIT
puts("addressing = 36-bit\n");
#else
puts("addressing = 32-bit\n");
#endif
#endif
print_eth(0);
#if defined(CONFIG_HAS_ETH1)
print_eth(1);
#endif
#if defined(CONFIG_HAS_ETH2)
print_eth(2);
#endif
#if defined(CONFIG_HAS_ETH3)
print_eth(3);
#endif
#if defined(CONFIG_HAS_ETH4)
print_eth(4);
#endif
#if defined(CONFIG_HAS_ETH5)
print_eth(5);
#endif
#ifdef CONFIG_HERMES
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
printf("IP addr = %s\n", getenv("ipaddr"));
printf("baudrate = %6u bps\n", bd->bi_baudrate);
print_num("relocaddr", gd->relocaddr);
board_detail();
return 0;
}
void __init s3c2443_init_clocks(int xtal)
{
struct clk *clkp;
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
int ret;
int ptr;
clk_h.parent = &clk_prediv;
clk_p.parent = &clk_prediv;
s3c24xx_register_baseclocks(xtal);
s3c2443_setup_clocks();
s3c2443_clk_initparents();
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
clkp = clks[ptr];
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
clk_epll.parent = &clk_epllref;
clk_usb_bus.parent = &clk_usb_bus_host;
if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) {
printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
clk_set_rate(&clk_usb_bus_host, 48*1000*1000);
}
printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
(epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(clk_get_rate(&clk_epll)),
print_mhz(clk_get_rate(&clk_usb_bus)));
clkp = init_clocks;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_CMD_BDI_DUMP_EMI_BANKS
#if !defined(ST40_EMI_SIZE)
#define ST40_EMI_SIZE (128 << 20) /* EMI is usually 128 MiB */
#endif /* ST40_EMI_SIZE */
#define MAX_EMI_BANKS 6 /* Maximum of 6 EMI Banks */
const u32 emi_base = 0xa0000000u;
u32 base[MAX_EMI_BANKS+1]; /* Base address for each bank */
u32 enabled; /* number of enabled EMI banks */
#endif /* CONFIG_CMD_BDI_DUMP_EMI_BANKS */
#if defined(CONFIG_CMD_NET) || CONFIG_CMD_BDI_DUMP_EMI_BANKS
unsigned int i;
#endif
bd_t *bd = gd->bd;
print_num ("boot_params", (ulong)bd->bi_boot_params);
print_num ("memstart", (ulong)bd->bi_memstart);
print_mem ("memsize", (ulong)bd->bi_memsize);
#ifndef CFG_NO_FLASH
print_num ("flashstart", (ulong)bd->bi_flashstart);
print_mem ("flashsize", (ulong)bd->bi_flashsize);
print_num ("flashoffset", (ulong)bd->bi_flashoffset);
#endif /* CFG_NO_FLASH */
#if defined(CONFIG_CMD_NET)
puts ("ethaddr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
}
puts ("\nip_addr = ");
print_IPaddr (bd->bi_ip_addr);
#endif
printf ("\nbaudrate = %d bps\n", bd->bi_baudrate);
#if defined(CONFIG_SH_STB7100)
if (STB7100_DEVICEID_7109(bd->bi_devid))
printf ("\nSTb7109 version %ld.x", STB7100_DEVICEID_CUT(bd->bi_devid));
else if (STB7100_DEVICEID_7100(bd->bi_devid))
printf ("\nSTb7100 version %ld.x", STB7100_DEVICEID_CUT(bd->bi_devid));
#elif defined(CONFIG_SH_STX5197)
if (STX5197_DEVICEID_5197(bd->bi_devid))
printf ("\nSTx5197 version %ld.x", STX5197_DEVICEID_CUT(bd->bi_devid));
#elif defined(CONFIG_SH_STX5206)
if (STX5206_DEVICEID_5206(bd->bi_devid))
printf ("\nSTx5206/STx5289 version %ld.x", STX5206_DEVICEID_CUT(bd->bi_devid));
#elif defined(CONFIG_SH_STX7105)
if (STX7105_DEVICEID_7105(bd->bi_devid))
printf ("\nSTx7105 version %ld.x", STX7105_DEVICEID_CUT(bd->bi_devid));
#elif defined(CONFIG_SH_STX7108)
if (STX7108_DEVICEID_7108(bd->bi_devid))
printf ("\nSTx7108 version %ld.x", STX7108_DEVICEID_CUT(bd->bi_devid));
#elif defined(CONFIG_SH_STX7111)
if (STX7111_DEVICEID_7111(bd->bi_devid))
printf ("\nSTx7111 version %ld.x", STX7111_DEVICEID_CUT(bd->bi_devid));
#elif defined(CONFIG_SH_STX7141)
if (STX7141_DEVICEID_7141(bd->bi_devid))
printf ("\nSTx7141 version %ld.x", STX7141_DEVICEID_CUT(bd->bi_devid));
#elif defined(CONFIG_SH_STX7200)
if (STX7200_DEVICEID_7200(bd->bi_devid))
printf ("\nSTx7200 version %ld.x", STX7200_DEVICEID_CUT(bd->bi_devid));
#elif defined(CONFIG_SH_FLI7510)
if (FLI7510_DEVICEID_7510(bd->bi_devid))
printf ("\nFLI7510 version %ld.x", FLI7510_DEVICEID_CUT(bd->bi_devid));
#elif defined(CONFIG_SH_FLI7540)
if (FLI7540_DEVICEID_7540(bd->bi_devid))
printf ("\nFLI7540 version %ld.x", FLI7540_DEVICEID_CUT(bd->bi_devid));
#else
#error Missing Device Definitions!
#endif
else
printf ("\nUnknown device! (id=0x%08lx)", bd->bi_devid);
#ifdef CONFIG_SH_SE_MODE
printf (" [32-bit mode]\n");
#else
printf (" [29-bit mode]\n");
#endif
#ifdef CONFIG_SH_STB7100
print_mhz ("PLL0", bd->bi_pll0frq);
print_mhz ("PLL1", bd->bi_pll1frq);
print_mhz ("ST40 CPU", bd->bi_st40cpufrq);
print_mhz ("ST40 BUS", bd->bi_st40busfrq);
print_mhz ("ST40 PER", bd->bi_st40perfrq);
print_mhz ("ST231 CPU", bd->bi_st231frq);
print_mhz ("ST BUS", bd->bi_stbusfrq);
print_mhz ("EMI", bd->bi_emifrq);
print_mhz ("LMI", bd->bi_lmifrq);
#else
print_mhz ("EMI", bd->bi_emifrq);
#endif /* CONFIG_SH_STB7100 */
#if CONFIG_CMD_BDI_DUMP_EMI_BANKS
enabled = *ST40_EMI_BANK_ENABLE;
printf("#EMI Banks = %u\n", enabled);
if (enabled > MAX_EMI_BANKS)
{
printf("Error: Maximum Number of Enabled Banks should be %u\n", MAX_EMI_BANKS);
enabled = MAX_EMI_BANKS;
}
/*
* EmiBaseAddress[5:0] == Address[27:22] (Multiple of 4MiB)
*
* Retreive all the configured EMI bank bases into base[].
*/
for(i=0; i<enabled; i++)
{
const u32 start = *ST40_EMI_BASEADDRESS(i) & 0x3fu;
base[i] = emi_base + (start << (22));
}
/* last valid bank occupies all remaining space */
base[i] = emi_base + ST40_EMI_SIZE; /* total size of EMI is usually 128MiB */
/*
* Print out the ranges of each bank.
*/
for(i=0; i<enabled; i++)
{
const u32 lower = base[i];
const u32 upper = base[i+1];
printf ("EMI #%u CS%c = 0x%08X ... 0x%08X (",
i,
'A' + i,
lower,
upper-1u);
print_size (upper-lower, ")\n");
}
#endif /* CONFIG_CMD_BDI_DUMP_EMI_BANKS */
return 0;
}
void __init_or_cpufreq s5p6450_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long hclk_low;
unsigned long pclk;
unsigned long pclk_low;
unsigned long epll;
unsigned long dpll;
unsigned long apll;
unsigned long mpll;
unsigned int ptr;
/* Set S5P6450 functions for clk_fout_epll */
clk_fout_epll.enable = s5p6450_epll_enable;
clk_fout_epll.ops = &s5p6450_epll_ops;
clk_48m.enable = s5p6450_clk48m_ctrl;
xtal_clk = clk_get(NULL, "ext_xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
__raw_readl(S5P_EPLL_CON_K));
dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P_DPLL_CON),
__raw_readl(S5P_DPLL_CON_K), pll_4650c);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_dpll.rate = dpll;
clk_fout_apll.rate = apll;
ctable.apll_rate = clk_fout_apll.rate/1000000;
switch (ctable.apll_rate)
{
case IS_ARM_800 :
ctable.clock_table_size = ARRAY_SIZE(clock_table_800);
ctable.clock_table = clock_table_800;
break;
case IS_ARM_667:
ctable.clock_table_size = ARRAY_SIZE(clock_table_667);
ctable.clock_table = clock_table_667;
break;
case IS_ARM_533:
ctable.clock_table_size = ARRAY_SIZE(clock_table_533);
ctable.clock_table = clock_table_533;
break;
default:
printk("------------------------- UNKNOW FREQ WARNING !!!!!!!!!--------------- e \n");
}
/*
if(ctable.apll_rate == IS_ARM_667){
printk("----------------------------------------- 667 Freq table \n");
ctable.clock_table_size = ARRAY_SIZE(clock_table_667);
ctable.clock_table = clock_table_667;
}else if(ctable.apll_rate == IS_ARM_533)
{
printk("----------------------------------------- 533 Freq table \n");
ctable.clock_table_size = ARRAY_SIZE(clock_table_533);
ctable.clock_table = clock_table_533;
}
*/
printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
" E=%ld.%ldMHz, D=%ld.%ldMHz\n",
print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(dpll));
fclk = clk_get_rate(&clk_armclk.clk);
hclk = clk_get_rate(&clk_hclk166.clk);
pclk = clk_get_rate(&clk_pclk83.clk);
hclk_low = clk_get_rate(&clk_hclk133.clk);
pclk_low = clk_get_rate(&clk_pclk66.clk);
printk(KERN_INFO "S5P6450: HCLK166=%ld.%ldMHz, HCLK133=%ld.%ldMHz," \
" PCLK83=%ld.%ldMHz, PCLK66=%ld.%ldMHz\n",
print_mhz(hclk), print_mhz(hclk_low),
print_mhz(pclk), print_mhz(pclk_low));
clk_f.rate = fclk;
clk_h.rate = hclk;
clk_p.rate = pclk;
clk_h_low.rate = hclk_low;
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++)
s3c_set_clksrc(clksrc_audio + ptr, true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
}
void __init s3c2443_init_clocks(int xtal)
{
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
unsigned long pll;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
struct clk *clkp;
int ret;
int ptr;
/* s3c2443 parents h and p clocks from prediv */
clk_h.parent = &clk_prediv;
clk_p.parent = &clk_prediv;
pll = s3c2443_get_mpll(mpllcon, xtal);
clk_msysclk.rate = pll;
fclk = pll / s3c2443_fclk_div(clkdiv0);
hclk = s3c2443_prediv_getrate(&clk_prediv);
hclk /= s3c2443_get_hdiv(clkdiv0);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(pll), print_mhz(fclk),
print_mhz(hclk), print_mhz(pclk));
s3c2443_clk_initparents();
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
clkp = clks[ptr];
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
clk_usb_bus.parent = &clk_usb_bus_host;
/* ensure usb bus clock is within correct rate of 48MHz */
if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) {
printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
clk_set_rate(&clk_usb_bus_host, 48*1000*1000);
}
printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
(epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(clk_get_rate(&clk_epll)),
print_mhz(clk_get_rate(&clk_usb_bus)));
/* register clocks from clock array */
clkp = init_clocks;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
/* We must be careful disabling the clocks we are not intending to
* be using at boot time, as subsystems such as the LCD which do
* their own DMA requests to the bus can cause the system to lockup
* if they where in the middle of requesting bus access.
*
* Disabling the LCD clock if the LCD is active is very dangerous,
* and therefore the bootloader should be careful to not enable
* the LCD clock if it is not needed.
*/
/* install (and disable) the clocks we do not need immediately */
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
}
