void platform_early_init(void)
{
ps7_init();
/* zynq manual says this is mandatory */
*REG32(SLCR_BASE + 0xa1c) = 0x020202;
/* early initialize the uart so we can printf */
uart_init_early();
/* initialize the interrupt controller */
arm_gic_init();
/* initialize the timer block */
arm_cortex_a9_timer_init(CPUPRIV_BASE, zynq_get_arm_timer_freq());
/* add the main memory arena */
#if !ZYNQ_CODE_IN_SDRAM && SDRAM_SIZE != 0
/* In the case of running from SRAM, and we are using SDRAM,
* there is a discontinuity between the end of SRAM (256K) and the start of SDRAM (1MB),
* so intentionally bump the boot-time allocator to start in the base of SDRAM.
*/
extern uintptr_t boot_alloc_start;
extern uintptr_t boot_alloc_end;
boot_alloc_start = KERNEL_BASE + MB;
boot_alloc_end = KERNEL_BASE + MB;
#endif
#if SDRAM_SIZE != 0
pmm_add_arena(&sdram_arena);
#endif
pmm_add_arena(&sram_arena);
}
int main(int argc, char* agrv[]) {
//initialize DDR and MMIO
ps7_init();
//Switch pin 7 to output
GPIO->DIRECTION_0 = GPIO->DIRECTION_0 | (1 << 7);
//Set pin 7 to on
GPIO->MASK_DATA_LSW_0 = ((~(1<<7)) << 16) | (1 << 7);
//disable stdout buffering
setvbuf(stdout, 0, _IONBF, 0);
UartInitialize(UART1, 115200);
printf("Initialized\n");
unsigned int id = CPUGetCoreNumber();
printf("Running on CPU %X\n", id);
GICInit();
printf("GIC Initialized\n");
GICUnmaskInterrupt(29);
GICConnectInterrupt(29, TimerHandler);
PrivateTimerStop(PRIVATE_TIMER);
PrivateTimerSetPrescaler(PRIVATE_TIMER, 255);
PrivateTimerLoad(PRIVATE_TIMER, 1302083);
PrivateTimerEnableAutoReload(PRIVATE_TIMER, 1302083);
PrivateTimerEnableInterrupt(PRIVATE_TIMER);
PrivateTimerClearExpiration(PRIVATE_TIMER);
PrivateTimerStart(PRIVATE_TIMER);
//enable interrupts
CPUEnableInterrupts();
//CPUEnableFastInterrupts();
//uint32_t foo = 0;
while(1)
{
/*if(PrivateTimerIsExpired(PRIVATE_TIMER))
{
foo++;
PrivateTimerClearExpiration(PRIVATE_TIMER);
}
if(foo % 10000 == 0)
printf("A");*/
//uint8_t foo = UartReceiveByte(UART1);
//UartSendByte(UART1, foo);
}
//int* foo = malloc(0x20);
return 0;
}
void board_init_f(ulong dummy)
{
ps7_init();
arch_cpu_init();
/*
* The debug UART can be used from this point:
* debug_uart_init();
* printch('x');
*/
}
void board_init_f(ulong dummy)
{
ps7_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
preloader_console_init();
arch_cpu_init();
board_init_r(NULL, 0);
}
void board_init_f(ulong dummy)
{
ps7_init();
arch_cpu_init();
#ifdef CONFIG_DEBUG_UART
/* Uart debug for sure */
debug_uart_init();
puts("Debug uart enabled\n"); /* or printch() */
#endif
}
void board_init_f(ulong dummy)
{
ps7_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* Set global data pointer. */
gd = &gdata;
preloader_console_init();
arch_cpu_init();
board_init_r(NULL, 0);
}
void
init_platform()
{
/*
* If you want to run this example outside of SDK,
* uncomment the following line and also #include "ps7_init.h" at the top.
* Make sure that the ps7_init.c and ps7_init.h files are included
* along with this example source files for compilation.
*/
#if( INCLUDE_PS7_INIT != 0 )
{
ps7_init();
}
#endif
enable_caches();
init_uart();
}
void platform_early_init(void)
{
#if 0
ps7_init();
#else
/* Unlock the registers and leave them that way */
zynq_slcr_unlock();
zynq_mio_init();
zynq_pll_init();
zynq_clk_init();
#if ZYNQ_SDRAM_INIT
zynq_ddr_init();
#endif
#endif
/* Enable all level shifters */
SLCR_REG(LVL_SHFTR_EN) = 0xF;
/* FPGA SW reset (not documented, but mandatory) */
SLCR_REG(FPGA_RST_CTRL) = 0x0;
/* zynq manual says this is mandatory for cache init */
*REG32(SLCR_BASE + 0xa1c) = 0x020202;
/* early initialize the uart so we can printf */
uart_init_early();
/* initialize the interrupt controller */
arm_gic_init();
zynq_gpio_init();
/* initialize the timer block */
arm_cortex_a9_timer_init(CPUPRIV_BASE, zynq_get_arm_timer_freq());
/* bump the 2nd cpu into our code space and remap the top SRAM block */
if (KERNEL_LOAD_OFFSET != 0) {
/* construct a trampoline to get the 2nd cpu up to the trap routine */
/* figure out the offset of the trampoline routine in physical space from address 0 */
extern void platform_reset(void);
addr_t tramp = (addr_t)&platform_reset;
tramp -= KERNEL_BASE;
tramp += MEMBASE;
/* stuff in a ldr pc, [nextaddrress], and a target address */
uint32_t *ptr = (uint32_t *)KERNEL_BASE;
ptr[0] = 0xe51ff004; // ldr pc, [pc, #-4]
ptr[1] = tramp;
arch_clean_invalidate_cache_range((addr_t)ptr, 8);
}
/* reset the 2nd cpu, letting it go through its reset vector (at 0x0 physical) */
SLCR_REG(A9_CPU_RST_CTRL) |= (1<<1); // reset cpu 1
spin(10);
SLCR_REG(A9_CPU_RST_CTRL) &= ~(1<<1); // unreset cpu 1
/* wait for the 2nd cpu to reset, go through the usual reset vector, and get trapped by our code */
/* see platform/zynq/reset.S */
extern volatile int __cpu_trapped;
uint count = 100000;
while (--count) {
arch_clean_invalidate_cache_range((addr_t)&__cpu_trapped, sizeof(__cpu_trapped));
if (__cpu_trapped != 0)
break;
}
if (count == 0) {
panic("ZYNQ: failed to trap 2nd cpu\n");
}
/* bounce the 4th sram region down to lower address */
SLCR_REG(OCM_CFG) &= ~0xf; /* all banks at low address */
/* add the main memory arena */
#if !ZYNQ_CODE_IN_SDRAM && SDRAM_SIZE != 0
/* In the case of running from SRAM, and we are using SDRAM,
* there is a discontinuity between the end of SRAM (256K) and the start of SDRAM (1MB),
* so intentionally bump the boot-time allocator to start in the base of SDRAM.
*/
extern uintptr_t boot_alloc_start;
extern uintptr_t boot_alloc_end;
boot_alloc_start = KERNEL_BASE + MB;
boot_alloc_end = KERNEL_BASE + MB;
#endif
#if SDRAM_SIZE != 0
pmm_add_arena(&sdram_arena);
#endif
pmm_add_arena(&sram_arena);
}
