Exemplo n.º 1
0
int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
    ARMCPU *cpu = ARM_CPU(cs);
    CPUARMState *env = &cpu->env;
    uint64_t tmp;

    tmp = ldq_p(mem_buf);

    if (n < 31) {
        /* Core integer register.  */
        env->xregs[n] = tmp;
        return 8;
    }
    switch (n) {
    case 31:
        env->xregs[31] = tmp;
        return 8;
    case 32:
        env->pc = tmp;
        return 8;
    case 33:
        /* CPSR */
        pstate_write(env, tmp);
        return 4;
    }
    /* Unknown register.  */
    return 0;
}
Exemplo n.º 2
0
static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val = qemu_get_be32(f);

    env->aarch64 = ((val & PSTATE_nRW) == 0);

    if (is_a64(env)) {
        pstate_write(env, val);
        return 0;
    }

    cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
    return 0;
}
Exemplo n.º 3
0
static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val = qemu_get_be32(f);

    env->aarch64 = ((val & PSTATE_nRW) == 0);

    if (is_a64(env)) {
        pstate_write(env, val);
        return 0;
    }

    /* Avoid mode switch when restoring CPSR */
    env->uncached_cpsr = val & CPSR_M;
    cpsr_write(env, val, 0xffffffff);
    return 0;
}
Exemplo n.º 4
0
/* FIXME: This should be generalized and moved into helper.c */
static void map_a32_to_a64_regs(CPUARMState *env)
{
    unsigned int i;

    for (i = 0; i < 13; i++) {
        env->xregs[i] = env->regs[i];
    }
    env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
    env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];

    for (i = 0; i < ARRAY_SIZE(env->fiq_regs); i++) {
        env->xregs[i + 24] = env->fiq_regs[i];
    }
    env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
    env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];

    /* HAX!  */
    env->xregs[31] = env->regs[13];

    env->pc = env->regs[15];
    pstate_write(env, env->spsr | (1 << 4));
}
Exemplo n.º 5
0
int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
    ARMCPU *cpu = ARM_CPU(cs);
    CPUARMState *env = &cpu->env;
    uint64_t tmp;
    int rlen = 0;

#ifndef CONFIG_USER_ONLY
    if (!is_a64(env)) {
        map_a32_to_a64_regs(env);
    }
#endif

    tmp = ldq_p(mem_buf);

    if (n < 31) {
        /* Core integer register.  */
        env->xregs[n] = tmp;
        rlen = 8;
    }
    switch (n) {
    case 31: {
        unsigned int cur_el = arm_current_el(env);

        aarch64_save_sp(env, cur_el);
        switch (env->debug_ctx) {
            case DEBUG_EL0:
                env->sp_el[0] = tmp;
                break;
            case DEBUG_EL1:
                env->sp_el[1] = tmp;
                break;
            case DEBUG_EL2:
                env->sp_el[2] = tmp;
                break;
            case DEBUG_EL3:
                env->sp_el[3] = tmp;
                break;
            default:
                env->xregs[31] = tmp;
                break;
        }
        aarch64_restore_sp(env, cur_el);
        rlen = 8;
        break;
    }
    case 32:
        env->pc = tmp;
        rlen = 8;
        break;
    case 33:
        /* CPSR */
        pstate_write(env, tmp);
        rlen = 4;
        break;
    }

#ifndef CONFIG_USER_ONLY
    if (!is_a64(env)) {
        map_a64_to_a32_regs(env);
    }
#endif

    /* Unknown register.  */
    return rlen;
}