int main(void) {
nvmType_t type=0;
nvmErr_t err;
volatile uint8_t c;
volatile uint32_t i;
volatile uint32_t buf[4];
volatile uint32_t len=0;
volatile uint32_t state = SCAN_X;
volatile uint32_t addr,data;
uart_init(UART1, 115200);
disable_irq(UART1);
vreg_init();
dbg_putstr("Detecting internal nvm\n\r");
err = nvm_detect(gNvmInternalInterface_c, &type);
dbg_putstr("nvm_detect returned: 0x");
dbg_put_hex(err);
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)nvm_base, NVM_BASE, 0x100);
dbg_putstr("nvm_read returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
/* erase the flash */
nvm_setsvar(0);
err = nvm_erase(gNvmInternalInterface_c, type, 0x40000000);
dbg_putstr("nvm_erase returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)nvm_base, NVM_BASE, 0x100);
dbg_putstr("nvm_write returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
/* say we are ready */
len = 0;
putstr("ready");
flushrx();
/* read the length */
for(i=0; i<4; i++) {
c = uart1_getc();
/* bail if the first byte of the length is zero */
len += (c<<(i*8));
}
dbg_putstr("len: ");
dbg_put_hex32(len);
dbg_putstr("\n\r");
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
putstr("flasher done\n\r");
state = SCAN_X; addr=0;
while((c=getc())) {
if(state == SCAN_X) {
/* read until we see an 'x' */
if(c==0) { break; }
if(c!='x'){ continue; }
/* go to read_chars once we have an 'x' */
state = READ_CHARS;
i = 0;
}
if(state == READ_CHARS) {
/* read all the chars up to a ',' */
((uint8_t *)buf)[i++] = c;
/* after reading a ',' */
/* goto PROCESS state */
if((c == ',') || (c == 0)) { state = PROCESS; }
}
if(state == PROCESS) {
if(addr==0) {
/*interpret the string as the starting address */
addr = to_u32(buf);
} else {
/* string is data to write */
data = to_u32(buf);
putstr("writing addr ");
put_hex32(NVM_BASE+addr);
putstr(" data ");
put_hex32(data);
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&data, NVM_BASE+addr, 4);
addr += 4;
putstr(" err ");
put_hex32(err);
putstr("\n\r");
}
/* look for the next 'x' */
state=SCAN_X;
}
}
putstr("process flasher done\n\r");
while(1) {continue;};
}
void main(void) {
uart_init(UART1, 115200);
*mem32(0x00401ffc) = 0x01234567;
*mem32(0x00407ffc) = 0xdeadbeef;
*mem32(0x0040fffc) = 0xface00ff;
*mem32(0x00410000) = 0xabcd0123;
putstr("sleep test\n\r");
putstr("0x00401ffc: ");
put_hex32(*mem32(0x00401ffc));
putstr("\r\n");
putstr("0x00407ffc: ");
put_hex32(*mem32(0x00407ffc));
putstr("\r\n");
putstr("0x0040fffc: ");
put_hex32(*mem32(0x0040fffc));
putstr("\r\n");
putstr("0x00410000: ");
put_hex32(*mem32(0x00410000));
putstr("\r\n");
GPIO->FUNC_SEL.ADC3 = 1;
GPIO->PAD_DIR.ADC3 = 0;
GPIO->PAD_KEEP.ADC3 = 0;
GPIO->PAD_PU_EN.ADC3 = 0;
adc_init();
ADC->COMP_3= 0x38ff; //use channel 3, compare on 0ff
ADC->SEQ_1 = 0x8; //only channel 3 is enabled
ADC->CONTROL &= ~0xe000;
/* radio must be OFF before sleeping */
/* otherwise MCU will not wake up properly */
/* this is undocumented behavior */
// radio_off();
#if USE_32KHZ
/* turn on the 32kHz crystal */
putstr("enabling 32kHz crystal\n\r");
/* you have to hold it's hand with this on */
/* once you start the 32xHz crystal it can only be stopped with a reset (hard or soft) */
/* first, disable the ring osc */
clear_bit(*CRM_RINGOSC_CNTL,0);
/* enable the 32kHZ crystal */
set_bit(*CRM_XTAL32_CNTL,0);
/* set the XTAL32_EXISTS bit */
/* the datasheet says to do this after you've check that RTC_COUNT is changing */
/* the datasheet is not correct */
set_bit(*CRM_SYS_CNTL,5);
{
static volatile uint32_t old;
old = *CRM_RTC_COUNT;
putstr("waiting for xtal\n\r");
while(*CRM_RTC_COUNT == old) {
continue;
}
/* RTC has started up */
set_bit(*CRM_SYS_CNTL,5);
putstr("32kHZ xtal started\n\r");
}
#endif
/* go to sleep */
*CRM_SLEEP_CNTL = 0x70;
// *CRM_WU_CNTL = 0; /* don't wake up */
*CRM_WU_CNTL = 0xb; /* enable wakeup from wakeup timer, rtc for sampling, and auto adc */
// *CRM_WU_TIMEOUT = 1875000; /* wake 10 sec later if doze */
#if USE_32KHZ
*CRM_WU_TIMEOUT = 327680*2;
#else
*CRM_WU_TIMEOUT = 200000; /* wake 10 sec later if hibernate ring osc */
*CRM_RTC_TIMEOUT= 200; //sample 10 times a second
#endif
enable_irq(ADC);
/* hobby board: 2kHz = 11uA; 32kHz = 11uA */
// *CRM_SLEEP_CNTL = 1; /* hibernate, RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 2kHz = 2.0uA */
/* hobby board: 2kHz = 18uA; 32kHz = 19uA */
// *CRM_SLEEP_CNTL = 0x41; /* hibernate, RAM page 0 only, retain state, don't power GPIO */ /* approx. 2kHz = 10.0uA */
/* hobby board: 2kHz = 20uA; 32kHz = 21uA */
// *CRM_SLEEP_CNTL = 0x51; /* hibernate, RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 2kHz = 11.7uA */
/* hobby board: 2kHz = 22uA; 32kHz = 22.5uA */
// *CRM_SLEEP_CNTL = 0x61; /* hibernate, RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 2kHz = 13.9uA */
/* hobby board: 2kHz = 24uA; 32kHz = 25uA */
*CRM_SLEEP_CNTL = 0x71; /* hibernate, all RAM pages, retain state, don't power GPIO */ /* approx. 2kHz = 16.1uA */
// *CRM_SLEEP_CNTL = 0xf1; /* hibernate, all RAM pages, retain state, power GPIO */ /* consumption depends on GPIO hookup */
// *CRM_SLEEP_CNTL = 2; /* doze , RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 69.2 uA */
// *CRM_SLEEP_CNTL = 0x42; /* doze , RAM page 0 only, retain state, don't power GPIO */ /* approx. 77.3uA */
// *CRM_SLEEP_CNTL = 0x52; /* doze , RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 78.9uA */
// *CRM_SLEEP_CNTL = 0x62; /* doze , RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 81.2uA */
// *CRM_SLEEP_CNTL = 0x72; /* doze , all RAM pages, retain state, don't power GPIO */ /* approx. 83.4uA - possibly with periodic refresh*/
// *CRM_SLEEP_CNTL = 0xf2; /* doze , all RAM pages, retain state, power GPIO */ /* consumption depends on GPIO hookup */
/* wait for the sleep cycle to complete */
while((*CRM_STATUS & 0x1) == 0) { continue; }
/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and powers down */
*CRM_STATUS = 1;
/* asleep */
/* wait for the awake cycle to complete */
while((*CRM_STATUS & 0x1) == 0) { continue; }
/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and finishes wakeup */
*CRM_STATUS = 1;
putstr("\n\r\n\r\n\r");
putstr("0x00401ffc: ");
put_hex32(*mem32(0x00401ffc));
putstr("\r\n");
putstr("0x00407ffc: ");
put_hex32(*mem32(0x00407ffc));
putstr("\r\n");
putstr("0x0040fffc: ");
put_hex32(*mem32(0x0040fffc));
putstr("\r\n");
putstr("0x00410000: ");
put_hex32(*mem32(0x00410000));
putstr("\r\n");
*GPIO_PAD_DIR0 = LED_RED;
#define DELAY 400000
//uint32_t read;
volatile uint32_t i;
while(1) {
*GPIO_DATA0 = LED_RED;
for(i=0; i<DELAY; i++) { continue; }
*GPIO_DATA0 = 0;
for(i=0; i<DELAY; i++) { continue; }
if(rupt==1)
{
putstr("adc interrupt! \r\n");
rupt=0;
}
};
}
void main(void) {
nvmType_t type=0;
nvmErr_t err;
volatile uint8_t c;
volatile uint32_t i;
volatile uint32_t buf[4];
volatile uint32_t len=0;
volatile uint32_t state = SCAN_X;
volatile uint32_t addr,data;
uart_init(INC, MOD, SAMP);
disable_irq(UART1);
vreg_init();
dbg_putstr("Detecting internal nvm\n\r");
err = nvm_detect(gNvmInternalInterface_c, &type);
dbg_putstr("nvm_detect returned: 0x");
dbg_put_hex(err);
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
/* erase the flash */
err = nvm_erase(gNvmInternalInterface_c, type, 0x7fffffff);
dbg_putstr("nvm_erase returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
/* say we are ready */
len = 0;
putstr("ready");
flushrx();
/* read the length */
for(i=0; i<4; i++) {
c = uart1_getc();
/* bail if the first byte of the length is zero */
len += (c<<(i*8));
}
dbg_putstr("len: ");
dbg_put_hex32(len);
dbg_putstr("\n\r");
/* write the OKOK magic */
#if BOOT_OK
((uint8_t *)buf)[0] = 'O'; ((uint8_t *)buf)[1] = 'K'; ((uint8_t *)buf)[2] = 'O'; ((uint8_t *)buf)[3] = 'K';
#elif BOOT_SECURE
((uint8_t *)buf)[0] = 'S'; ((uint8_t *)buf)[1] = 'E'; ((uint8_t *)buf)[2] = 'C'; ((uint8_t *)buf)[3] = 'U';
#else
((uint8_t *)buf)[0] = 'N'; ((uint8_t *)buf)[1] = 'O'; ((uint8_t *)buf)[2] = 'N'; ((uint8_t *)buf)[3] = 'O';
#endif
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
/* don't make a valid boot image if the received length is zero */
if(len == 0) {
((uint8_t *)buf)[0] = 'N';
((uint8_t *)buf)[1] = 'O';
((uint8_t *)buf)[2] = 'N';
((uint8_t *)buf)[3] = 'O';
}
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)buf, 0, 4);
dbg_putstr("nvm_write returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
/* write the length */
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&len, 4, 4);
/* read a byte, write a byte */
for(i=0; i<len; i++) {
c = getc();
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&c, 8+i, 1);
}
putstr("flasher done\n\r");
state = SCAN_X; addr=0;
while((c=getc())) {
if(state == SCAN_X) {
/* read until we see an 'x' */
if(c==0) { break; }
if(c!='x'){ continue; }
/* go to read_chars once we have an 'x' */
state = READ_CHARS;
i = 0;
}
if(state == READ_CHARS) {
/* read all the chars up to a ',' */
((uint8_t *)buf)[i++] = c;
/* after reading a ',' */
/* goto PROCESS state */
if((c == ',') || (c == 0)) { state = PROCESS; }
}
if(state == PROCESS) {
if(addr==0) {
/*interpret the string as the starting address */
addr = to_u32(buf);
} else {
/* string is data to write */
data = to_u32(buf);
putstr("writing addr ");
put_hex32(addr);
putstr(" data ");
put_hex32(data);
putstr("\n\r");
err = nvm_write(gNvmInternalInterface_c, 1, (uint8_t *)&data, addr, 4);
addr += 4;
}
/* look for the next 'x' */
state=SCAN_X;
}
}
while(1) {continue;};
}