Exemplo n.º 1
0
int main()
{
    init_platform();

    xil_printf("%s\n\r", "Welcome to Brutus cracker system!");

    while (1) {
    	xil_printf("%s\n\r", "Enter hash: ");
		char recv = XUartLite_RecvByte(STDIN_BASEADDRESS); // read first char


		/* Read password hash */
		char buff[32];
		int idx_buff = 0;
		while (recv != '\r') {
			buff[idx_buff++] = recv;
			recv = XUartLite_RecvByte(STDIN_BASEADDRESS);
		}

		unsigned int i_buff[4] = {0};
		unsigned num = 0;

		for (int i = 0; i < 4; i++) {
			for (int j = 0; j < 8; j++) {
				num = ctox(buff[j + i*8]);
				i_buff[i] += (pow(16, 7-j) * num);
			}
			//xil_printf("%x\n\r", i_buff[i]);
		}

		//xil_printf("%u\n\r", i_buff[0]);


		putfsl(i_buff[0], 0);
		putfsl(i_buff[1], 0);
		putfsl(i_buff[2], 0);
		putfsl(i_buff[3], 0);
		xil_printf("Cracking...\n\r");

		unsigned int resp;
		char *str = &resp; // c-magic

		getfsl(resp, 0);
		unsigned i;
		xil_printf("password: "******"%c", *(str+i));
		}
		getfsl(resp, 0);
		for (i = 0; i < 4; i++) {
			xil_printf("%c", *(str+i));
		}
		xil_printf("\n\r");
    }
    cleanup_platform();

    return 0;
}
Exemplo n.º 2
0
int main (void) 
{
   
//------- LOOP FOR IMAGES -------
	for (m=0; m < Number_of_Images; m++)  // loop for Images 
	{
	getfsl(id1,0);	                       // Start Signal			
	
  //void fdct_8x8(short dct_data, unsigned num_fdcts)  
                   
  /* -------------------------------------------------------- /    
     /  Set up the cosine coefficients c0..c7.                  /    
     / -------------------------------------------------------- */    
  const unsigned short c1 = 0x2C62, c3 = 0x25A0;                    
  const unsigned short c5 = 0x1924, c7 = 0x08D4;                    
  const unsigned short c0 = 0xB505, c2 = 0x29CF;                    
  const unsigned short c6 = 0x1151;                                 
                                                                           
  /* -------------------------------------------------------- /    
     /  Intermediate calculations.                              /    
     / -------------------------------------------------------- */    
  short f0, f1, f2, f3,f4, f5, f6, f7;       // Spatial domain samples.       
  int   g0, g1, h0, h1,p0, p1;               // Even-half intermediate.     
  short r0, r1;               // Even-half intermediate.     
  int   P0, P1, R0, R1;       // Even-half intermediate.         
  short g2, g3, h2, h3;       // Odd-half intermediate.           
  short q0a,s0a,q0, q1,s0, s1;               // Odd-half intermediate.          
  short Q0, Q1, S0, S1;       // Odd-half intermediate.       
  int   F0, F1, F2, F3, F4, F5, F6, F7;       // Freq. domain results. 
  int   F0r,F1r,F2r,F3r,F4r,F5r,F6r,F7r;      // Rounded, truncated results.   
  
  /* -------------------------------------------------------- /    
     /  Input and output pointers, loop control.                /    
     / -------------------------------------------------------- */    
  unsigned i, j, i_1;                                                  
        
  
  #ifdef chksum
/* initilize the input image */
 for (i = 0; i < num_fdcts*M; i++) 
    dct_io_ptr[i] = i;   
#endif	

 
		 
  /* -------------------------------------------------------- /    
     /  Outer vertical loop -- Process each 8x8 block.          /    
     / -------------------------------------------------------- */    
  //dct_io_ptr = dct_data;    
  i_1 = 0;
  for (i = 0; i < num_fdcts; i++) {      
 
    /* ---------------------------------------------------- /    
       /  Perform Vert 1-D FDCT on columns within each block. /    
       / ---------------------------------------------------- */    
    for (j = 0; j < N; j++) {                                                             
      /* ------------------------------------------------ /    
	 /  Load the spatial-domain samples.                /    
	 / ------------------------------------------------ */    
      f0 = dct_io_ptr[ 0+i_1];                                      
      f1 = dct_io_ptr[ 8+i_1];                                      
      f2 = dct_io_ptr[16+i_1];                                      
      f3 = dct_io_ptr[24+i_1];                                      
      f4 = dct_io_ptr[32+i_1];                                      
      f5 = dct_io_ptr[40+i_1];                                      
      f6 = dct_io_ptr[48+i_1];                                      
      f7 = dct_io_ptr[56+i_1];                                      
                                                                           
      /* ------------------------------------------------ /    
	 /  Stage 1:  Separate into even and odd halves.    /    
	 / ------------------------------------------------ */    
      g0 = f0 + f7;               h2 = f0 - f7;                 
      g1 = f1 + f6;               h3 = f1 - f6;                 
      h1 = f2 + f5;               g3 = f2 - f5;                 
      h0 = f3 + f4;               g2 = f3 - f4;                 
      
      /* ------------------------------------------------ /    
	 /  Stage 2                                         /    
	 / ------------------------------------------------ */    
      p0 = g0 + h0;               r0 = g0 - h0;                 
      p1 = g1 + h1;               r1 = g1 - h1;                 
      q1 = g2;                    s1 = h2;                      
      
      s0a= h3 + g3;               q0a= h3 - g3;                   
      s0 = (s0a * c0 + 0x7FFF) >> 16;                           
      q0 = (q0a * c0 + 0x7FFF) >> 16;                           
                                                                           
      /* ------------------------------------------------ /    
	 /  Stage 3                                         /    
	 / ------------------------------------------------ */    
      P0 = p0 + p1;             P1 = p0 - p1;                 
      R1 = c6 * r1 + c2 * r0;     R0 = c6 * r0 - c2 * r1;       
      
      Q1 = q1 + q0;               Q0 = q1 - q0;                 
      S1 = s1 + s0;               S0 = s1 - s0;                 
      
      /* ------------------------------------------------ /    
	 /  Stage 4                                         /    
	 / ------------------------------------------------ */    
      F0 = P0;                    F4 = P1;                      
      F2 = R1;                    F6 = R0;                      
      
      F1 = c7 * Q1 + c1 * S1;     F7 = c7 * S1 - c1 * Q1;       
      F5 = c3 * Q0 + c5 * S0;     F3 = c3 * S0 - c5 * Q0;        
      
      /* ------------------------------------------------ /    
	 /  Store the frequency domain results.             /    
	 / ------------------------------------------------ */    
	
		
	 putfsl(0+i_1, 0);
	putfsl(F0, 0);
	
	putfsl(8+i_1, 0);
	putfsl(F1 >> 13, 0);
	
	putfsl(16+i_1, 0);
	putfsl(F2 >> 13, 0);
	
	putfsl(24+i_1, 0);
	putfsl(F3 >> 13, 0);
	
	putfsl(32+i_1, 0);
	putfsl(F4, 0);

	putfsl(40+i_1, 0);
	putfsl(F5 >> 13, 0);

	putfsl(48+i_1, 0);
	putfsl(F6 >> 13, 0);

	putfsl(56+i_1, 0);
	putfsl(F7 >> 13, 0);

	i_1++;                                            
    }                                                             
    /* ---------------------------------------------------- /    
    /  Update pointer to next 8x8 FDCT block.              /    
   / ---------------------------------------------------- */    
   i_1 += 56;                                    
  }
 putfsl(999999999,0);					 // Stop Signal
}  
 	
  
   return 0;
} 
Exemplo n.º 3
0
void icap_reset(int resetProduction)
{
	unsigned long int fpga_base;
	u32 val;

	// ICAP behavior is described (poorly) in Xilinx specification UG380.  Brave
	// souls may look there for detailed guidance on what is being done here.
	fpga_base = (resetProduction != 0) ? RUNTIME_FPGA_BASE : BOOT_FPGA_BASE;
#ifdef CONFIG_SYS_GPIO
	if ((rdreg32(CONFIG_SYS_GPIO_ADDR) &
			(GARCIA_FPGA_LX100_ID | GARCIA_FPGA_LX150_ID)) == GARCIA_FPGA_LX150_ID) {
		fpga_base = BOOT_FPGA_BASE;
	}
#endif

	// It has been empirically determined that ICAP FSL doesn't always work
	// the first time, but if retried enough times it does eventually work.
	// Thus we keep hammering the operation we want and checking for failure
	// until we finally succeed.  Somebody please fix ICAP!! <sigh>

	// Abort anything in progress
	do {
		putfslx(0x0FFFF, 0, FSL_CONTROL); // Control signal aborts, data doesn't matter
		udelay(1000);
		getfsl(val, 0); // Read the ICAP result
	} while ((val & ICAP_FSL_FAILED) != 0);

	do {
		// Synchronize command bytes
		putfsl(0x0FFFF, 0); // Pad words
		putfsl(0x0FFFF, 0);
		putfsl(0x0AA99, 0); // SYNC
		putfsl(0x05566, 0); // SYNC

#ifndef CONFIG_SPI_FLASH
		// Set the Mode register so that fallback images will be manipulated
		// correctly.  Use bitstream mode instead of physical mode (required
		// for configuration fallback) and set boot mode for BPI
		putfsl(0x03301, 0); // Write MODE_REG
		putfsl(0x02000, 0); // Value 0 allows u-boot to use production image
#endif
		// Write the reconfiguration FPGA offset; the base address of the
		// "run-time" FPGA is #defined as a byte address, but the ICAP needs
		// a 16-bit half-word address, so we shift right by one extra bit.
#ifdef CONFIG_SPI_FLASH
		putfsl(0x03261, 0); // Write GENERAL1
		putfsl(((fpga_base >> 0) & 0x0FFFF), 0); // Multiboot start address[15:0]
		putfsl(0x03281, 0); // Write GENERAL2
		putfsl((((fpga_base >> 16) & 0x0FF) | 0x0300), 0); // Opcode 0x00 and address[23:16]

		// Write the fallback FPGA offset (this image)
		putfsl(0x032A1, 0); // Write GENERAL3
		putfsl(((BOOT_FPGA_BASE >> 0) & 0x0FFFF), 0);
		putfsl(0x032C1, 0); // Write GENERAL4
		putfsl((((BOOT_FPGA_BASE >> 16) & 0x0FF) | 0x0300), 0);
#else
		putfsl(0x03261, 0); // Write GENERAL1
		putfsl(((fpga_base >> 1) & 0x0FFFF), 0); // Multiboot start address[15:0]
		putfsl(0x03281, 0); // Write GENERAL2
		putfsl(((fpga_base >> 17) & 0x0FF), 0); // Opcode 0x00 and address[23:16]

		// Write the fallback FPGA offset (this image)
		putfsl(0x032A1, 0); // Write GENERAL3
		putfsl(((BOOT_FPGA_BASE >> 1) & 0x0FFFF), 0);
		putfsl(0x032C1, 0); // Write GENERAL4
		putfsl(((BOOT_FPGA_BASE >> 17) & 0x0FF), 0);
#endif

		putfsl(0x032E1, 0); // Write GENERAL5
		putfsl((resetProduction ? 1 : 0), 0); // Value 0 allows u-boot to use production image

		// Write IPROG command
		putfsl(0x030A1, 0); // Write CMD
		putfsl(0x0000E, 0); // IPROG Command

		// Add some safety noops
		putfsl(0x02000, 0); // Type 1 NOP
		putfsl(FINISH_FSL_BIT | 0x02000, 0); // Type 1 NOP, and Trigger the FSL peripheral to drain the FIFO into the ICAP
		__udelay (1000);
		getfsl(val, 0); // Read the ICAP result
	} while ((val & ICAP_FSL_FAILED) != 0);

	return;
}