static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *_pwm)
{
struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
tpu_pwm_timer_stop(pwm);
kfree(pwm);
}
static void s3c_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct s3c_chip *s3c = to_s3c_chip(chip);
struct s3c_pwm_device *s3c_pwm = pwm_get_chip_data(pwm);
void __iomem *reg_base = s3c->reg_base;
unsigned long flags;
unsigned long tcon;
spin_lock_irqsave(&pwm_spinlock, flags);
if (pwm_is_s3c24xx(s3c)) {
tcon = __raw_readl(reg_base + REG_TCON);
tcon &= ~pwm_tcon_start(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
} else {
tcon = __raw_readl(reg_base + REG_TCON);
tcon &= ~pwm_tcon_autoreload(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
}
s3c_pwm->running = 0;
pwm_enable_cnt--;
spin_unlock_irqrestore(&pwm_spinlock, flags);
}
static int bfin_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct bfin_pwm *priv = pwm_get_chip_data(pwm);
enable_gptimer(priv->pin);
return 0;
}
static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *_pwm)
{
struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
/* The timer must be running to modify the pin output configuration. */
tpu_pwm_timer_start(pwm);
tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE);
tpu_pwm_timer_stop(pwm);
}
static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *_pwm,
enum pwm_polarity polarity)
{
struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
pwm->polarity = polarity;
return 0;
}
static void bfin_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct bfin_pwm *priv = pwm_get_chip_data(pwm);
if (priv) {
peripheral_free(priv->pin);
kfree(priv);
}
}
static void s3c_pwm_free(struct pwm_chip *chip,
struct pwm_device *pwm)
{
struct s3c_chip *s3c = to_s3c_chip(chip);
struct s3c_pwm_device *s3c_pwm = pwm_get_chip_data(pwm);
unsigned int id = pwm->pwm;
s3c->s3c_pwm[id] = NULL;
devm_kfree(chip->dev, s3c_pwm);
}
static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
{
struct s3c_pwm_device *s3c_pwm = pwm_get_chip_data(pwm);
unsigned long tin_parent_rate;
unsigned int div;
tin_parent_rate = clk_get_rate(clk_get_parent(s3c_pwm->clk_div));
clk_set_rate(clk_get_parent(s3c_pwm->clk_div),tin_parent_rate);
for (div = 2; div <= 16; div *= 2) {
if ((tin_parent_rate / (div << 16)) < freq)
return tin_parent_rate / div;
}
return tin_parent_rate / 16;
}
static int s3c_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct s3c_chip *s3c = to_s3c_chip(chip);
struct s3c_pwm_device *s3c_pwm = pwm_get_chip_data(pwm);
void __iomem *reg_base = s3c->reg_base;
unsigned long flags;
unsigned long tcon;
spin_lock_irqsave(&pwm_spinlock, flags);
if (pwm_is_s3c24xx(s3c)) {
tcon = __raw_readl(reg_base + REG_TCON);
tcon |= pwm_tcon_start(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
} else {
tcon = __raw_readl(reg_base + REG_TCON);
if (!(tcon & pwm_tcon_start(s3c_pwm))) {
tcon |= pwm_tcon_manulupdate(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
tcon &= ~pwm_tcon_manulupdate(s3c_pwm);
if (s3c_pwm->duty_cycle == DUTY_CYCLE_ZERO)
tcon &= ~pwm_tcon_autoreload(s3c_pwm);
else
tcon |= pwm_tcon_autoreload(s3c_pwm);
tcon |= pwm_tcon_start(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
} else if (!(tcon & pwm_tcon_autoreload(s3c_pwm)) &&
s3c_pwm->duty_cycle != DUTY_CYCLE_ZERO) {
tcon |= pwm_tcon_manulupdate(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
tcon &= ~pwm_tcon_manulupdate(s3c_pwm);
tcon |= pwm_tcon_autoreload(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
}
}
s3c_pwm->running = 1;
pwm_enable_cnt++;
spin_unlock_irqrestore(&pwm_spinlock, flags);
return 0;
}
static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *_pwm)
{
struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
int ret;
ret = tpu_pwm_timer_start(pwm);
if (ret < 0)
return ret;
/*
* To avoid running the timer when not strictly required, handle 0% and
* 100% duty cycles as fixed levels and stop the timer.
*/
if (pwm->duty == 0 || pwm->duty == pwm->period) {
tpu_pwm_set_pin(pwm, pwm->duty ?
TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
tpu_pwm_timer_stop(pwm);
}
return 0;
}
static int bfin_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
int duty_ns, int period_ns)
{
struct bfin_pwm *priv = pwm_get_chip_data(pwm);
unsigned long period, duty;
unsigned long long val;
val = (unsigned long long)get_sclk() * period_ns;
do_div(val, NSEC_PER_SEC);
period = val;
val = (unsigned long long)period * duty_ns;
do_div(val, period_ns);
duty = period - val;
if (duty >= period)
duty = period - 1;
set_gptimer_config(priv->pin, TIMER_MODE_PWM | TIMER_PERIOD_CNT);
set_gptimer_pwidth(priv->pin, duty);
set_gptimer_period(priv->pin, period);
return 0;
}
static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *_pwm,
int duty_ns, int period_ns)
{
static const unsigned int prescalers[] = { 1, 4, 16, 64 };
struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
struct tpu_device *tpu = to_tpu_device(chip);
unsigned int prescaler;
bool duty_only = false;
u32 clk_rate;
u32 period;
u32 duty;
int ret;
/*
* Pick a prescaler to avoid overflowing the counter.
* TODO: Pick the highest acceptable prescaler.
*/
clk_rate = clk_get_rate(tpu->clk);
for (prescaler = 0; prescaler < ARRAY_SIZE(prescalers); ++prescaler) {
period = clk_rate / prescalers[prescaler]
/ (NSEC_PER_SEC / period_ns);
if (period <= 0xffff)
break;
}
if (prescaler == ARRAY_SIZE(prescalers) || period == 0) {
dev_err(&tpu->pdev->dev, "clock rate mismatch\n");
return -ENOTSUPP;
}
if (duty_ns) {
duty = clk_rate / prescalers[prescaler]
/ (NSEC_PER_SEC / duty_ns);
if (duty > period)
return -EINVAL;
} else {
duty = 0;
}
dev_dbg(&tpu->pdev->dev,
"rate %u, prescaler %u, period %u, duty %u\n",
clk_rate, prescalers[prescaler], period, duty);
if (pwm->prescaler == prescaler && pwm->period == period)
duty_only = true;
pwm->prescaler = prescaler;
pwm->period = period;
pwm->duty = duty;
/* If the channel is disabled we're done. */
if (!test_bit(PWMF_ENABLED, &_pwm->flags))
return 0;
if (duty_only && pwm->timer_on) {
/*
* If only the duty cycle changed and the timer is already
* running, there's no need to reconfigure it completely, Just
* modify the duty cycle.
*/
tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty);
dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel,
pwm->duty);
} else {
/* Otherwise perform a full reconfiguration. */
ret = tpu_pwm_timer_start(pwm);
if (ret < 0)
return ret;
}
if (duty == 0 || duty == period) {
/*
* To avoid running the timer when not strictly required, handle
* 0% and 100% duty cycles as fixed levels and stop the timer.
*/
tpu_pwm_set_pin(pwm, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
tpu_pwm_timer_stop(pwm);
}
return 0;
}
static void bfin_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct bfin_pwm *priv = pwm_get_chip_data(pwm);
disable_gptimer(priv->pin);
}
static int s3c_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
int duty_ns, int period_ns)
{
struct s3c_chip *s3c = to_s3c_chip(chip);
struct s3c_pwm_device *s3c_pwm = pwm_get_chip_data(pwm);
void __iomem *reg_base = s3c->reg_base;
unsigned long tin_rate;
unsigned long tin_ns;
unsigned long period;
unsigned long flags;
unsigned long tcon;
unsigned long tcnt;
long tcmp;
enum duty_cycle duty_cycle;
unsigned int id = pwm->pwm;
/* We currently avoid using 64bit arithmetic by using the
* fact that anything faster than 1Hz is easily representable
* by 32bits. */
if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
return -ERANGE;
if (duty_ns > period_ns)
return -EINVAL;
if (period_ns == s3c_pwm->period_ns &&
duty_ns == s3c_pwm->duty_ns)
return 0;
period = NS_IN_HZ / period_ns;
/* Check to see if we are changing the clock rate of the PWM */
if (s3c_pwm->period_ns != period_ns && pwm_is_tdiv(s3c_pwm)) {
tin_rate = pwm_calc_tin(pwm, period);
clk_set_rate(s3c_pwm->clk_div, tin_rate);
tin_rate = clk_get_rate(s3c_pwm->clk_div);
s3c_pwm->period_ns = period_ns;
pwm_dbg(s3c, "tin_rate=%lu\n", tin_rate);
} else {
tin_rate = clk_get_rate(s3c_pwm->clk_tin);
}
if(!tin_rate)
return -EFAULT;
/* Note, counters count down */
tin_ns = NS_IN_HZ / tin_rate;
tcnt = DIV_ROUND_CLOSEST(period_ns, tin_ns);
tcmp = DIV_ROUND_CLOSEST(duty_ns, tin_ns);
if (tcnt <= 1) {
/* Too small to generate a pulse */
return -ERANGE;
}
pwm_dbg(s3c, "duty_ns=%d, period_ns=%d (%lu)\n",
duty_ns, period_ns, period);
if (tcmp == 0)
duty_cycle = DUTY_CYCLE_ZERO;
else if (tcmp == tcnt)
duty_cycle = DUTY_CYCLE_FULL;
else
duty_cycle = DUTY_CYCLE_PULSE;
tcmp = tcnt - tcmp;
/* the pwm hw only checks the compare register after a decrement,
so the pin never toggles if tcmp = tcnt */
if (tcmp == tcnt)
tcmp--;
/*
* PWM counts 1 hidden tick at the end of each period on S3C64XX and
* EXYNOS series, so tcmp and tcnt should be subtracted 1.
*/
if (!pwm_is_s3c24xx(s3c)) {
tcnt--;
/*
* tcmp can be -1. It appears 100% duty cycle and PWM never
* toggles when TCMPB is set to 0xFFFFFFFF (-1).
*/
tcmp--;
}
pwm_dbg(s3c, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
/* Update the PWM register block. */
spin_lock_irqsave(&pwm_spinlock, flags);
__raw_writel(tcmp, reg_base + REG_TCMPB(id));
__raw_writel(tcnt, reg_base + REG_TCNTB(id));
if (pwm_is_s3c24xx(s3c)) {
tcon = __raw_readl(reg_base + REG_TCON);
tcon |= pwm_tcon_manulupdate(s3c_pwm);
tcon |= pwm_tcon_autoreload(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
tcon &= ~pwm_tcon_manulupdate(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
} else {
tcon = __raw_readl(reg_base + REG_TCON);
if (s3c_pwm->running == 1 &&
tcon & pwm_tcon_start(s3c_pwm) &&
s3c_pwm->duty_cycle != duty_cycle) {
if (duty_cycle == DUTY_CYCLE_ZERO) {
tcon |= pwm_tcon_manulupdate(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
tcon &= ~pwm_tcon_manulupdate(s3c_pwm);
tcon &= ~pwm_tcon_autoreload(s3c_pwm);
} else {
tcon |= pwm_tcon_autoreload(s3c_pwm);
}
__raw_writel(tcon, reg_base + REG_TCON);
}
}
s3c_pwm->duty_ns = duty_ns;
s3c_pwm->period_ns = period_ns;
s3c_pwm->duty_cycle = duty_cycle;
spin_unlock_irqrestore(&pwm_spinlock, flags);
return 0;
}
