static int cam_cc_sdm845_probe(struct platform_device *pdev)
{
struct regmap *regmap;
struct alpha_pll_config cam_cc_pll_config = { };
regmap = qcom_cc_map(pdev, &cam_cc_sdm845_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
cam_cc_pll_config.l = 0x1f;
cam_cc_pll_config.alpha = 0x4000;
clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll_config);
cam_cc_pll_config.l = 0x2a;
cam_cc_pll_config.alpha = 0x1556;
clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll_config);
cam_cc_pll_config.l = 0x32;
cam_cc_pll_config.alpha = 0x0;
clk_fabia_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll_config);
cam_cc_pll_config.l = 0x14;
clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config);
return qcom_cc_really_probe(pdev, &cam_cc_sdm845_desc, regmap);
}
static int lcc_msm8960_probe(struct platform_device *pdev)
{
u32 val;
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &lcc_msm8960_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Use the correct frequency plan depending on speed of PLL4 */
val = regmap_read(regmap, 0x4, &val);
if (val == 0x12) {
slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
pcm_src.freq_tbl = clk_tbl_pcm_492;
}
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regmap_write(regmap, 0xc4, 0x1);
return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap);
}
int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return qcom_cc_really_probe(pdev, desc, regmap);
}
static int lcc_ipq806x_probe(struct platform_device *pdev)
{
u32 val;
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &lcc_ipq806x_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Configure the rate of PLL4 if the bootloader hasn't already */
val = regmap_read(regmap, 0x0, &val);
if (!val)
clk_pll_configure_sr(&pll4, regmap, &pll4_config, true);
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regmap_write(regmap, 0xc4, 0x1);
return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap);
}
static int gcc_mdm9615_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct regmap *regmap;
int ret;
int i;
regmap = qcom_cc_map(pdev, &gcc_mdm9615_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
for (i = 0; i < ARRAY_SIZE(gcc_mdm9615_hws); i++) {
ret = devm_clk_hw_register(dev, gcc_mdm9615_hws[i]);
if (ret)
return ret;
}
return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap);
}
