static int tcx_load(QEMUFile *f, void *opaque, int version_id)
{
TCXState *s = opaque;
uint32_t dummy;
if (version_id != 3 && version_id != 4)
return -EINVAL;
if (version_id == 3) {
qemu_get_be32s(f, &dummy);
qemu_get_be32s(f, &dummy);
qemu_get_be32s(f, &dummy);
}
qemu_get_be16s(f, &s->height);
qemu_get_be16s(f, &s->width);
qemu_get_be16s(f, &s->depth);
qemu_get_buffer(f, s->r, 256);
qemu_get_buffer(f, s->g, 256);
qemu_get_buffer(f, s->b, 256);
qemu_get_8s(f, &s->dac_index);
qemu_get_8s(f, &s->dac_state);
update_palette_entries(s, 0, 256);
if (s->depth == 24)
tcx24_invalidate_display(s);
else
tcx_invalidate_display(s);
return 0;
}
static int get_tlb(QEMUFile *f, void *pv, size_t size,
const VMStateField *field)
{
r4k_tlb_t *v = pv;
uint16_t flags;
qemu_get_betls(f, &v->VPN);
qemu_get_be32s(f, &v->PageMask);
qemu_get_be16s(f, &v->ASID);
qemu_get_be16s(f, &flags);
v->G = (flags >> 10) & 1;
v->C0 = (flags >> 7) & 3;
v->C1 = (flags >> 4) & 3;
v->V0 = (flags >> 3) & 1;
v->V1 = (flags >> 2) & 1;
v->D0 = (flags >> 1) & 1;
v->D1 = (flags >> 0) & 1;
v->EHINV = (flags >> 15) & 1;
v->RI1 = (flags >> 14) & 1;
v->RI0 = (flags >> 13) & 1;
v->XI1 = (flags >> 12) & 1;
v->XI0 = (flags >> 11) & 1;
qemu_get_be64s(f, &v->PFN[0]);
qemu_get_be64s(f, &v->PFN[1]);
return 0;
}
int virtio_load(VirtIODevice *vdev, QEMUFile *f)
{
int num, i, ret;
uint32_t features;
uint32_t supported_features =
vdev->binding->get_features(vdev->binding_opaque);
if (vdev->binding->load_config) {
ret = vdev->binding->load_config(vdev->binding_opaque, f);
if (ret)
return ret;
}
qemu_get_8s(f, &vdev->status);
qemu_get_8s(f, &vdev->isr);
qemu_get_be16s(f, &vdev->queue_sel);
qemu_get_be32s(f, &features);
if (features & ~supported_features) {
fprintf(stderr, "Features 0x%x unsupported. Allowed features: 0x%x\n",
features, supported_features);
return -1;
}
vdev->guest_features = features;
vdev->config_len = qemu_get_be32(f);
qemu_get_buffer(f, vdev->config, vdev->config_len);
num = qemu_get_be32(f);
for (i = 0; i < num; i++) {
vdev->vq[i].vring.num = qemu_get_be32(f);
vdev->vq[i].pa = qemu_get_be64(f);
qemu_get_be16s(f, &vdev->vq[i].last_avail_idx);
if (vdev->vq[i].pa) {
virtqueue_init(&vdev->vq[i]);
}
if (vdev->binding->load_queue) {
ret = vdev->binding->load_queue(vdev->binding_opaque, i, f);
if (ret)
return ret;
}
}
virtio_notify_vector(vdev, VIRTIO_NO_VECTOR);
return 0;
}
static int vmmouse_load(QEMUFile *f, void *opaque, int version_id)
{
VMMouseState *s = (VMMouseState *)opaque;
int i;
if (version_id != 0)
return -EINVAL;
if (qemu_get_be32(f) != VMMOUSE_QUEUE_SIZE)
return -EINVAL;
for (i = 0; i < VMMOUSE_QUEUE_SIZE; i++)
qemu_get_be32s(f, &s->queue[i]);
qemu_get_be16s(f, &s->nb_queue);
qemu_get_be16s(f, &s->status);
qemu_get_8s(f, &s->absolute);
vmmouse_update_handler(s);
return 0;
}
static int get_uint16_equal(QEMUFile *f, void *pv, size_t size)
{
uint16_t *v = pv;
uint16_t v2;
qemu_get_be16s(f, &v2);
if (*v == v2) {
return 0;
}
return -EINVAL;
}
static int get_uint16_equal(QEMUFile *f, void *pv, size_t size,
VMStateField *field)
{
uint16_t *v = pv;
uint16_t v2;
qemu_get_be16s(f, &v2);
if (*v == v2) {
return 0;
}
error_report("%x != %x", *v, v2);
return -EINVAL;
}
static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
int i;
qemu_get_be32s(f, &s->status);
qemu_get_be32s(f, &s->clkrt);
qemu_get_be32s(f, &s->spi);
qemu_get_be32s(f, &s->cmdat);
qemu_get_be32s(f, &s->resp_tout);
qemu_get_be32s(f, &s->read_tout);
s->blklen = qemu_get_be32(f);
s->numblk = qemu_get_be32(f);
qemu_get_be32s(f, &s->intmask);
qemu_get_be32s(f, &s->intreq);
s->cmd = qemu_get_be32(f);
qemu_get_be32s(f, &s->arg);
s->cmdreq = qemu_get_be32(f);
s->active = qemu_get_be32(f);
s->bytesleft = qemu_get_be32(f);
s->tx_len = qemu_get_byte(f);
s->tx_start = 0;
if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0)
return -EINVAL;
for (i = 0; i < s->tx_len; i ++)
s->tx_fifo[i] = qemu_get_byte(f);
s->rx_len = qemu_get_byte(f);
s->rx_start = 0;
if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0)
return -EINVAL;
for (i = 0; i < s->rx_len; i ++)
s->rx_fifo[i] = qemu_get_byte(f);
s->resp_len = qemu_get_byte(f);
if (s->resp_len > 9 || s->resp_len < 0)
return -EINVAL;
for (i = s->resp_len; i < 9; i ++)
qemu_get_be16s(f, &s->resp_fifo[i]);
return 0;
}
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
CPUMIPSState *env = opaque;
int i;
if (version_id != 3)
return -EINVAL;
/* Load active TC */
load_tc(f, &env->active_tc);
/* Load active FPU */
load_fpu(f, &env->active_fpu);
/* Load MVP */
qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
/* Load TLB */
qemu_get_be32s(f, &env->tlb->nb_tlb);
for(i = 0; i < MIPS_TLB_MAX; i++) {
uint16_t flags;
uint8_t asid;
qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
qemu_get_8s(f, &asid);
env->tlb->mmu.r4k.tlb[i].ASID = asid;
qemu_get_be16s(f, &flags);
env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1;
env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
}
/* Load CPU metastate */
qemu_get_be32s(f, &env->current_tc);
qemu_get_be32s(f, &env->current_fpu);
qemu_get_sbe32s(f, &env->error_code);
qemu_get_be32s(f, &env->hflags);
qemu_get_betls(f, &env->btarget);
qemu_get_sbe32s(f, &i);
env->bcond = i;
/* Load remaining CP1 registers */
qemu_get_sbe32s(f, &env->CP0_Index);
qemu_get_sbe32s(f, &env->CP0_Random);
qemu_get_sbe32s(f, &env->CP0_VPEControl);
qemu_get_sbe32s(f, &env->CP0_VPEConf0);
qemu_get_sbe32s(f, &env->CP0_VPEConf1);
qemu_get_betls(f, &env->CP0_YQMask);
qemu_get_betls(f, &env->CP0_VPESchedule);
qemu_get_betls(f, &env->CP0_VPEScheFBack);
qemu_get_sbe32s(f, &env->CP0_VPEOpt);
qemu_get_betls(f, &env->CP0_EntryLo0);
qemu_get_betls(f, &env->CP0_EntryLo1);
qemu_get_betls(f, &env->CP0_Context);
qemu_get_sbe32s(f, &env->CP0_PageMask);
qemu_get_sbe32s(f, &env->CP0_PageGrain);
qemu_get_sbe32s(f, &env->CP0_Wired);
qemu_get_sbe32s(f, &env->CP0_SRSConf0);
qemu_get_sbe32s(f, &env->CP0_SRSConf1);
qemu_get_sbe32s(f, &env->CP0_SRSConf2);
qemu_get_sbe32s(f, &env->CP0_SRSConf3);
qemu_get_sbe32s(f, &env->CP0_SRSConf4);
qemu_get_sbe32s(f, &env->CP0_HWREna);
qemu_get_betls(f, &env->CP0_BadVAddr);
qemu_get_sbe32s(f, &env->CP0_Count);
qemu_get_betls(f, &env->CP0_EntryHi);
qemu_get_sbe32s(f, &env->CP0_Compare);
qemu_get_sbe32s(f, &env->CP0_Status);
qemu_get_sbe32s(f, &env->CP0_IntCtl);
qemu_get_sbe32s(f, &env->CP0_SRSCtl);
qemu_get_sbe32s(f, &env->CP0_SRSMap);
qemu_get_sbe32s(f, &env->CP0_Cause);
qemu_get_betls(f, &env->CP0_EPC);
qemu_get_sbe32s(f, &env->CP0_PRid);
qemu_get_sbe32s(f, &env->CP0_EBase);
qemu_get_sbe32s(f, &env->CP0_Config0);
qemu_get_sbe32s(f, &env->CP0_Config1);
qemu_get_sbe32s(f, &env->CP0_Config2);
qemu_get_sbe32s(f, &env->CP0_Config3);
qemu_get_sbe32s(f, &env->CP0_Config6);
qemu_get_sbe32s(f, &env->CP0_Config7);
qemu_get_betls(f, &env->lladdr);
for(i = 0; i < 8; i++)
qemu_get_betls(f, &env->CP0_WatchLo[i]);
for(i = 0; i < 8; i++)
qemu_get_sbe32s(f, &env->CP0_WatchHi[i]);
qemu_get_betls(f, &env->CP0_XContext);
qemu_get_sbe32s(f, &env->CP0_Framemask);
qemu_get_sbe32s(f, &env->CP0_Debug);
qemu_get_betls(f, &env->CP0_DEPC);
qemu_get_sbe32s(f, &env->CP0_Performance0);
qemu_get_sbe32s(f, &env->CP0_TagLo);
qemu_get_sbe32s(f, &env->CP0_DataLo);
qemu_get_sbe32s(f, &env->CP0_TagHi);
qemu_get_sbe32s(f, &env->CP0_DataHi);
qemu_get_betls(f, &env->CP0_ErrorEPC);
qemu_get_sbe32s(f, &env->CP0_DESAVE);
/* Load inactive TC state */
for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
load_tc(f, &env->tcs[i]);
for (i = 0; i < MIPS_FPU_MAX; i++)
load_fpu(f, &env->fpus[i]);
/* XXX: ensure compatiblity for halted bit ? */
tlb_flush(env, 1);
return 0;
}
static int get_uint16(QEMUFile *f, void *pv, size_t size)
{
uint16_t *v = pv;
qemu_get_be16s(f, v);
return 0;
}
