static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque) { PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; int i; qemu_put_be32(f, s->irqlevel); qemu_put_be32(f, s->transp); for (i = 0; i < 6; i ++) qemu_put_be32s(f, &s->control[i]); for (i = 0; i < 2; i ++) qemu_put_be32s(f, &s->status[i]); for (i = 0; i < 2; i ++) qemu_put_be32s(f, &s->ovl1c[i]); for (i = 0; i < 2; i ++) qemu_put_be32s(f, &s->ovl2c[i]); qemu_put_be32s(f, &s->ccr); qemu_put_be32s(f, &s->cmdcr); qemu_put_be32s(f, &s->trgbr); qemu_put_be32s(f, &s->tcr); qemu_put_be32s(f, &s->liidr); qemu_put_8s(f, &s->bscntr); for (i = 0; i < 7; i ++) { qemu_put_betl(f, s->dma_ch[i].branch); qemu_put_byte(f, s->dma_ch[i].up); qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer)); qemu_put_betl(f, s->dma_ch[i].descriptor); qemu_put_betl(f, s->dma_ch[i].source); qemu_put_be32s(f, &s->dma_ch[i].id); qemu_put_be32s(f, &s->dma_ch[i].command); } }
static void cpu_put_seg(QEMUFile *f, SegmentCache *dt) { qemu_put_be32(f, dt->selector); qemu_put_betl(f, dt->base); qemu_put_be32(f, dt->limit); qemu_put_be32(f, dt->flags); }