int main(void)
{
qm_mpr_config_t cfg;
uint8_t lower_bound;
uint32_t heap_offset, mpr_base;
QM_PUTS("Starting: MPR");
/*
* The MPR is located in the heap in order to ensure it doesn't clash
* with anything so it is necessary to calculate the page number that
* corresponds to the start of the heap.
*/
heap_offset = (uint32_t)&__heap;
lower_bound = (uint8_t)((heap_offset - SRAM_BASE) / MPR_PAGE_SIZE) + 1;
/* Calculate the physical address of the start of the MPR. */
mpr_base = SRAM_BASE + (lower_bound * MPR_PAGE_SIZE);
/* Request the IRQ. */
qm_irq_request(QM_IRQ_SRAM_MPR_0_INT, qm_sram_mpr_0_isr);
/* Set the violation policy to trigger an interrupt. */
qm_mpr_set_violation_policy(MPR_VIOL_MODE_INTERRUPT,
mpr_example_callback, NULL);
/* Configure MPR to allow R/W from DMA agent only. */
cfg.en_lock_mask = QM_SRAM_MPR_EN_MASK_ENABLE;
cfg.agent_read_en_mask = QM_SRAM_MPR_AGENT_MASK_DMA;
cfg.agent_write_en_mask = QM_SRAM_MPR_AGENT_MASK_DMA;
cfg.up_bound = lower_bound;
cfg.low_bound = lower_bound;
qm_mpr_set_config(QM_MPR_0, &cfg);
/* Trigger a violation event by attempting a write inside the MPR. */
REG_VAL(mpr_base + 1) = 0xff;
/* Wait for the callback to be invoked. */
while (false == callback_invoked)
;
QM_PUTS("MPR Violation!");
QM_PUTS("Finished: MPR");
return 0;
}
/* QMSI MPR sample application: this example uses an MPR to pretect a 1kB page
of SRAM, and then triggers an MPR violation interrupt. */
int main(void)
{
qm_mpr_config_t cfg;
uint8_t lower_bound;
uint32_t heap_offset, sram_base, mpr_base;
QM_PUTS("\nMPR example app start");
/* we're going to put this MPR in the heap, to ensure it doesn't clash
* with anything else, so we need to figure out the page number that
* corresponds to the start of the heap */
heap_offset = (uint32_t)&__heap;
/* the IDT lives at the start of SRAM, so __idt_start gives us the SRAM
* base address in the Lakemont memory map */
sram_base = (uint32_t)&__idt_start;
lower_bound = (uint8_t)((heap_offset - sram_base) / MPR_PAGE_SIZE) + 1;
/* get the Lakemont physical address of the start of the MPR */
mpr_base = sram_base + (lower_bound * MPR_PAGE_SIZE);
/* Set the violation policy to trigger an interrupt */
qm_irq_request(QM_IRQ_SRAM, qm_mpr_isr);
qm_mpr_set_violation_policy(MPR_VIOL_MODE_INTERRUPT,
mpr_example_callback);
/* Configure MPR to allow R/W from DMA agent */
cfg.en_lock_mask = QM_SRAM_MPR_EN_MASK_ENABLE;
cfg.agent_read_en_mask = QM_SRAM_MPR_AGENT_MASK_DMA;
cfg.agent_write_en_mask = QM_SRAM_MPR_AGENT_MASK_DMA;
cfg.up_bound = lower_bound;
cfg.low_bound = lower_bound;
qm_mpr_set_config(QM_MPR_0, &cfg);
/* trigger a violation event by attempting a write inside the MPR */
REG_VAL(mpr_base + 1) = 0xff;
QM_PUTS("MPR example app complete");
return 0;
}
