void r600_context_gfx_flush(void *context, unsigned flags,
struct pipe_fence_handle **fence)
{
struct r600_context *ctx = context;
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
if (cs->cdw == ctx->b.initial_gfx_cs_size && !fence)
return;
r600_preflush_suspend_features(&ctx->b);
/* flush the framebuffer cache */
ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV |
R600_CONTEXT_FLUSH_AND_INV_CB |
R600_CONTEXT_FLUSH_AND_INV_DB |
R600_CONTEXT_FLUSH_AND_INV_CB_META |
R600_CONTEXT_FLUSH_AND_INV_DB_META |
R600_CONTEXT_WAIT_3D_IDLE |
R600_CONTEXT_WAIT_CP_DMA_IDLE;
r600_flush_emit(ctx);
/* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
if (ctx->b.chip_class == R600) {
radeon_set_context_reg(cs, R_028350_SX_MISC, 0);
}
/* force to keep tiling flags */
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
/* Flush the CS. */
ctx->b.ws->cs_flush(cs, flags, fence);
r600_begin_new_cs(ctx);
}
void r600_context_gfx_flush(void *context, unsigned flags,
struct pipe_fence_handle **fence)
{
struct r600_context *ctx = context;
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
struct radeon_winsys *ws = ctx->b.ws;
if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size) &&
(!fence || ctx->b.last_gfx_fence)) {
if (fence)
ws->fence_reference(fence, ctx->b.last_gfx_fence);
if (!(flags & RADEON_FLUSH_ASYNC))
ws->cs_sync_flush(cs);
return;
}
r600_preflush_suspend_features(&ctx->b);
/* flush the framebuffer cache */
ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV |
R600_CONTEXT_FLUSH_AND_INV_CB |
R600_CONTEXT_FLUSH_AND_INV_DB |
R600_CONTEXT_FLUSH_AND_INV_CB_META |
R600_CONTEXT_FLUSH_AND_INV_DB_META |
R600_CONTEXT_WAIT_3D_IDLE |
R600_CONTEXT_WAIT_CP_DMA_IDLE;
r600_flush_emit(ctx);
/* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
if (ctx->b.chip_class == R600) {
radeon_set_context_reg(cs, R_028350_SX_MISC, 0);
}
/* Flush the CS. */
ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
if (fence)
ws->fence_reference(fence, ctx->b.last_gfx_fence);
ctx->b.num_gfx_cs_flushes++;
r600_begin_new_cs(ctx);
}
static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
{
struct r600_context *rctx = CALLOC_STRUCT(r600_context);
struct r600_screen* rscreen = (struct r600_screen *)screen;
struct radeon_winsys *ws = rscreen->b.ws;
if (rctx == NULL)
return NULL;
rctx->b.b.screen = screen;
rctx->b.b.priv = priv;
rctx->b.b.destroy = r600_destroy_context;
if (!r600_common_context_init(&rctx->b, &rscreen->b))
goto fail;
rctx->screen = rscreen;
rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
r600_init_blit_functions(rctx);
if (rscreen->b.info.has_uvd) {
rctx->b.b.create_video_codec = r600_uvd_create_decoder;
rctx->b.b.create_video_buffer = r600_video_buffer_create;
} else {
rctx->b.b.create_video_codec = vl_create_decoder;
rctx->b.b.create_video_buffer = vl_video_buffer_create;
}
r600_init_common_state_functions(rctx);
switch (rctx->b.chip_class) {
case R600:
case R700:
r600_init_state_functions(rctx);
r600_init_atom_start_cs(rctx);
rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
: r600_create_resolve_blend(rctx);
rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
rctx->b.family == CHIP_RV620 ||
rctx->b.family == CHIP_RS780 ||
rctx->b.family == CHIP_RS880 ||
rctx->b.family == CHIP_RV710);
break;
case EVERGREEN:
case CAYMAN:
evergreen_init_state_functions(rctx);
evergreen_init_atom_start_cs(rctx);
evergreen_init_atom_start_compute_cs(rctx);
rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
rctx->b.family == CHIP_PALM ||
rctx->b.family == CHIP_SUMO ||
rctx->b.family == CHIP_SUMO2 ||
rctx->b.family == CHIP_CAICOS ||
rctx->b.family == CHIP_CAYMAN ||
rctx->b.family == CHIP_ARUBA);
break;
default:
R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
goto fail;
}
rctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX,
r600_context_gfx_flush, rctx,
rscreen->b.trace_bo ?
rscreen->b.trace_bo->cs_buf : NULL);
rctx->b.rings.gfx.flush = r600_context_gfx_flush;
rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
0, PIPE_USAGE_DEFAULT, FALSE);
if (!rctx->allocator_fetch_shader)
goto fail;
rctx->isa = calloc(1, sizeof(struct r600_isa));
if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
goto fail;
rctx->blitter = util_blitter_create(&rctx->b.b);
if (rctx->blitter == NULL)
goto fail;
util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
rctx->blitter->draw_rectangle = r600_draw_rectangle;
r600_begin_new_cs(rctx);
r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
rctx->dummy_pixel_shader =
util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
TGSI_SEMANTIC_GENERIC,
TGSI_INTERPOLATE_CONSTANT);
rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
return &rctx->b.b;
fail:
r600_destroy_context(&rctx->b.b);
return NULL;
}
static struct pipe_context *r600_create_context(struct pipe_screen *screen,
void *priv, unsigned flags)
{
struct r600_context *rctx = CALLOC_STRUCT(r600_context);
struct r600_screen* rscreen = (struct r600_screen *)screen;
struct radeon_winsys *ws = rscreen->b.ws;
if (!rctx)
return NULL;
rctx->b.b.screen = screen;
assert(!priv);
rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
rctx->b.b.destroy = r600_destroy_context;
rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
goto fail;
rctx->screen = rscreen;
LIST_INITHEAD(&rctx->texture_buffers);
r600_init_blit_functions(rctx);
if (rscreen->b.info.has_hw_decode) {
rctx->b.b.create_video_codec = r600_uvd_create_decoder;
rctx->b.b.create_video_buffer = r600_video_buffer_create;
} else {
rctx->b.b.create_video_codec = vl_create_decoder;
rctx->b.b.create_video_buffer = vl_video_buffer_create;
}
if (getenv("R600_TRACE"))
rctx->is_debug = true;
r600_init_common_state_functions(rctx);
switch (rctx->b.chip_class) {
case R600:
case R700:
r600_init_state_functions(rctx);
r600_init_atom_start_cs(rctx);
rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
: r600_create_resolve_blend(rctx);
rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
rctx->b.family == CHIP_RV620 ||
rctx->b.family == CHIP_RS780 ||
rctx->b.family == CHIP_RS880 ||
rctx->b.family == CHIP_RV710);
break;
case EVERGREEN:
case CAYMAN:
evergreen_init_state_functions(rctx);
evergreen_init_atom_start_cs(rctx);
evergreen_init_atom_start_compute_cs(rctx);
rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
rctx->b.family == CHIP_PALM ||
rctx->b.family == CHIP_SUMO ||
rctx->b.family == CHIP_SUMO2 ||
rctx->b.family == CHIP_CAICOS ||
rctx->b.family == CHIP_CAYMAN ||
rctx->b.family == CHIP_ARUBA);
break;
default:
R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
goto fail;
}
rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
r600_context_gfx_flush, rctx);
rctx->b.gfx.flush = r600_context_gfx_flush;
rctx->allocator_fetch_shader =
u_suballocator_create(&rctx->b.b, 64 * 1024,
0, PIPE_USAGE_DEFAULT, 0, FALSE);
if (!rctx->allocator_fetch_shader)
goto fail;
rctx->isa = calloc(1, sizeof(struct r600_isa));
if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
goto fail;
if (rscreen->b.debug_flags & DBG_FORCE_DMA)
rctx->b.b.resource_copy_region = rctx->b.dma_copy;
rctx->blitter = util_blitter_create(&rctx->b.b);
if (rctx->blitter == NULL)
goto fail;
util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
rctx->blitter->draw_rectangle = r600_draw_rectangle;
r600_begin_new_cs(rctx);
rctx->dummy_pixel_shader =
util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
TGSI_SEMANTIC_GENERIC,
TGSI_INTERPOLATE_CONSTANT);
rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
return &rctx->b.b;
fail:
r600_destroy_context(&rctx->b.b);
return NULL;
}
void r600_context_gfx_flush(void *context, unsigned flags,
struct pipe_fence_handle **fence)
{
struct r600_context *ctx = context;
struct radeon_cmdbuf *cs = ctx->b.gfx.cs;
struct radeon_winsys *ws = ctx->b.ws;
if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
return;
if (r600_check_device_reset(&ctx->b))
return;
r600_preflush_suspend_features(&ctx->b);
/* flush the framebuffer cache */
ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV |
R600_CONTEXT_FLUSH_AND_INV_CB |
R600_CONTEXT_FLUSH_AND_INV_DB |
R600_CONTEXT_FLUSH_AND_INV_CB_META |
R600_CONTEXT_FLUSH_AND_INV_DB_META |
R600_CONTEXT_WAIT_3D_IDLE |
R600_CONTEXT_WAIT_CP_DMA_IDLE;
r600_flush_emit(ctx);
if (ctx->trace_buf)
eg_trace_emit(ctx);
/* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
if (ctx->b.chip_class == R600) {
radeon_set_context_reg(cs, R_028350_SX_MISC, 0);
}
if (ctx->is_debug) {
/* Save the IB for debug contexts. */
radeon_clear_saved_cs(&ctx->last_gfx);
radeon_save_cs(ws, cs, &ctx->last_gfx, true);
r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf);
r600_resource_reference(&ctx->trace_buf, NULL);
}
/* Flush the CS. */
ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
if (fence)
ws->fence_reference(fence, ctx->b.last_gfx_fence);
ctx->b.num_gfx_cs_flushes++;
if (ctx->is_debug) {
if (!ws->fence_wait(ws, ctx->b.last_gfx_fence, 10000000)) {
const char *fname = getenv("R600_TRACE");
if (!fname)
exit(-1);
FILE *fl = fopen(fname, "w+");
if (fl) {
eg_dump_debug_state(&ctx->b.b, fl, 0);
fclose(fl);
} else
perror(fname);
exit(-1);
}
}
r600_begin_new_cs(ctx);
}
