static int spic_transfer(const u8 *cmd, int n_cmd, u8 *buf, int n_buf, int flag)
{
int retval = -1;
//spic_init();
ra_dbg("cmd(%x): %x %x %x %x , buf:%x len:%x, flag:%s \n",
n_cmd, cmd[0], cmd[1], cmd[2], cmd[3],
(buf)? (*buf) : 0, n_buf,
(flag == SPIC_READ_BYTES)? "read" : "write");
#if defined(CONFIG_RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)||defined(CONFIG_RALINK_SLIC_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
ra_outl(RT2880_SPI_ARB_REG, SPIARB_ARB_EN|(SPIARB_SPI1_ACTIVE_MODE<<1)| SPIARB_SPI0_ACTIVE_MODE);
#if defined(CONFIG_RALINK_SPI_CS1_HIGH_ACTIVE)
ra_and(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE));
#else
ra_or(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE)&0x01);
#endif
#endif
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV | SPICFG_SPICLKPOL );
// assert CS and we are already CLK normal high
ra_and(RT2880_SPICTL_REG, ~(SPICTL_SPIENA_HIGH));
// write command
for (retval = 0; retval < n_cmd; retval++) {
ra_outl(RT2880_SPIDATA_REG, cmd[retval]);
ra_or(RT2880_SPICTL_REG, SPICTL_STARTWR);
if (spic_busy_wait()) {
retval = -1;
goto end_trans;
}
}
// read / write data
if (flag & SPIC_READ_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_or(RT2880_SPICTL_REG, SPICTL_STARTRD);
if (spic_busy_wait())
goto end_trans;
buf[retval] = (u8) ra_inl(RT2880_SPIDATA_REG);
}
}
else if (flag & SPIC_WRITE_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_outl(RT2880_SPIDATA_REG, buf[retval]);
ra_or(RT2880_SPICTL_REG, SPICTL_STARTWR);
if (spic_busy_wait())
goto end_trans;
}
}
end_trans:
// de-assert CS and
ra_or (RT2880_SPICTL_REG, (SPICTL_SPIENA_HIGH));
return retval;
}
int spic_init(void)
{
// use normal(SPI) mode instead of GPIO mode
ra_and(RT2880_GPIOMODE_REG, ~(1 << 1));
#if defined (RT6855_ASIC_BOARD) || defined (RT6855_FPGA_BOARD)
ra_or(RT2880_GPIOMODE_REG, (1 << 11));
#endif
// reset spi block
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
#if defined(RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
RT2880_REG(RT2880_SPI_ARB_REG) = SPIARB_ARB_EN | (SPIARB_SPI1_ACTIVE_MODE <<1) | SPIARB_SPI0_ACTIVE_MODE;
RT2880_REG(RT2880_SPI0_CTL_REG) = (~SPIARB_SPI0_ACTIVE_MODE)&0x1; //disable first
RT2880_REG(RT2880_SPI1_CTL_REG) = (~SPIARB_SPI1_ACTIVE_MODE)&0x1; //disable first
#endif
// FIXME, clk_div should depend on spi-flash.
#ifdef ADDR_4B // use 4 byte address mode
ra_outl(RT2880_SPI0_CFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLK_DIV8 | SPICFG_SPICLKPOL | SPICFG_ADDRMODE);
#else
ra_outl(RT2880_SPI0_CFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLK_DIV8 | SPICFG_SPICLKPOL);
#endif
// set idle state
ra_outl(RT2880_SPI0_CTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / ((mips_bus_feq / 1000 / 1000 / SPICFG_SPICLK_DIV8) )) >> 1 ;
printf("spi_wait_nsec: %x \n", spi_wait_nsec);
return 0;
}
/*
* @cmd: command and address
* @n_cmd: size of command, in bytes
* @buf: buffer into which data will be read/written
* @n_buf: size of buffer, in bytes
* @flag: tag as READ/WRITE
*
* @return: if write_onlu, -1 means write fail, or return writing counter.
* @return: if read, -1 means read fail, or return reading counter.
*/
static int spic_transfer(const u8 *cmd, int n_cmd, u8 *buf, int n_buf, int flag)
{
int retval = -1;
/*
ra_dbg("cmd(%x): %x %x %x %x , buf:%x len:%x, flag:%s \n",
n_cmd, cmd[0], cmd[1], cmd[2], cmd[3],
(buf)? (*buf) : 0, n_buf,
(flag == SPIC_READ_BYTES)? "read" : "write");
*/
// assert CS and we are already CLK normal high
ra_and(RT2880_SPI0_CTL_REG, ~(SPICTL_SPIENA_HIGH));
// write command
for (retval = 0; retval < n_cmd; retval++) {
ra_outl(RT2880_SPI0_DATA_REG, cmd[retval]);
ra_or(RT2880_SPI0_CTL_REG, SPICTL_STARTWR);
if (spic_busy_wait()) {
retval = -1;
goto end_trans;
}
}
// read / write data
if (flag & SPIC_READ_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_or(RT2880_SPI0_CTL_REG, SPICTL_STARTRD);
#ifndef READ_BY_PAGE
if (n_cmd != 1 && (retval & 0xffff) == 0) {
printf(".");
}
#endif
if (spic_busy_wait()) {
printf("\n");
goto end_trans;
}
buf[retval] = (u8) ra_inl(RT2880_SPI0_DATA_REG);
}
}
else if (flag & SPIC_WRITE_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_outl(RT2880_SPI0_DATA_REG, buf[retval]);
ra_or(RT2880_SPI0_CTL_REG, SPICTL_STARTWR);
if (spic_busy_wait()) {
goto end_trans;
}
}
}
end_trans:
// de-assert CS and
ra_or (RT2880_SPI0_CTL_REG, (SPICTL_SPIENA_HIGH));
return retval;
}
int spic_init(void)
{
// GPIO-SPI mode
ra_and(RALINK_REG_GPIOMODE, ~(1 << 1)); //use normal(SPI) mode instead of GPIO mode
/* reset spi block */
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
udelay(1);
#if defined(CONFIG_RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)||defined(CONFIG_RALINK_SLIC_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
ra_outl(RT2880_SPI_ARB_REG, SPIARB_ARB_EN|(SPIARB_SPI1_ACTIVE_MODE<<1)| SPIARB_SPI0_ACTIVE_MODE);
ra_outl(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE)&0x1);
#endif
ra_outl(RT2880_SPI0_CTL_REG, (~SPIARB_SPI0_ACTIVE_MODE)&0x1);
// FIXME, clk_div should depend on spi-flash.
// mode 0 (SPICLKPOL = 0) & (RXCLKEDGE_FALLING = 0)
// mode 3 (SPICLKPOL = 1) & (RXCLKEDGE_FALLING = 0)
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV | SPICFG_SPICLKPOL );
// set idle state
ra_outl(RT2880_SPICTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / ((get_surfboard_sysclk() / 1000 / 1000 / CFG_CLK_DIV) )) >> 1 ;
//printk("spi_wait_nsec: %x \n", spi_wait_nsec);
return 0;
}
int spic_init(void)
{
/* use normal SPI mode instead of GPIO mode */
ra_and(RALINK_REG_GPIOMODE, ~(RALINK_GPIOMODE_SPI));
/* reset spi block */
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
udelay(1);
#if defined(CONFIG_RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)||defined(CONFIG_RALINK_SLIC_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
ra_outl(RT2880_SPI_ARB_REG, SPIARB_ARB_EN|(SPIARB_SPI1_ACTIVE_MODE<<1)| SPIARB_SPI0_ACTIVE_MODE);
ra_outl(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE)&0x1);
#endif
ra_outl(RT2880_SPI0_CTL_REG, (~SPIARB_SPI0_ACTIVE_MODE)&0x1);
#if !defined (COMMAND_MODE)
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_RXCLKEDGE_FALLING | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV);
#else
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLKPOL | CFG_CLK_DIV );
#endif
// set idle state
ra_outl(RT2880_SPICTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / (128 / (CFG_CLK_DIV+1)) ) >> 1;
printk("Ralink SPI flash driver, SPI clock: %dMHz\n", (get_surfboard_sysclk() / 1000000) >> (CFG_CLK_DIV+1));
return 0;
}
void spic_init(void)
{
u32 clk_sys, clk_div, reg;
#if defined (CONFIG_RALINK_MT7621)
clk_sys = 125; /* bclk = 125MHz */
#if defined (CONFIG_MTD_SPI_FAST_CLOCK)
clk_div = 4; /* bclk/4 -> 31.25 MHz */
#else
clk_div = 5; /* bclk/5 -> 25 MHz */
#endif
#elif defined (CONFIG_RALINK_MT7628)
clk_sys = get_surfboard_sysclk() / 1000000;
#if defined (CONFIG_MTD_SPI_FAST_CLOCK)
clk_div = 5; /* hclk/5 -> 40 MHz */
#else
clk_div = 8; /* hclk/8 -> 25 MHz */
#endif
#endif
reg = ra_inl(SPI_REG_MASTER);
reg &= ~(0x7);
reg &= ~(0x0fff << 16);
reg |= ((clk_div - 2) << 16);
ra_outl(SPI_REG_MASTER, reg);
#ifdef TEST_CS1_FLASH
#if defined (CONFIG_RALINK_MT7628)
ra_and(RALINK_REG_GPIOMODE, ~(3 << 4));
#endif
ra_or(SPI_REG_MASTER, (1 << 29));
#endif
printk("Ralink SPI flash driver, SPI clock: %dMHz\n", clk_sys / clk_div);
}
void spic_init(void)
{
#if defined (MT7621_ASIC_BOARD) || defined (MT7628_ASIC_BOARD)
u32 clk_sys, clk_div, reg;
clk_sys = mips_bus_feq / 1000000;
#if defined (MT7621_ASIC_BOARD)
// hclk = 220 MHz
#ifdef SPI_FAST_CLOCK
clk_div = 5; /* hclk/5 -> 44.0 MHz */
#else
clk_div = 7; /* hclk/7 -> 31.4 MHz */
#endif
#else
// hclk = 193/191 MHz
#ifdef SPI_FAST_CLOCK
clk_div = 4; /* hclk/4 -> 48.3 MHz */
#else
clk_div = 6; /* hclk/6 -> 32.2 MHz */
#endif
#endif
reg = ra_inl(SPI_REG_MASTER);
reg &= ~(0x7);
reg &= ~(0xfff << 16);
reg |= ((clk_div - 2) << 16);
ra_outl(SPI_REG_MASTER, reg);
printf("%s SPI flash driver, SPI clock: %dMHz\n", RLT_MTK_VENDOR_NAME, clk_sys / clk_div);
#elif defined (RT6855_ASIC_BOARD) || defined (RT6855_FPGA_BOARD)
// enable SMC bank 0 alias addressing
ra_or(RALINK_SYSCTL_BASE + 0x38, 0x80000000);
#endif
}
unsigned long ranand_init(void)
{
//maks sure gpio-0 is input
ra_outl(RALINK_PIO_BASE+0x24, ra_inl(RALINK_PIO_BASE+0x24) & ~0x01);
//set WP to high
ra_or(NFC_CTRL, 0x01);
if (nfc_all_reset() != 0)
return -1;
return CFG_CHIPSIZE;
}
int spic_init(void)
{
// use normal(SPI) mode instead of GPIO mode
#if defined (RT6855_ASIC_BOARD) || defined (RT6855_FPGA_BOARD)
ra_or(RT2880_GPIOMODE_REG, (1 << 11));
#elif defined (MT7620_ASIC_BOARD) || defined (MT7620_FPGA_BOARD)
ra_and(RT2880_GPIOMODE_REG, ~(1 << 11));
#else
ra_and(RT2880_GPIOMODE_REG, ~(1 << 1));
#endif
// reset spi block
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
udelay(1);
#if defined(RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
RT2880_REG(RT2880_SPI_ARB_REG) = SPIARB_ARB_EN | (SPIARB_SPI1_ACTIVE_MODE <<1) | SPIARB_SPI0_ACTIVE_MODE;
RT2880_REG(RT2880_SPI0_CTL_REG) = (~SPIARB_SPI0_ACTIVE_MODE)&0x1; //disable first
RT2880_REG(RT2880_SPI1_CTL_REG) = (~SPIARB_SPI1_ACTIVE_MODE)&0x1; //disable first
#endif
#if !defined(COMMAND_MODE)
ra_outl(RT2880_SPI0_CFG_REG, SPICFG_MSBFIRST | SPICFG_RXCLKEDGE_FALLING | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV);
#else
ra_outl(RT2880_SPI0_CFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLKPOL | CFG_CLK_DIV);
#endif
// set idle state
ra_outl(RT2880_SPI0_CTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / (128 / (CFG_CLK_DIV+1)) ) >> 1 ;
printf("%s SPI flash driver, SPI clock: %dMHz\n", RLT_MTK_VENDOR_NAME, (mips_bus_feq / 1000000) >> (CFG_CLK_DIV+1));
return 0;
}
int spic_init(void)
{
// use normal(SPI) mode instead of GPIO mode
ra_and(RT2880_GPIOMODE_REG, ~(1 << 1));
// reset spi block
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
// FIXME, clk_div should depend on spi-flash.
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLK_DIV4 | SPICFG_SPICLKPOL);
// set idle state
ra_outl(RT2880_SPICTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / ((mips_bus_feq / 1000 / 1000 / SPICFG_SPICLK_DIV4) )) >> 1 ;
printf("spi_wait_nsec: %x \n", spi_wait_nsec);
return 0;
}