void radeon_disable_vblank(struct drm_device *dev, int crtc) { drm_radeon_private_t *dev_priv = dev->dev_private; if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { switch (crtc) { case 0: r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0); break; case 1: r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0); break; default: DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", crtc); break; } } else { switch (crtc) { case 0: radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0); break; case 1: radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0); break; default: DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", crtc); break; } } }
int radeon_driver_irq_postinstall(struct drm_device *dev) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; atomic_set(&dev_priv->swi_emitted, 0); DRM_INIT_WAITQUEUE(&dev_priv->swi_queue); dev->max_vblank_count = 0x001fffff; radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); return 0; }
int radeon_driver_irq_postinstall(struct drm_device * dev) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; atomic_set(&dev_priv->swi_emitted, 0); DRM_INIT_WAITQUEUE(&dev_priv->swi_queue); if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) return 0; radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); return 0; }
int radeon_driver_irq_postinstall(struct drm_device *dev) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; atomic_set(&dev_priv->swi_emitted, 0); init_waitqueue_head(&dev_priv->swi_queue); dev->max_vblank_count = 0x001fffff; if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) return 0; radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); return 0; }