int radio_init()
{
// Reset
delay_ms(50);
radio_command(SRES);
delay_ms(50);
if (!radio_check_version())
{
failures |= Fail_Radio_Interface;
return 0;
}
// Test GDO2 high
radio_write(IOCFG2, 0x2f | GDOx_INVERT);
if (!radio_gdo2())
{
// Interrupt line is stuck low
failures |= Fail_Radio_Int_Low;
return 0;
}
// Test GDO2 low
radio_write(IOCFG2, 0x2f);
if (radio_gdo2())
{
// Interrupt line is stuck high
failures |= Fail_Radio_Int_High;
return 0;
}
return 1;
}
void reset_RX(unsigned char *output){
retrieve_data_from_bf(4, output);
radio_command(0xE2); // Flush RX FIFO
radio_write_register(0x27, 0x40); // Reset int
}
void radio_configure()
{
radio_in_tx = 0;
radio_command(SIDLE);
radio_select();
for (int i = 0; i < sizeof(cc1101_regs); ++i)
{
spi_xfer(cc1101_regs[i]);
}
radio_deselect();
radio_write(IOCFG2, 6 | GDOx_INVERT);
radio_channel(current_channel);
radio_command(SFRX);
radio_command(SRX);
}
static int rx_finished()
{
radio_write(FSCTRL0, radio_read(FREQEST));
uint8_t bytes = radio_read(RXBYTES);
if (bytes < 3)
{
// Bad CRC, so the packet was flushed (or the radio got misconfigured).
radio_command(SFRX);
radio_command(SRX);
return 0;
}
// Read the packet from the radio
radio_select();
spi_xfer(RXFIFO | CC_READ | CC_BURST);
radio_rx_len = spi_xfer(SNOP);
if (radio_rx_len > sizeof(radio_rx_buf))
{
// Either PKTLEN in the radio configuration is wrong or we lost data in the FIFO and this wasn't really a length byte.
radio_deselect();
radio_command(SFRX);
radio_command(SRX);
radio_rx_len = 0;
return 0;
}
for (int i = 0; i < radio_rx_len; ++i)
{
radio_rx_buf[i] = spi_xfer(SNOP);
}
// Read status bytes
last_rssi = (int8_t)spi_xfer(SNOP);
uint8_t status = spi_xfer(SNOP);
radio_deselect();
if (!(status & 0x80))
{
// Bad CRC
//
// Autoflush is supposed to be on so this should never happen.
// If we get here and autoflush is on, this means some bytes have been lost
// and the status byte isn't really the status byte.
radio_command(SFRX);
radio_command(SRX);
return 0;
}
return 1;
}
void radio_transmit(uint8_t* buf, int len)
{
LED_ON(LED_RY);
radio_select();
spi_xfer(TXFIFO | CC_BURST);
spi_xfer(len);
for (int i = 0; i < len; ++i)
{
spi_xfer(buf[i]);
}
radio_deselect();
// Start transmitting. When this finishes, the radio will automatically switch to RX
// without calibrating (because it doesn't go through IDLE).
radio_command(STX);
radio_in_tx = 1;
}
void configure_receiver(){
unsigned char status;
CE = 0;
status = radio_write_register(0x20, 0x39); //PRX, CRC enabled
sprintf(msg,"%d \r\n", status);
NU32_WriteUART1("Status 1: ");
NU32_WriteUART1(msg);
status = radio_write_register(0x21, 0x00); //disable auto-ack for all channels
sprintf(msg,"%d \r\n", status);
NU32_WriteUART1("Status 2: ");
NU32_WriteUART1(msg);
status = radio_write_register(0x23, 0x03); // address width = 5
sprintf(msg,"%d \r\n", status);
NU32_WriteUART1("Status 3: ");
NU32_WriteUART1(msg);
radio_write_register(0x26, 0x07); // data rate = 1MB
radio_write_register(0x31, 0x04); // 4 byte payload
radio_write_register(0x25, 0x02); // set channel 2, this is default
radio_write_register(0x30, 0xE7); // set address E7E7E7E7E7
radio_write_register(0x20, 0x3B); // Power up to change to change to STAND BY state
CE = 1;
int counter;
for (counter = 0; counter < 80000; counter++){;}
status = radio_command(0xFF);
sprintf(msg,"%d \r\n", status);
NU32_WriteUART1("Status 4: ");
NU32_WriteUART1(msg);
}
void transmit_data(char *data_to_send, int n_bytes){
int counter;
radio_write_register(0x27, 0x7E); // Clear all FIFO interrupts and maximum number of retransmits
radio_write_register(0x20, 0x3A); // Power up to change to change to STAND BY state
radio_command(0xE1); // Clear TX fifo, the data sheet says that this is supposed to come up 0 after POR, but that doesn't seem to be the case
CS = 0;
spi_io(0xA0);
for (counter = 0; counter < n_bytes; counter++)
{
spi_io(data_to_send[counter]);
}
CS = 1;
CE = 1; //Pulse CE to start transmission
for (counter = 0; counter < 800000; counter++){;} // Wait for 1 ms (assuming the PIC clock is set to 80MHz)
CE = 0;
}
