void clocksource_hse_in_8_out_48(void) {
// see
// https://www.mikrocontroller.net/attachment/322047/Clock_Control.png
// or RM00091 p. 98
// enable internal high-speed oscillator
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
// Select HSI as SYSCLK source.
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
// Enable external high-speed oscillator 8MHz
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
rcc_set_sysclk_source(RCC_CFGR_SW_HSE);
// set prescalers for AHB, ADC, ABP1, ABP2.
// Do this before touching the PLL
rcc_set_hpre(RCC_CFGR_HPRE_NODIV); // 48Mhz (max 72)
rcc_set_ppre(RCC_CFGR_PPRE_DIV2); // 24Mhz (max 36)
// sysclk runs with 48MHz -> 1 waitstates.
// * 0WS from 0-24MHz
// * 1WS from 24-48MHz
// * 2WS from 48-72MHz
flash_set_ws(FLASH_ACR_LATENCY_1WS);
// set the PLL multiplication factor to 6
// pll source is hse
RCC_CFGR |= RCC_CFGR_PLLSRC;
// pll prediv = 1
rcc_set_prediv(RCC_CFGR2_PREDIV_NODIV);
// 8MHz (external) * 6 (multiplier) = 48MHz
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6);
// enable PLL oscillator and wait for it to stabilize.
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
// select PLL as SYSCLK source.
rcc_set_sysclk_source(RCC_PLL);
// set the peripheral clock frequencies used */
rcc_ahb_frequency = 48000000;
rcc_apb1_frequency = 24000000;
// When PPRE is set to something != NODIV
// TIM input clock is apb clkspeed*2 (see RM00091 p98)
rcc_timer_frequency = 2*rcc_apb1_frequency;
}
/**
* Setup clocks to run from PLL.
* The arguments provide the pll source, multipliers, dividers, all that's
* needed to establish a system clock.
* @param clock clock information structure
*/
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
if (clock->pllsrc == RCC_CFGR_PLLSRC_HSE_PREDIV) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
} else {
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
}
rcc_osc_off(RCC_PLL);
rcc_usb_prescale_1_5();
if (clock->usbdiv1) {
rcc_usb_prescale_1();
}
rcc_wait_for_osc_not_ready(RCC_PLL);
rcc_set_pll_source(clock->pllsrc);
rcc_set_pll_multiplier(clock->pllmul);
rcc_set_prediv(clock->plldiv);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Configure flash settings. */
flash_prefetch_enable();
flash_set_ws(clock->flash_waitstates);
rcc_set_hpre(clock->hpre);
rcc_set_ppre2(clock->ppre2);
rcc_set_ppre1(clock->ppre1);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
}
void gpio_setup(void) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
rcc_osc_off(RCC_PLL);
rcc_wait_for_osc_not_ready(RCC_PLL);
rcc_set_prediv(RCC_CFGR2_PREDIV_NODIV);
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_PREDIV);
rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_PLL_IN_CLK_X3);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE);
rcc_set_ppre2(RCC_CFGR_PPRE1_DIV_2);
rcc_set_ppre1(RCC_CFGR_PPRE2_DIV_NONE);
flash_set_ws(FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2WS);
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
rcc_wait_for_sysclk_status(RCC_PLL);
rcc_ahb_frequency = 60000000;
rcc_apb1_frequency = 30000000;
rcc_apb2_frequency = 30000000;
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_GPIOC);
rcc_periph_clock_enable(RCC_GPIOD);
rcc_periph_clock_enable(RCC_GPIOE);
rcc_periph_clock_enable(RCC_USART1);
rcc_periph_clock_enable(RCC_TIM2);
rcc_periph_clock_enable(RCC_DAC1);
nvic_enable_irq(NVIC_TIM1_CC_IRQ);
nvic_enable_irq(NVIC_TIM2_IRQ);
nvic_enable_irq(NVIC_TIM3_IRQ);
nvic_enable_irq(NVIC_ADC1_2_IRQ);
/* Unused pins. */
gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN,
GPIO0 |
GPIO2 |
GPIO6 |
GPIO11 |
GPIO12
);
gpio_mode_setup(GPIOB, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN,
GPIO0 |
GPIO1 |
GPIO2 |
GPIO6 |
GPIO7 |
GPIO8 |
GPIO10 |
GPIO11 |
GPIO12 |
GPIO13 |
GPIO14 |
GPIO15
);
gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN,
GPIO0 |
GPIO1 |
GPIO2 |
GPIO3 |
GPIO4 |
GPIO5 |
GPIO6 |
GPIO7 |
GPIO8 |
GPIO13
);
gpio_mode_setup(GPIOD, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN,
GPIO0 |
GPIO1 |
GPIO2 |
GPIO3 |
GPIO4 |
GPIO5 |
GPIO6 |
GPIO7 |
GPIO11 |
GPIO12 |
GPIO13 |
GPIO14 |
GPIO15
);
gpio_mode_setup(GPIOE, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN,
GPIO0 |
GPIO1 |
GPIO3 |
GPIO4 |
GPIO7 |
GPIO8 |
GPIO10 |
GPIO11 |
GPIO12 |
GPIO13 |
GPIO14
);
// gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO5);
gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3);
/* Timer 2, IC2 */
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO1);
gpio_set_af(GPIOA, GPIO_AF1, GPIO1);
/* USART2 */
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9 | GPIO10);
gpio_set_af(GPIOA, GPIO_AF7, GPIO9 | GPIO10);
/* ADC1, channel 4, no filter, fast channel. */
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO3);
/* ADC2, channel 4, no filter, fast channel. */
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO7);
/* ADC3, channel 2, no filter, fast channel. */
gpio_mode_setup(GPIOE, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO9);
/* ADC4, channel 2, no filter, fast channel. */
gpio_mode_setup(GPIOE, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO15);
/* VCTCXO steering, DAC output. */
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO4);
}