/*!
\brief IRC40K configuration function
\param[in] none
\param[out] none
\retval none
*/
void irc40k_config(void)
{
/* enable IRC40K */
rcu_osci_on(RCU_IRC40K);
/* wait till IRC40K is ready */
rcu_osci_stab_wait(RCU_IRC40K);
}
/*!
\brief configure the different system clocks
\param[in] none
\param[out] none
\retval none
*/
void rcu_config(void)
{
/* enable PMU clock */
rcu_periph_clock_enable(RCU_PMU);
/* PMU backup domain write enable */
pmu_backup_write_enable();
/* enable IRC40K */
rcu_osci_on(RCU_IRC40K);
/* wait for IRC40K stabilization flags */
rcu_osci_stab_wait(RCU_IRC40K);
/* configure the RTC clock source selection */
rcu_slcd_clock_config(RCU_RTC_IRC40K);
}
/*!
\brief configure I2S prescale
\param[in] spi_periph: SPIx(x=1,2)
\param[in] i2s_audiosample: I2S audio sample rate
only one parameter can be selected which is shown as below:
\arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
\arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz
\arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz
\arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz
\arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz
\arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz
\arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz
\arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz
\arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz
\param[in] i2s_frameformat: I2S data length and channel length
only one parameter can be selected which is shown as below:
\arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
\arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
\arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
\arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
\param[in] i2s_mckout: I2S master clock output
only one parameter can be selected which is shown as below:
\arg I2S_MCKOUT_ENABLE: I2S master clock output enable
\arg I2S_MCKOUT_DISABLE: I2S master clock output disable
\param[out] none
\retval none
*/
void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout)
{
uint32_t i2sdiv = 2U, i2sof = 0U;
uint32_t clks = 0U;
uint32_t i2sclock = 0U;
#ifndef I2S_EXTERNAL_CLOCK_IN
uint32_t plli2sm = 0U, plli2sn = 0U, plli2sr = 0U;
#endif /* I2S_EXTERNAL_CLOCK_IN */
/* deinit SPI_I2SPSC register */
SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE;
#ifdef I2S_EXTERNAL_CLOCK_IN
rcu_i2s_clock_config(RCU_I2SSRC_I2S_CKIN);
/* set the I2S clock to the external clock input value */
i2sclock = I2S_EXTERNAL_CLOCK_IN;
#else
/* turn on the oscillator HXTAL */
rcu_osci_on(RCU_HXTAL);
/* wait for oscillator stabilization flags is SET */
rcu_osci_stab_wait(RCU_HXTAL);
/* turn on the PLLI2S */
rcu_osci_on(RCU_PLLI2S_CK);
/* wait for PLLI2S flags is SET */
rcu_osci_stab_wait(RCU_PLLI2S_CK);
/* configure the I2S clock source selection */
rcu_i2s_clock_config(RCU_I2SSRC_PLLI2S);
/* get the RCU_PLL_PLLPSC value */
plli2sm = (uint32_t)(RCU_PLL & RCU_PLL_PLLPSC);
/* get the RCU_PLLI2S_PLLI2SN value */
plli2sn = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SN) >> 6);
/* get the RCU_PLLI2S_PLLI2SR value */
plli2sr = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SR) >> 28);
if ((RCU_PLL & RCU_PLL_PLLSEL) == RCU_PLLSRC_HXTAL) {
/* get the I2S source clock value */
i2sclock = (uint32_t)(((HXTAL_VALUE / plli2sm) * plli2sn) / plli2sr);
} else {
/* get the I2S source clock value */
i2sclock = (uint32_t)(((IRC16M_VALUE / plli2sm) * plli2sn) / plli2sr);
}
#endif /* I2S_EXTERNAL_CLOCK_IN */
/* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
if (I2S_MCKOUT_ENABLE == i2s_mckout) {
clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample);
} else {
if (I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat) {
clks = (uint32_t)(((i2sclock / 32U) * 10U) / i2s_audiosample);
} else {
clks = (uint32_t)(((i2sclock / 64U) * 10U) / i2s_audiosample);
}
}
/* remove the floating point */
clks = (clks + 5U) / 10U;
i2sof = (clks & 0x00000001U);
i2sdiv = ((clks - i2sof) / 2U);
i2sof = (i2sof << 8U);
/* set the default values */
if ((i2sdiv < 2U) || (i2sdiv > 255U)) {
i2sdiv = 2U;
i2sof = 0U;
}
/* configure SPI_I2SPSC */
SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout);
/* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
/* configure data frame format */
SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat;
}
/*!
\brief configure TLI peripheral
\param[in] none
\param[out] none
\retval none
*/
static void tli_config(void)
{
tli_parameter_struct tli_init_struct;
tli_layer_parameter_struct tli_layer_init_struct;
rcu_periph_clock_enable(RCU_TLI);
/* configure the PLLSAI clock to generate lcd clock */
if(ERROR == rcu_pllsai_config(192, 2, 3, 3)){
while(1);
}
rcu_tli_clock_div_config(RCU_PLLSAIR_DIV8);
rcu_osci_on(RCU_PLLSAI_CK);
if(ERROR == rcu_osci_stab_wait(RCU_PLLSAI_CK)){
while(1);
}
/* TLI initialization */
tli_init_struct.signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW;
tli_init_struct.signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW;
tli_init_struct.signalpolarity_de = TLI_DE_ACTLIVE_LOW;
tli_init_struct.signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI;
/* LCD display timing configuration */
tli_init_struct.synpsz_hpsz = LCD_480_320_HSYNC;
tli_init_struct.synpsz_vpsz = LCD_480_320_VSYNC;
tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP;
tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP;
tli_init_struct.activesz_hasz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP;
tli_init_struct.activesz_vasz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP;
tli_init_struct.totalsz_htsz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP;
tli_init_struct.totalsz_vtsz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP + LCD_480_320_VFP;
/* LCD background color configure*/
tli_init_struct.backcolor_red = 0x00;
tli_init_struct.backcolor_green = 0x00;
tli_init_struct.backcolor_blue = 0x00;
tli_init(&tli_init_struct);
lcd_framebuffer = rt_malloc(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH);
RT_ASSERT(lcd_framebuffer != NULL);
rt_memset(lcd_framebuffer, 0, sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT);
/* TLI layer0 configuration */
tli_layer_init_struct.layer_window_leftpos = tli_init_struct.backpsz_hbpsz + 1;
tli_layer_init_struct.layer_window_rightpos = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH;
tli_layer_init_struct.layer_window_toppos = tli_init_struct.backpsz_vbpsz + 1;
tli_layer_init_struct.layer_window_bottompos = tli_init_struct.backpsz_vbpsz + RT_HW_LCD_HEIGHT;
tli_layer_init_struct.layer_ppf = LAYER_PPF_RGB565;
tli_layer_init_struct.layer_sa = 0xFF;
tli_layer_init_struct.layer_default_blue = 0x00;
tli_layer_init_struct.layer_default_green = 0x00;
tli_layer_init_struct.layer_default_red = 0x00;
tli_layer_init_struct.layer_default_alpha = 0x00;
tli_layer_init_struct.layer_acf1 = LAYER_ACF1_PASA;
tli_layer_init_struct.layer_acf2 = LAYER_ACF2_PASA;
tli_layer_init_struct.layer_frame_bufaddr = (uint32_t)lcd_framebuffer;
tli_layer_init_struct.layer_frame_line_length = ((RT_HW_LCD_WIDTH * 2) + 3);
tli_layer_init_struct.layer_frame_buf_stride_offset = (RT_HW_LCD_WIDTH * 2);
tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT;
tli_layer_init(LAYER0, &tli_layer_init_struct);
}