static int sio_open(struct tty_struct *tty, struct file *filp)
{
int line;
dbg("%s:\n", __FUNCTION__);
MOD_INC_USE_COUNT;
line = MINOR(tty->device) - tty->driver.minor_start;
if (line) {
MOD_DEC_USE_COUNT;
return -ENODEV;
}
tty->driver_data = NULL;
tty->low_latency = 1; // simple test
if (!sio_tty)
sio_tty = tty;
dbg("%s: STA=%02x. CON=%02x, BCN=%02x, TCN=%02x, BT=%02x\n",
__FUNCTION__, rd_reg(OKI_SIOSTA), rd_reg(OKI_SIOCON),
rd_reg(OKI_SIOBCN), rd_reg(OKI_SIOTCN), rd_reg(OKI_SIOBT));
enable_irq(IRQ_SIO);
sio_use_count++;
return 0;
}
static inline void sio_set_cflag(int cflag)
{
int h_lcr, baud, quot;
switch (cflag & CSIZE) {
case CS7:
h_lcr = OKI_SIOCON_LN7;
break;
default: /* CS8 */
h_lcr = 0x0;
break;
}
if (cflag & PARENB)
h_lcr |= OKI_SIOCON_EVN | OKI_SIOCON_PEN;
if (cflag & PARODD)
h_lcr |= OKI_SIOCON_PEN;
if (!(cflag & CSTOPB))
h_lcr |= OKI_SIOCON_TSTB;
switch (cflag & CBAUD) {
case B200: baud = 200; break;
case B300: baud = 300; break;
case B1200: baud = 1200; break;
case B1800: baud = 1800; break;
case B2400: baud = 2400; break;
case B4800: baud = 4800; break;
default:
case B9600: baud = 9600; break;
case B19200: baud = 19200; break;
case B38400: baud = 38400; break;
case B57600: baud = 57600; break;
case B115200: baud = 115200; break;
}
quot = 256 - (oki_cclk/(16*baud));
printk("quot = %d\n", quot);
wr_reg(OKI_SIOBCN, 0x00);
wr_reg(OKI_SIOCON, 0x00);
wr_reg(OKI_SIOBT, quot);
wr_reg(OKI_SIOCON, h_lcr);
/* set for loopback test... */
if (0)
wr_reg(OKI_SIOTCN, OKI_SIOTCN_LBTST);
else
wr_reg(OKI_SIOTCN, 0x00);
wr_reg(OKI_SIOBCN, OKI_SIOBCN_BGRUN);
dbg("%s: STA=%02x. CON=%02x, BCN=%02x, TCN=%02x, OBT=%02x\n",
__FUNCTION__, rd_reg(OKI_SIOSTA), rd_reg(OKI_SIOCON),
rd_reg(OKI_SIOBCN), rd_reg(OKI_SIOTCN), rd_reg(OKI_SIOBT));
}
void audio_adc_Stop(void)
{
REG32(AUDIO_ACON) |= BIT(4);//mute adc
REG32(AUDIO_ACON) &= ~(BIT(0)|BIT(1));//mic disable/adc analog
wr_reg(AUADC_CFG,rd_reg(AUADC_CFG)&(~AUADC_EN));
wr_reg(DACCFG,rd_reg(DACCFG)&(~G_AUADC_EN)&(~G_AGC_EN));
ClrIntSrc(AUADC_INT);
dmac_channel_disable(AUDIO_ADC_DMA_CH);
}
void audio_adc_init()
{
u8 adr;
REG32(PCON0) &= ~(1<<21); // enable dac clock
REG32(CLKCON1) &= ~(0xf<<8);
REG32(CLKCON1) |= (9<<8);//10 div 240M/(9+1)=24M
REG32(CLKCON0) &= ~((1<<6)|(1<<7));
g_stcJpegInfo.u32AudioDataReady = 0;
g_stcJpegInfo.iAudioFillBufCnt=0;
g_stcJpegInfo.iAudioFSWriteBufCnt=0;
g_stcJpegInfo.dwAudiobufSize = 0x2000;
g_stcJpegInfo.pAudioDataBuf = (u8 *)((u32)JPEG_BUFFER_END_ADDRESS - 0x2000);
audio_adc_analog_init();//
//llp_peri2mem(AUDIO_ADC_DMA_CH, (6<<7)|(0<<11), 0, (DMA_LLP *)(&adc_llp0));
dmac_channel_disable(AUDIO_ADC_DMA_CH);
dma_peri2mem_Ext(AUDIO_ADC_DMA_CH, (0<<11)|(6<<7)|(0<<1), (0<<11)|(0<<10), AUADC_DMA_TX_ADR, (audio_buffer_ptr+8), (2048-2));
REG32(DMA_ClearTfrL) = BIT(3);
REG32(DMA_MaskTfrL) |= (BIT(3) | BIT(3+8));
SetIntSrc(DMA_INT);
wr_reg(DACCFG,rd_reg(DACCFG)|G_AUADC_EN|G_AGC_EN);//AGC EN ADC EN
for(adr=0; adr<140; adr++)
{
wr_reg(AUADC_DAT,0);
}
wr_reg(AUADC_BAUD,4);//24000000/192000/25-1
wr_reg(AUADC_CFG,AUADC_FILT1_DOWN(2)|AUADC_FILT2_DOWN(2)|AUADC_FILT3_DOWN(3)|AUADC_COEF_EN|AUADC_FILT1_EN|AUADC_FILT2_EN|AUADC_EN);
// DMA enable and AGC enable
//wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)|DMA_EN|AGC_IE);
wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)|DMA_EN);
// block number, block size
wr_reg(AGC_CFG3,(1<<12)|((2048-2)<<0));
// clear DMA_DONE pending flag before kit-start AGC
wr_reg(AGC_CFG_CLR,1<<0);
// kit-start AGC
wr_reg(AGC_CFG_CLR,1<<4);
wr_reg(AGC_CFG1,0x17e6); //mic sound is max
wr_reg(AGC_CFG2,0x780); //mic sound set
REG32(AUDIO_ACON) |= BIT(5);
SetIntSrc(AUADC_INT);
deg_Printf("audio adc init ok\n");
}
void test_gpio( void )
{
wr_reg( 0x0304, 0x0123 ); // frame begin/end length reg
wr_reg( 0x030A, 0x4567 ); // line begin/end length reg
if ( rd_reg( 0x0304 ) == 0x0123 ) { DBG("rd_reg( 0x0304 ) == 0x0123 failed\n"); }
if ( rd_reg( 0x030A ) == 0x4567 ) { DBG("rd_reg( 0x030A ) == 0x4567 failed\n"); }
wr_reg( 0x0304, 0xFEDC );
wr_reg( 0x030A, 0xBA98 );
if ( rd_reg( 0x0304 ) == 0xFEDC ) { DBG("rd_reg( 0x0304 ) == 0xFEDC failed\n"); }
if ( rd_reg( 0x030A ) == 0xBA98 ) { DBG("rd_reg( 0x030A ) == 0xBA98 failed\n"); }
}
void audio_adc_isr(void)
{
u32 agc_sta = rd_reg(AGC_STA);
if(agc_sta & BIT(4))
{
agcflg=0x0a;
// deg_Printf("audio_adc_isr a\n");
}
else
{
agcflg=0x0b;
// deg_Printf("audio_adc_isr b\n");
}
wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(0));
}
static inline int sio_xmit(int ch)
{
unsigned long flags;
dbg_tx("%s: ch %02x (STA %02x)\n", __FUNCTION__, ch, rd_reg(OKI_SIOSTA));
local_irq_save(flags);
/* decided wether we can write this directly to the uart
* or wether we are going to have to buffer it */
printk(KERN_DEBUG "%s: ready %d, locked %d, xchar %02x\n",
__FUNCTION__, sio_xmit_ready(), sio_xmit_locked(), x_char);
if (sio_xmit_ready() && !sio_xmit_locked() && x_char == 0) {
sio_xmit_do(ch);
goto exit;
}
if (putp + 1 == getp ||
(putp + 1 == wbuf + sizeof(wbuf) && getp == wbuf)) {
local_irq_restore(flags);
return 0;
}
*putp = ch;
if (++putp >= wbuf + sizeof(wbuf))
putp = wbuf;
exit:
local_irq_restore(flags);
return 1;
}
static void sio_close(struct tty_struct *tty, struct file *filp)
{
dbg("%s:\n", __FUNCTION__);
dbg("%s: STA=%02x. CON=%02x, BCN=%02x, TCN=%02x, BT=%02x\n",
__FUNCTION__, rd_reg(OKI_SIOSTA), rd_reg(OKI_SIOCON),
rd_reg(OKI_SIOBCN), rd_reg(OKI_SIOTCN), rd_reg(OKI_SIOBT));
if (!--sio_use_count) {
dbg("%s: closing down\n", __FUNCTION__);
sio_wait_until_sent(tty, 0);
disable_irq(IRQ_SIO);
sio_tty = NULL;
}
MOD_DEC_USE_COUNT;
}
int do_mem_mw_mask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *endp;
unsigned long reg_add=0;
unsigned int wr_reg_value=0;
unsigned int rd_reg_value=0;
unsigned int wr_reg_and_mask_1=0xffffffff;
if (argc < 4) {
//cmd_usage(cmdtp);
return -1;
}
reg_add = simple_strtoul(argv[1], &endp, 10);
wr_reg_value = simple_strtoul(argv[2], &endp, 10);
wr_reg_and_mask_1 = simple_strtoul(argv[3], &endp, 10);
rd_reg_value = (rd_reg(reg_add));
wr_reg(reg_add,(rd_reg_value&wr_reg_and_mask_1)|(wr_reg_value&(~wr_reg_and_mask_1)) );
printf("mwm 0x%lx:[0x%8x] with [0x%8x] ok\n", reg_add, rd_reg_value, rd_reg(reg_add));
return 0;
}
void NokiaN70_ReadRegister(uint8_t reg,uint8_t length,uint8_t *val) {
uint8_t i;
// first read is dummy read
val[0]=rd_reg(reg);
for(i=0;i<length;i++) {
val[i]=rd_dat();
}
}
static void sio_rx_int(void)
{
unsigned int flag;
unsigned int ch;
unsigned int status;
if (!sio_tty) {
disable_irq(IRQ_SIO);
wr_reg(OKI_SIOSTA, OKI_SIOSTA_RVIRQ);
return;
}
do {
status = rd_reg(OKI_SIOSTA);
flag = TTY_NORMAL;
if ((status & OKI_SIOSTA_RVIRQ) == 0)
break;
ch = rd_reg(OKI_SIOBUF);
wr_reg(OKI_SIOSTA, OKI_SIOSTA_RVIRQ | ALL_ERRS);
if ((status & OKI_SIOSTA_OERR) && 1)
tty_insert_flip_char(sio_tty, 0, TTY_OVERRUN);
if (status & OKI_SIOSTA_PERR)
flag = TTY_PARITY;
else if (flag & OKI_SIOSTA_FERR )
flag = TTY_FRAME;
if (sio_tty->flip.count >= TTY_FLIPBUF_SIZE) {
printk("calling %p\n", sio_tty->flip.tqueue.routine);
sio_tty->flip.tqueue.routine((void *)sio_tty);
}
tty_insert_flip_char(sio_tty, ch, flag);
} while(1);
tty_flip_buffer_push(sio_tty);
}
void audio_AGC_DMA_Isr(void)
{
u32 agc_sta = rd_reg(AGC_STA);
//deg_Printf(" %x\n",agc_sta);
if((agc_sta & 0x1) == 0x1)
wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(0));
wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)&(~BIT(5)));
if((g_stcJpegInfo.iAudioFillBufCnt+1) < (g_stcJpegInfo.iAudioFSWriteBufCnt + AUDIO_BUFFER_NUM))
{
if(audio_buffer_ptr == ((u32)JPEG_BUFFER_END_ADDRESS - 0x2000))
audio_buffer_ptr = (u32)JPEG_BUFFER_END_ADDRESS-(AUDIO_BUFFER_NUM*0x2000);
else
audio_buffer_ptr += g_stcJpegInfo.dwAudiobufSize;
g_stcJpegInfo.iAudioFillBufCnt++;
}
else
{
deg_Printf("d");
g_stcJpegInfo.i30FrameCnt -=((192*(u32Framecount+1))/25 -(192*u32Framecount)/25);
u32Framecount++;
if(u32Framecount >= 25)
{
u32Framecount = 0;
}
g_stcJpegInfo.iJpeg10MSCnt -= 25;
}
dmac_channel_disable(AUDIO_ADC_DMA_CH);
//dma_peri2mem_Ext(AUDIO_ADC_DMA_CH, (0<<11)|(6<<7)|(0<<1), (0<<11)|(0<<10), AUADC_DMA_TX_ADR, (audio_buffer_ptr+8), (2048-2));
REG32(DMA_DAR0L + AUDIO_ADC_DMA_CH*0x58) = (u32)(audio_buffer_ptr+8);
dmac_channel_enable(AUDIO_ADC_DMA_CH);
wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)|(BIT(5)));
wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(5));
}
static void sio_irq(int irq, void *dev, struct pt_regs *regs)
{
while (1) {
unsigned int status = rd_reg(OKI_SIOSTA);
if (!(status & OKI_SIOSTA_ANYIRQ))
break;
if (status & OKI_SIOSTA_TRIRQ)
sio_tx_int();
if (status & OKI_SIOSTA_RVIRQ)
sio_rx_int();
}
}
static void sio_xmit_check(void)
{
unsigned int status;
/* must be called with irqs disabled */
status = rd_reg(OKI_SIOSTA);
dbg_tx("%s: status=%02x\n", __FUNCTION__, status);
if (status & OKI_SIOSTA_TRIRQ) {
sio_tx_inprogress = 0;
wr_reg(OKI_SIOSTA, OKI_SIOSTA_TRIRQ);
} else if (time_after(jiffies, sio_tx_last + HZ/10)) {
printk(KERN_ERR "sio: tx timeout\n");
sio_tx_inprogress = 0;
}
}
void dac_init()
{
// Uart_SendByte ('\n');Uart_SendByte ('e');Uart_SendByte ('\n');
REG32(PCON0) &= ~(1<<21); // enable dac clock
REG32(CLKCON0) &= ~(BIT(6)|BIT(7));
REG32(CLKCON1) &= ~(0xf<<8);
REG32(CLKCON1) |= (9<<8);//10 div 240M/(9+1)=24M
obuf_cfg();
REG32(DAC_ACON0) |= BIT(2);
wr_reg(FIFO_CNT, DAC_BLOCK_CNT);//
// wr_reg(OBUF_CLR, 0x02);//clear pending
// dac_analog_init();
#if 0
if(adc_single_double_ch)
{
music_llp0.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (1<<4) | (1<<1);
music_llp1.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (1<<4) | (1<<1);
}
else
{
music_llp0.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (2<<4) | (2<<1);
music_llp1.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (2<<4) | (2<<1);
}
#endif
llp_peri2mem (AUDIO_DAC_DMA_CH, (0<<7)|(7<<11), 0, &adc_dac0);
wr_reg(DACCFG, (rd_reg(DACCFG)& 0xffffff0f) | ((DAC_SAMPLE_32000)<<4) | DAC_EN);
digital_volume_set(0x3fff,1,0);//
REG32(DAC_ACON0) &= ~BIT(2);
deg_Printf("dac_init\r\n");
return;
}
void TFT_ILI9325::begin() {
uint16_t devCode;
sleep(50);
devCode = rd_reg(0x00);
if (devCode == LCD_DEVICE_ID) {
/* Start Initial Sequence --------------------------------------------------*/
wr_reg(0xE3, 0x3008);
wr_reg(0xE7, 0x0012);
wr_reg(0xEF, 0x1231);
// wr_reg(0xE5, 0x8000); /* Set the internal vcore voltage */
wr_reg(0x00, 0x0001); /* Start internal OSC */
wr_reg(0x01, 0x0100); /* Set SS and SM bit */
wr_reg(0x02, 0x0700); /* Set 1 line inversion */
wr_reg(0x03, 0x1030); /* Set GRAM write direction and BGR=1 */
wr_reg(0x04, 0x0000); /* Resize register */
wr_reg(0x08, 0x0207); /* 2 lines each, back and front porch */
wr_reg(0x09, 0x0000); /* Set non-disp area refresh cyc ISC */
wr_reg(0x0A, 0x0000); /* FMARK function */
wr_reg(0x0C, 0x0000); /* RGB interface setting */
wr_reg(0x0D, 0x0000); /* Frame marker Position */
wr_reg(0x0F, 0x0000); /* RGB interface polarity */
/* Power On sequence -------------------------------------------------------*/
wr_reg(0x10, 0x0000); /* Reset Power Control 1 */
wr_reg(0x11, 0x0007); /* Reset Power Control 2 */
wr_reg(0x12, 0x0000); /* Reset Power Control 3 */
wr_reg(0x13, 0x0000); /* Reset Power Control 4 */
sleep(200); /* Discharge cap power voltage (200ms)*/
wr_reg(0x10, 0x1690); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
wr_reg(0x11, 0x0227); /* DC1[2:0], DC0[2:0], VC[2:0] */
sleep(50); /* Delay 50 ms */
wr_reg(0x12, 0x001B); /* VREG1OUT voltage */
sleep(50); /* Delay 50 ms
*/
wr_reg(0x13, 0x1600); /* VDV[4:0] for VCOM amplitude */
wr_reg(0x29, 0x0018); /* VCM[4:0] for VCOMH */
wr_reg(0x2B, 0x000C);
sleep(50); /* Delay 50 ms */
wr_reg(0x20, 0x0000); /* GRAM horizontal Address */
wr_reg(0x21, 0x0000); /* GRAM Vertical Address */
/* Adjust the Gamma Curve --------------------------------------------------*/
wr_reg(0x30, 0x0000);
wr_reg(0x31, 0x0404);
wr_reg(0x32, 0x0304);
wr_reg(0x35, 0x0005);
wr_reg(0x36, 0x1604);
wr_reg(0x37, 0x0304);
wr_reg(0x38, 0x0303);
wr_reg(0x39, 0x0707);
wr_reg(0x3C, 0x0500);
wr_reg(0x3D, 0x000F);
/* Set GRAM area -----------------------------------------------------------*/
wr_reg(0x50, 0x0000); /* Horizontal GRAM Start Address */
wr_reg(0x51, (LCD_HEIGHT - 1)); /* Horizontal GRAM End Address */
wr_reg(0x52, 0x0000); /* Vertical GRAM Start Address */
wr_reg(0x53, (LCD_WIDTH - 1)); /* Vertical GRAM End Address */
wr_reg(0x60, 0xA700); /* Gate Scan Line */
wr_reg(0x61, 0x0001); /* NDL,VLE, REV */
wr_reg(0x6A, 0x0000); /* Set scrolling line */
/* Partial Display Control -------------------------------------------------*/
wr_reg(0x80, 0x0000);
wr_reg(0x81, 0x0000);
wr_reg(0x82, 0x0000);
wr_reg(0x83, 0x0000);
wr_reg(0x84, 0x0000);
wr_reg(0x85, 0x0000);
/* Panel Control -----------------------------------------------------------*/
wr_reg(0x90, 0x0010);
wr_reg(0x92, 0x6000);
wr_reg(0x03, 0x1038);
wr_reg(0x07, 0x0133); /* 262K color and display ON */
/* Turn backlight on */
pinBL = HIGH;
pinBL = LOW;
pinBL = HIGH;
} else {
dbg.println("TFT_ILI9325::begin! Unknow device id %Xh\n", devCode);
}
}
void adc_init(void)
{
// u16 tmp;
deg_Printf("adc_init\r\n");
u8 adr;
REG32(PCON0) &= ~(1<<21); // enable dac clock
REG32(CLKCON1) &= ~(0xf<<8);
REG32(CLKCON1) |= (9<<8);//10 div 240M/(9+1)=24M
REG32(CLKCON0) &= ~((1<<6)|(1<<7));
if(1 == adc_single_double_ch)
{
adc_llp0.CTL_L = (1<<28) | (1<<27) | (1<<25) | (0<<23) | (2<<20) | (2<<9) | (0<<7) | (1<<4) | (1<<1);
adc_llp1.CTL_L = (1<<28) | (1<<27) | (1<<25) | (0<<23) | (2<<20) | (2<<9) | (0<<7) | (1<<4) | (1<<1);
}
else
{
adc_llp0.CTL_L = (1<<28) | (1<<27) | (1<<25) | (0<<23) | (2<<20) | (2<<9) | (0<<7) | (2<<4) | (2<<1);
adc_llp1.CTL_L = (1<<28) | (1<<27) | (1<<25) | (0<<23) | (2<<20) | (2<<9) | (0<<7) | (2<<4) | (2<<1);
}
llp_peri2mem (AUDIO_ADC_DMA_CH, (6<<7)|(0<<11), 0, &adc_llp0);
// dmac_channel_disable(AUDIO_ADC_DMA_CH);
// dma_peri2mem(AUDIO_ADC_DMA_CH, (0<<11)|(6<<7)|(0<<1), (0<<11)|(0<<10), AUADC_DMA_TX_ADR, (u32)(&audio_buffer_ptr[0]), 1024/4);
REG32(DAC_ACON0) |= BIT(0)|BIT(17)|BIT(13)|BIT(15);
REG32(AUDIO_ACON) |= BIT(0)|BIT(1);
REG32(AUDIO_ACON) &= ~BIT(4);
// audio_adc_analog_init();//
wr_reg(DACCFG,rd_reg(DACCFG)|G_AUADC_EN|G_AGC_EN);//AGC EN ADC EN
for(adr=0; adr<140; adr++)
{
wr_reg(AUADC_DAT,0);
}
#if 0
wr_reg(AGC_CFG0,(1<<5));
wr_reg(AGC_CFG_CLR,(1<<4));
wr_reg(AUADC_CFG,(1<<6) |(1<<4)| (1<<0));
wr_reg(AUADC_BAUD,15);
#else
if (ADC_44_1K == adc_sample_rate)
{
wr_reg(AUADC_BAUD,7);//24000000/176400/17-1
// ADC filter1sample multiple, adc filter1 enable, Audio ADC enable
wr_reg(AUADC_CFG,AUADC_FILT1_DOWN(4)/*|AUADC_FILT2_DOWN(2)|AUADC_FILT3_DOWN(2)|AUADC_COEF_EN|AUADC_FILT2_EN*/|AUADC_COEF_EN|AUADC_FILT1_EN|AUADC_SAMP_SEL|AUADC_RMDC_EN|AUADC_EN);
deg_Printf (("adc simple setting ADC_44_1K\r\n"));
// wr_reg(AUADC_CFG,AUADC_FILT1_DOWN(2)|AUADC_COEF_EN|(1<<6)|AUADC_SAMP_SEL|AUADC_RMDC_EN|AUADC_EN);
}
else if (ADC_16K == adc_sample_rate)
{
wr_reg(AUADC_BAUD,4);//24000000/192000/25-1
wr_reg(AUADC_CFG,AUADC_FILT1_DOWN(2)|AUADC_FILT2_DOWN(2)|AUADC_FILT3_DOWN(3)|AUADC_COEF_EN|AUADC_FILT1_EN|AUADC_FILT2_EN|AUADC_EN);
deg_Printf (("adc simple setting ADC_16K\r\n"));
}
else if (ADC_48K == adc_sample_rate)
{
wr_reg(AUADC_BAUD,4);//24000000/192000/25-1
// ADC filter1sample multiple, adc filter1 enable, Audio ADC enable
wr_reg(AUADC_CFG,AUADC_FILT1_DOWN(4)/*|AUADC_FILT2_DOWN(2)|AUADC_FILT3_DOWN(2)|AUADC_COEF_EN|AUADC_FILT2_EN*/|AUADC_COEF_EN|AUADC_FILT1_EN|AUADC_RMDC_EN|AUADC_EN);
deg_Printf (("adc simple setting ADC_48K\r\n"));
}
else if (ADC_32K == adc_sample_rate)
{
wr_reg(AUADC_BAUD,4);//24000000/192000/25-1
// ADC filter1sample multiple, adc filter1 enable, Audio ADC enable
wr_reg(AUADC_CFG,AUADC_FILT1_DOWN(6)/*|AUADC_FILT2_DOWN(2)|AUADC_FILT3_DOWN(2)|AUADC_COEF_EN|AUADC_FILT2_EN*/|AUADC_COEF_EN|AUADC_FILT1_EN|AUADC_RMDC_EN|AUADC_EN);
deg_Printf (("adc simple setting ADC_32K\r\n"));
}
else
{
deg_Printf (("adc simple setting unknown\r\n"));
}
// DMA enable and AGC enable
//wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)|DMA_EN);
// wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)|DMA_EN);
wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)|DMA_EN|AGC_IE);
// block number, block size
wr_reg(AGC_CFG3,(2<<12)|(DAC_BLOCK_CNT<<0));
// clear DMA_DONE pending flag before kit-start AGC
wr_reg(AGC_CFG_CLR,1<<0);
// kit-start AGC
wr_reg(AGC_CFG_CLR,1<<4);
wr_reg(AGC_CFG1,0x16e6);
wr_reg(AGC_CFG2,0x600);
SetIntSrc(AUADC_INT);
#endif
// APP_TRACE_INFO(("adc init over\r\n"));
return ;
}
void GLCD_Init (void) {
unsigned long temp;
unsigned short driverCode;
/* Configure the LCD Control pins --------------------------------------------*/
RCC->AHB1ENR |=((1UL << 0) | /* Enable GPIOA clock */
#ifndef __STM_EVAL /* MCBSTM32F200 and MCBSTMF400 board */
(1UL << 2) | /* Enable GPIOC clock */
#endif
(1UL << 3) | /* Enable GPIOD clock */
(1UL << 4) | /* Enable GPIOE clock */
(1UL << 5) | /* Enable GPIOF clock */
(1UL << 6)); /* Enable GPIOG clock */
/* PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE) */
/* PD.08(D13), PD.09(D14), PD.10(D15), PD.14(D0), PD.15(D1) */
temp = GPIOD->MODER & ~0xF03F0F0F; /* Clear Bits */
GPIOD->MODER = temp | 0xA02A0A0A; /* Alternate Function mode */
temp = GPIOD->OSPEEDR & ~0xF03F0F0F; /* Clear Bits */
GPIOD->OSPEEDR = temp | 0xA02A0A0A; /* 50 MHz Fast speed */
temp = GPIOD->AFR[0] & ~0x00FF00FF; /* Clear Bits */
GPIOD->AFR[0] = temp | 0x00CC00CC; /* Alternate Function mode AF12 */
temp = GPIOD->AFR[1] & ~0xFF000FFF; /* Clear Bits */
GPIOD->AFR[1] = temp | 0xCC000CCC; /* Alternate Function mode AF12 */
/* PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8) */
/* PE.12(D9), PE.13(D10), PE.14(D11), PE.15(D12) */
temp = GPIOE->MODER & ~0xFFFFC000; /* Clear Bits */
GPIOE->MODER = temp | 0xAAAA8000; /* Alternate Function mode */
temp = GPIOE->OSPEEDR & ~0xFFFFC000; /* Clear Bits */
GPIOE->OSPEEDR = temp | 0xAAAA8000; /* 50 MHz Fast speed */
temp = GPIOE->AFR[0] & ~0xF0000000; /* Clear Bits */
GPIOE->AFR[0] = temp | 0xC0000000; /* Alternate Function mode AF12 */
temp = GPIOE->AFR[1] & ~0xFFFFFFFF; /* Clear Bits */
GPIOE->AFR[1] = temp | 0xCCCCCCCC; /* Alternate Function mode AF12 */
/* PF.00(A0 (RS)) */
temp = GPIOF->MODER & ~0x00000003; /* Clear Bits */
GPIOF->MODER = temp | 0x00000002; /* Alternate Function mode */
temp = GPIOF->OSPEEDR & ~0x00000003; /* Clear Bits */
GPIOF->OSPEEDR = temp | 0x00000002; /* 50 MHz Fast speed */
temp = GPIOF->AFR[0] & ~0x0000000F; /* Clear Bits */
GPIOF->AFR[0] = temp | 0x0000000C; /* Alternate Function mode AF12 */
#ifdef __STM_EVAL /* STM3220G-EVAL and STM3240G-EVAL */
/* PG.10(NE4 (LCD/CS)) - CE1(LCD /CS) */
temp = GPIOG->MODER & ~0x00300000; /* Clear Bits */
GPIOG->MODER = temp | 0x00200000; /* Alternate Function mode */
temp = GPIOG->OSPEEDR = ~0x00300000; /* Clear Bits */
GPIOG->OSPEEDR = temp | 0x00200000; /* 50 MHz Fast speed */
temp = GPIOG->AFR[1] & ~0x00000F00; /* Clear Bits */
GPIOG->AFR[1] = temp | 0x00000C00; /* Alternate Function mode AF12 */
/* PA.08(LCD Backlight */
GPIOA->BSRRH |= (1UL << 8); /* Backlight off */
temp = GPIOA->MODER & ~(3UL << 2*8); /* Clear Bits */
GPIOA->MODER = temp | (1UL << 2*8); /* PA.9 is output */
GPIOA->OTYPER &= ~(1UL << 8); /* PA.9 is output Push-Pull */
temp = GPIOA->OSPEEDR & ~(3UL << 2*8); /* Clear Bits */
GPIOA->OSPEEDR = temp | (2UL << 2*8); /* PA.9 is 50MHz Fast Speed */
#else /* MCBSTM32F200 and MCBSTMF400 board */
/* PG.12(NE4 (LCD/CS)) - CE1(LCD /CS) */
temp = GPIOG->MODER & ~0x03000000; /* Clear Bits */
GPIOG->MODER = temp | 0x02000000; /* Alternate Function mode */
temp = GPIOG->OSPEEDR & ~0x03000000; /* Clear Bits */
GPIOG->OSPEEDR = temp | 0x02000000; /* 50 MHz Fast speed */
temp = GPIOG->AFR[1] & ~0x000F0000; /* Clear Bits */
GPIOG->AFR[1] = temp | 0x000C0000; /* Alternate Function mode AF12 */
/* PC.07(LCD Backlight */
GPIOC->BSRRH |= (1UL << 7); /* Backlight off */
temp = GPIOC->MODER & ~(3UL << 2*7); /* Clear Bits */
GPIOC->MODER = temp | (1UL << 2*7); /* PC.7 is output */
GPIOC->OTYPER &= ~(1UL << 7); /* PC.7 is output Push-Pull */
temp = GPIOC->OSPEEDR & ~(3UL << 2*7); /* Clear Bits */
GPIOC->OSPEEDR = temp | (2UL << 2*7); /* PC.7 is 50MHz Fast Speed */
#endif
/*-- FSMC Configuration ------------------------------------------------------*/
RCC->AHB3ENR |= (1UL << 0); /* Enable FSMC clock */
#ifdef __STM_EVAL /* STM3220G-EVAL and STM3240G-EVAL */
FSMC_Bank1->BTCR[(3-1)*2 + 1] = /* Bank3 NOR/SRAM timing register */
/* configuration */
#else /* MCBSTM32F200 and MCBSTMF400 board */
FSMC_Bank1->BTCR[(4-1)*2 + 1] = /* Bank4 NOR/SRAM timing register */
/* configuration */
#endif
(0 << 28) | /* FSMC AccessMode A */
(0 << 24) | /* Data Latency */
(0 << 20) | /* CLK Division */
(0 << 16) | /* Bus Turnaround Duration */
(11 << 8) | /* Data SetUp Time */
(0 << 4) | /* Address Hold Time */
(1 << 0); /* Address SetUp Time */
#ifdef __STM_EVAL /* STM3220G-EVAL and STM3240G-EVAL */
FSMC_Bank1->BTCR[(3-1)*2 + 0] =
#else /* MCBSTM32F200 and MCBSTMF400 board */
FSMC_Bank1->BTCR[(4-1)*2 + 0] = /* Control register */
#endif
(0 << 19) | /* Write burst disabled */
(0 << 15) | /* Async wait disabled */
(0 << 14) | /* Extended mode disabled */
(0 << 13) | /* NWAIT signal is disabled */
(1 << 12) | /* Write operation enabled */
(0 << 11) | /* NWAIT signal is active one data */
/* cycle before wait state */
(0 << 10) | /* Wrapped burst mode disabled */
(0 << 9) | /* Wait signal polarity active low */
(0 << 8) | /* Burst access mode disabled */
(1 << 4) | /* Memory data bus width is 16 bits */
(0 << 2) | /* Memory type is SRAM */
(0 << 1) | /* Address/Data Multiplexing disable */
(1 << 0); /* Memory Bank enable */
delay(5); /* Delay 50 ms */
driverCode = rd_reg(0x00);
if (driverCode == 0x47) { /* LCD with HX8347-D LCD Controller */
Himax = 1; /* Set Himax LCD controller flag */
/* Driving ability settings ----------------------------------------------*/
wr_reg(0xEA, 0x00); /* Power control internal used (1) */
wr_reg(0xEB, 0x20); /* Power control internal used (2) */
wr_reg(0xEC, 0x0C); /* Source control internal used (1) */
wr_reg(0xED, 0xC7); /* Source control internal used (2) */
wr_reg(0xE8, 0x38); /* Source output period Normal mode */
wr_reg(0xE9, 0x10); /* Source output period Idle mode */
wr_reg(0xF1, 0x01); /* RGB 18-bit interface ;0x0110 */
wr_reg(0xF2, 0x10);
/* Adjust the Gamma Curve ------------------------------------------------*/
wr_reg(0x40, 0x01);
wr_reg(0x41, 0x00);
wr_reg(0x42, 0x00);
wr_reg(0x43, 0x10);
wr_reg(0x44, 0x0E);
wr_reg(0x45, 0x24);
wr_reg(0x46, 0x04);
wr_reg(0x47, 0x50);
wr_reg(0x48, 0x02);
wr_reg(0x49, 0x13);
wr_reg(0x4A, 0x19);
wr_reg(0x4B, 0x19);
wr_reg(0x4C, 0x16);
wr_reg(0x50, 0x1B);
wr_reg(0x51, 0x31);
wr_reg(0x52, 0x2F);
wr_reg(0x53, 0x3F);
wr_reg(0x54, 0x3F);
wr_reg(0x55, 0x3E);
wr_reg(0x56, 0x2F);
wr_reg(0x57, 0x7B);
wr_reg(0x58, 0x09);
wr_reg(0x59, 0x06);
wr_reg(0x5A, 0x06);
wr_reg(0x5B, 0x0C);
wr_reg(0x5C, 0x1D);
wr_reg(0x5D, 0xCC);
/* Power voltage setting -------------------------------------------------*/
wr_reg(0x1B, 0x1B);
wr_reg(0x1A, 0x01);
wr_reg(0x24, 0x2F);
wr_reg(0x25, 0x57);
wr_reg(0x23, 0x88);
/* Power on setting ------------------------------------------------------*/
wr_reg(0x18, 0x36); /* Internal oscillator frequency adj */
wr_reg(0x19, 0x01); /* Enable internal oscillator */
wr_reg(0x01, 0x00); /* Normal mode, no scrool */
wr_reg(0x1F, 0x88); /* Power control 6 - DDVDH Off */
delay(20);
wr_reg(0x1F, 0x82); /* Power control 6 - Step-up: 3 x VCI */
delay(5);
wr_reg(0x1F, 0x92); /* Power control 6 - Step-up: On */
delay(5);
wr_reg(0x1F, 0xD2); /* Power control 6 - VCOML active */
delay(5);
/* Color selection -------------------------------------------------------*/
wr_reg(0x17, 0x55); /* RGB, System interface: 16 Bit/Pixel*/
wr_reg(0x00, 0x00); /* Scrolling off, no standby */
/* Interface config ------------------------------------------------------*/
wr_reg(0x2F, 0x11); /* LCD Drive: 1-line inversion */
wr_reg(0x31, 0x00);
wr_reg(0x32, 0x00); /* DPL=0, HSPL=0, VSPL=0, EPL=0 */
/* Display on setting ----------------------------------------------------*/
wr_reg(0x28, 0x38); /* PT(0,0) active, VGL/VGL */
delay(20);
wr_reg(0x28, 0x3C); /* Display active, VGL/VGL */
#if (LANDSCAPE == 1)
#if (ROTATE180 == 0)
wr_reg (0x16, 0xA8);
#else
wr_reg (0x16, 0x68);
#endif
#else
#if (ROTATE180 == 0)
wr_reg (0x16, 0x08);
#else
wr_reg (0x16, 0xC8);
#endif
#endif
/* Display scrolling settings --------------------------------------------*/
wr_reg(0x0E, 0x00); /* TFA MSB */
wr_reg(0x0F, 0x00); /* TFA LSB */
wr_reg(0x10, 320 >> 8); /* VSA MSB */
wr_reg(0x11, 320 & 0xFF); /* VSA LSB */
wr_reg(0x12, 0x00); /* BFA MSB */
wr_reg(0x13, 0x00); /* BFA LSB */
}
void GLCD_init (void) {
#ifndef ILI9341
static unsigned short DriverCode;
#endif
// Hardware interface
// nCS PC6
// RS PD13
// nWR PD14
// nRD PD15
// DATA[15:0] PE[15:0]
/* Enable clock for GPIOA,B,C,D,E AFIO and SPI3. */
RCC->APB2ENR |= 0x0000007D;
/* PE output set to high. */
GPIOE->CRL = 0x33333333; // output push-pull
GPIOE->CRH = 0x33333333; // output push-pull
GPIOC->CRL &= 0xf0ffffff; // PC6 output push-pull 50MHz
GPIOC->CRL |= 0x03000000;
GPIOD->CRH &= 0x000fffff; //PD13,14,15 output push-pull 50MHz
GPIOD->CRH |= 0x33300000;
GPIOC->BSRR = 0x00000040; //cs = 1;
GPIOD->BSRR = 0x0000E000; //rs,wr,rd = 1;
delay(10); /* Delay 50 ms */
#ifdef ILI9341
ili9341_read_id();
wr_cmd(0x11);
delay(20);
wr_cmd(0xD0);
wr_dat(0x07);
wr_dat(0x41);
wr_dat(0x1F);
wr_cmd(0xD1);
wr_dat(0x00);
wr_dat(0x2C);
wr_dat(0x1A);
wr_cmd(0xD2);
wr_dat(0x01);
wr_dat(0x11);
wr_cmd(0xC0);
wr_dat(0x00);
wr_dat(0x3B);
wr_dat(0x00);
wr_dat(0x02);
wr_dat(0x11);
wr_cmd(0xC5);
wr_dat(0x02);
wr_cmd(0xC8);
wr_dat(0x07);
wr_dat(0x07);
wr_dat(0x07);
wr_dat(0x50);
wr_dat(0x08);
wr_dat(0x00);
wr_dat(0x07);
wr_dat(0x07);
wr_dat(0x07);
wr_dat(0x05);
wr_dat(0x02);
wr_dat(0x06);
wr_cmd(0x36); // MADCTRL (Memory Access Control)
wr_dat(0xE8); //0x4B, 0x48
wr_cmd(0x3A);
wr_dat(0x55);
wr_cmd(0xF0);
wr_dat(0x01);
wr_cmd(0xF3);
wr_dat(0x40);
wr_dat(0x0A);
wr_cmd(0x2A);
wr_dat(0x00);
wr_dat(0x00);
wr_dat(0x01);
wr_dat(0x3F);
wr_cmd(0x2B);
wr_dat(0x00);
wr_dat(0x00);
wr_dat(0x01);
wr_dat(0xDF);
delay(120);
wr_cmd(0x29);
wr_cmd(0x2C);
delay(5);
#else /* not ILI9341*/
DriverCode = rd_reg(0x00);
//printf ("GLCD driver code=%x\n", DriverCode);
if(DriverCode == 0x9320)
{
/* Start Initial Sequence --------------------------------------------------*/
wr_reg(0xE5, 0x8000); /* Set the internal vcore voltage */
wr_reg(0x00, 0x0001); /* Start internal OSC */
wr_reg(0x01, 0x0100); /* Set SS and SM bit */
wr_reg(0x02, 0x0700); /* Set 1 line inversion */
wr_reg(0x03, 0x1030); /* Set GRAM write direction and BGR=1 */
wr_reg(0x04, 0x0000); /* Resize register */
wr_reg(0x08, 0x0202); /* 2 lines each, back and front porch */
wr_reg(0x09, 0x0000); /* Set non-disp area refresh cyc ISC */
wr_reg(0x0A, 0x0000); /* FMARK function */
wr_reg(0x0C, 0x0000); /* RGB interface setting */
wr_reg(0x0D, 0x0000); /* Frame marker Position */
wr_reg(0x0F, 0x0000); /* RGB interface polarity */
/* Power On sequence -------------------------------------------------------*/
wr_reg(0x10, 0x0000); /* Reset Power Control 1 */
wr_reg(0x11, 0x0000); /* Reset Power Control 2 */
wr_reg(0x12, 0x0000); /* Reset Power Control 3 */
wr_reg(0x13, 0x0000); /* Reset Power Control 4 */
delay(20); /* Discharge cap power voltage (200ms)*/
wr_reg(0x10, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
wr_reg(0x11, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
delay(5); /* Delay 50 ms */
wr_reg(0x12, 0x0139); /* VREG1OUT voltage */
delay(5); /* Delay 50 ms */
wr_reg(0x13, 0x1D00); /* VDV[4:0] for VCOM amplitude */
wr_reg(0x29, 0x0013); /* VCM[4:0] for VCOMH */
delay(5); /* Delay 50 ms */
wr_reg(0x20, 0x0000); /* GRAM horizontal Address */
wr_reg(0x21, 0x0000); /* GRAM Vertical Address */
/* Adjust the Gamma Curve --------------------------------------------------*/
wr_reg(0x30, 0x0006);
wr_reg(0x31, 0x0101);
wr_reg(0x32, 0x0003);
wr_reg(0x35, 0x0106);
wr_reg(0x36, 0x0B02);
wr_reg(0x37, 0x0302);
wr_reg(0x38, 0x0707);
wr_reg(0x39, 0x0007);
wr_reg(0x3C, 0x0600);
wr_reg(0x3D, 0x020B);
/* Set GRAM area -----------------------------------------------------------*/
wr_reg(0x50, 0x0000); /* Horizontal GRAM Start Address */
wr_reg(0x51, (HEIGHT-1)); /* Horizontal GRAM End Address */
wr_reg(0x52, 0x0000); /* Vertical GRAM Start Address */
wr_reg(0x53, (WIDTH-1)); /* Vertical GRAM End Address */
wr_reg(0x60, 0x2700); /* Gate Scan Line */
wr_reg(0x61, 0x0001); /* NDL,VLE, REV */
wr_reg(0x6A, 0x0000); /* Set scrolling line */
/* Partial Display Control -------------------------------------------------*/
wr_reg(0x80, 0x0000);
wr_reg(0x81, 0x0000);
wr_reg(0x82, 0x0000);
wr_reg(0x83, 0x0000);
wr_reg(0x84, 0x0000);
wr_reg(0x85, 0x0000);
/* Panel Control -----------------------------------------------------------*/
wr_reg(0x90, 0x0010);
wr_reg(0x92, 0x0000);
wr_reg(0x93, 0x0003);
wr_reg(0x95, 0x0110);
wr_reg(0x97, 0x0000);
wr_reg(0x98, 0x0000);
/* Set GRAM write direction and BGR = 1
I/D=10 (Horizontal : increment, Vertical : increment)
AM=1 (address is updated in vertical writing direction) */
wr_reg(0x03, 0x1038);
wr_reg(0x07, 0x0173); /* 262K color and display ON */
}
else if(DriverCode == 0x7783)
{
// Start Initial Sequence
wr_reg(0x00FF,0x0001);
wr_reg(0x00F3,0x0008);
wr_reg(0x0001,0x0100);
wr_reg(0x0002,0x0700);
wr_reg(0x0003,0x1030); //0x1030
wr_reg(0x0008,0x0302);
wr_reg(0x0008,0x0207);
// Power On sequence
wr_reg(0x0009,0x0000);
wr_reg(0x000A,0x0000);
wr_reg(0x0010,0x0000); //0x0790
wr_reg(0x0011,0x0005);
wr_reg(0x0012,0x0000);
wr_reg(0x0013,0x0000);
delay(100);
wr_reg(0x0010,0x12B0);
delay(100);;
wr_reg(0x0011,0x0007);
delay(100);
wr_reg(0x0012,0x008B);
delay(100);
wr_reg(0x0013,0x1700);
delay(100);
wr_reg(0x0029,0x0022);
// void Gamma_Set(void)
wr_reg(0x0030,0x0000);
wr_reg(0x0031,0x0707);
wr_reg(0x0032,0x0505);
wr_reg(0x0035,0x0107);
wr_reg(0x0036,0x0008);
wr_reg(0x0037,0x0000);
wr_reg(0x0038,0x0202);
wr_reg(0x0039,0x0106);
wr_reg(0x003C,0x0202);
wr_reg(0x003D,0x0408);
delay(100);
// Set GRAM area
wr_reg(0x0050,0x0000);
wr_reg(0x0051,0x00EF);
wr_reg(0x0052,0x0000);
wr_reg(0x0053,0x013F);
wr_reg(0x0060,0xA700);
wr_reg(0x0061,0x0001);
wr_reg(0x0090,0x0033);
wr_reg(0x002B,0x000B);
/* Set GRAM write direction and BGR = 1
I/D=10 (Horizontal : increment, Vertical : increment)
AM=1 (address is updated in vertical writing direction) */
wr_reg(0x03, 0x1038);
wr_reg(0x0007,0x0133);
}
else
{
if (DriverCode == 0x9325)
{
//printf ("Init ILI9325 LCD module\n");
wr_reg(0x00e7,0x0010);
wr_reg(0x0000,0x0001);//??????
wr_reg(0x0001,0x0100);
wr_reg(0x0002,0x0700);//????
#define ID_AM 011
#if ID_AM==000
wr_reg(0x0003,0x1000); // TFM=0,TRI=0,SWAP=1,16 bits system interface swap RGB to BRG,ORG HWM 0
#elif ID_AM==001
wr_reg(0x0003,0x1008);
#elif ID_AM==010
wr_reg(0x0003,0x1010);
#elif ID_AM==011
wr_reg(0x0003,0x1018);
#elif ID_AM==100
wr_reg(0x0003,0x1020);
#elif ID_AM==101
wr_reg(0x0003,0x1028);
#elif ID_AM==110
wr_reg(0x0003,0x1030);
#elif ID_AM==111
wr_reg(0x0003,0x1038);
#endif
wr_reg(0x0004,0x0000);
wr_reg(0x0008,0x0207);
wr_reg(0x0009,0x0000);
wr_reg(0x000a,0x0000);//display setting
wr_reg(0x000c,0x0001);//display setting
wr_reg(0x000d,0x0000);//0f3c
wr_reg(0x000f,0x0000);
wr_reg(0x0010,0x0000);
wr_reg(0x0011,0x0007);
wr_reg(0x0012,0x0000);
wr_reg(0x0013,0x0000);
delay(5);
wr_reg(0x0010,0x1590);
wr_reg(0x0011,0x0227);
delay(5);
wr_reg(0x0012,0x009c);
delay(5);
wr_reg(0x0013,0x1900);
wr_reg(0x0029,0x0023);
wr_reg(0x002b,0x000e);
delay(5);
wr_reg(0x0020,0x0000);
wr_reg(0x0021,0x013f);
delay(5);
wr_reg(0x0030,0x0007);
wr_reg(0x0031,0x0707);
wr_reg(0x0032,0x0006);
wr_reg(0x0035,0x0704);
wr_reg(0x0036,0x1f04);
wr_reg(0x0037,0x0004);
wr_reg(0x0038,0x0000);
wr_reg(0x0039,0x0706);
wr_reg(0x003c,0x0701);
wr_reg(0x003d,0x000f);
delay(5);
wr_reg(0x0050,0x0000);
wr_reg(0x0051,0x00ef);
wr_reg(0x0052,0x0000);
wr_reg(0x0053,0x013f);
wr_reg(0x0060,0xa700);
wr_reg(0x0061,0x0001);
wr_reg(0x006a,0x0000);
wr_reg(0x0080,0x0000);
wr_reg(0x0081,0x0000);
wr_reg(0x0082,0x0000);
wr_reg(0x0083,0x0000);
wr_reg(0x0084,0x0000);
wr_reg(0x0085,0x0000);
wr_reg(0x0090,0x0010);
wr_reg(0x0092,0x0000);
wr_reg(0x0093,0x0003);
wr_reg(0x0095,0x0110);
wr_reg(0x0097,0x0000);
wr_reg(0x0098,0x0000);
wr_reg(0x0007,0x0133);
wr_reg(0x0020,0x0000);
wr_reg(0x0021,0x013f);
}
}
#endif /* ILI9341 */
}
void GLCD_init (void) {
static unsigned short DriverCode;
/* Enable clock for GPIOA,B,C,D,E AFIO and SPI3. */
RCC->APB2ENR |= 0x0000007D;
/* NCS is PB2, GPIO output set to high. */
GPIOE->CRL = 0x33333333; //设置PE口为50M通用推挽输出模式
GPIOE->CRH = 0x33333333;
GPIOC->CRL &= 0xf0ffffff; //PC6设置为50M通用推挽输出模式
GPIOC->CRL |= 0x03000000;
GPIOD->CRH &= 0x000fffff; //PD13,14,15设置为50M通用推挽输出模式
GPIOD->CRH |= 0x33300000;
GPIOC->BSRR = 0x00000040; //cs = 1;
GPIOD->BSRR = 0x0000E000; //rs,wr,rd = 1;
delay(5); /* Delay 50 ms */
DriverCode = rd_reg(0x00);
if(DriverCode == 0x9320)
{
/* Start Initial Sequence --------------------------------------------------*/
wr_reg(0xE5, 0x8000); /* Set the internal vcore voltage */
wr_reg(0x00, 0x0001); /* Start internal OSC */
wr_reg(0x01, 0x0100); /* Set SS and SM bit */
wr_reg(0x02, 0x0700); /* Set 1 line inversion */
wr_reg(0x03, 0x1030); /* Set GRAM write direction and BGR=1 */
wr_reg(0x04, 0x0000); /* Resize register */
wr_reg(0x08, 0x0202); /* 2 lines each, back and front porch */
wr_reg(0x09, 0x0000); /* Set non-disp area refresh cyc ISC */
wr_reg(0x0A, 0x0000); /* FMARK function */
wr_reg(0x0C, 0x0000); /* RGB interface setting */
wr_reg(0x0D, 0x0000); /* Frame marker Position */
wr_reg(0x0F, 0x0000); /* RGB interface polarity */
/* Power On sequence -------------------------------------------------------*/
wr_reg(0x10, 0x0000); /* Reset Power Control 1 */
wr_reg(0x11, 0x0000); /* Reset Power Control 2 */
wr_reg(0x12, 0x0000); /* Reset Power Control 3 */
wr_reg(0x13, 0x0000); /* Reset Power Control 4 */
delay(20); /* Discharge cap power voltage (200ms)*/
wr_reg(0x10, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
wr_reg(0x11, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
delay(5); /* Delay 50 ms */
wr_reg(0x12, 0x0139); /* VREG1OUT voltage */
delay(5); /* Delay 50 ms */
wr_reg(0x13, 0x1D00); /* VDV[4:0] for VCOM amplitude */
wr_reg(0x29, 0x0013); /* VCM[4:0] for VCOMH */
delay(5); /* Delay 50 ms */
wr_reg(0x20, 0x0000); /* GRAM horizontal Address */
wr_reg(0x21, 0x0000); /* GRAM Vertical Address */
/* Adjust the Gamma Curve --------------------------------------------------*/
wr_reg(0x30, 0x0006);
wr_reg(0x31, 0x0101);
wr_reg(0x32, 0x0003);
wr_reg(0x35, 0x0106);
wr_reg(0x36, 0x0B02);
wr_reg(0x37, 0x0302);
wr_reg(0x38, 0x0707);
wr_reg(0x39, 0x0007);
wr_reg(0x3C, 0x0600);
wr_reg(0x3D, 0x020B);
/* Set GRAM area -----------------------------------------------------------*/
wr_reg(0x50, 0x0000); /* Horizontal GRAM Start Address */
wr_reg(0x51, (HEIGHT-1)); /* Horizontal GRAM End Address */
wr_reg(0x52, 0x0000); /* Vertical GRAM Start Address */
wr_reg(0x53, (WIDTH-1)); /* Vertical GRAM End Address */
wr_reg(0x60, 0x2700); /* Gate Scan Line */
wr_reg(0x61, 0x0001); /* NDL,VLE, REV */
wr_reg(0x6A, 0x0000); /* Set scrolling line */
/* Partial Display Control -------------------------------------------------*/
wr_reg(0x80, 0x0000);
wr_reg(0x81, 0x0000);
wr_reg(0x82, 0x0000);
wr_reg(0x83, 0x0000);
wr_reg(0x84, 0x0000);
wr_reg(0x85, 0x0000);
/* Panel Control -----------------------------------------------------------*/
wr_reg(0x90, 0x0010);
wr_reg(0x92, 0x0000);
wr_reg(0x93, 0x0003);
wr_reg(0x95, 0x0110);
wr_reg(0x97, 0x0000);
wr_reg(0x98, 0x0000);
/* Set GRAM write direction and BGR = 1
I/D=10 (Horizontal : increment, Vertical : increment)
AM=1 (address is updated in vertical writing direction) */
wr_reg(0x03, 0x1038);
// wr_reg(0x03, 0x1018);
wr_reg(0x07, 0x0173); /* 262K color and display ON */
}
else if(DriverCode == 0x9325)
{
// Start Initial Sequence
wr_reg(0x00FF,0x0001);
wr_reg(0x00F3,0x0008);
wr_reg(0x0001,0x0100);
wr_reg(0x0002,0x0700);
wr_reg(0x0003,0x1030); //0x1030
wr_reg(0x0008,0x0302);
wr_reg(0x0008,0x0207);
// Power On sequence
wr_reg(0x0009,0x0000);
wr_reg(0x000A,0x0000);
wr_reg(0x0010,0x0000); //0x0790
wr_reg(0x0011,0x0005);
wr_reg(0x0012,0x0000);
wr_reg(0x0013,0x0000);
delay(5);
wr_reg(0x0010,0x12B0);
delay(5);
wr_reg(0x0011,0x0007);
delay(5);
wr_reg(0x0012,0x008B);
delay(5);
wr_reg(0x0013,0x1700);
delay(5);
wr_reg(0x0029,0x0022);
// void Gamma_Set(void)
wr_reg(0x0030,0x0000);
wr_reg(0x0031,0x0707);
wr_reg(0x0032,0x0505);
wr_reg(0x0035,0x0107);
wr_reg(0x0036,0x0008);
wr_reg(0x0037,0x0000);
wr_reg(0x0038,0x0202);
wr_reg(0x0039,0x0106);
wr_reg(0x003C,0x0202);
wr_reg(0x003D,0x0408);
delay(5);
// Set GRAM area
wr_reg(0x0050,0x0000);
wr_reg(0x0051,0x00EF);
wr_reg(0x0052,0x0000);
wr_reg(0x0053,0x013F);
wr_reg(0x0060,0xA700);
wr_reg(0x0061,0x0001);
wr_reg(0x0090,0x0033);
wr_reg(0x002B,0x000B);
/* Set GRAM write direction and BGR = 1
I/D=10 (Horizontal : increment, Vertical : increment)
AM=1 (address is updated in vertical writing direction) */
wr_reg(0x03, 0x1038);
wr_reg(0x0007,0x0133);
}
}
void GLCD_Init (void) {
static unsigned short driverCode;
/* Configure the LCD Control pins */
//LPC_GPIO0->FIODIR |= 0x03f80000;
///LPC_GPIO0->FIOSET = 0x03f80000;
DDRD&=~(0x20);
PORTD|=0xFF;
//LCD_OUPUT();
delay(5); /* Delay 50 ms */
driverCode = rd_reg(0x00);
if(driverCode == 0x4531) //2.8" TFT LCD Module,DriverIC is LGDP4531
{
wr_reg(0x00,0x0001);
wr_reg(0x10,0x0628);
wr_reg(0x12,0x0006);
wr_reg(0x13,0x0A32);
wr_reg(0x11,0x0040);
wr_reg(0x15,0x0050);
wr_reg(0x12,0x0016);
delay(15);
wr_reg(0x10,0x5660);
delay(15);
wr_reg(0x13,0x2A4E);
wr_reg(0x01,0x0100);
wr_reg(0x02,0x0300);
wr_reg(0x03,0x1030);
wr_reg(0x08,0x0202);
wr_reg(0x0A,0x0000);
wr_reg(0x30,0x0000);
wr_reg(0x31,0x0402);
wr_reg(0x32,0x0106);
wr_reg(0x33,0x0700);
wr_reg(0x34,0x0104);
wr_reg(0x35,0x0301);
wr_reg(0x36,0x0707);
wr_reg(0x37,0x0305);
wr_reg(0x38,0x0208);
wr_reg(0x39,0x0F0B);
delay(15);
wr_reg(0x41,0x0002);
wr_reg(0x60,0x2700);
wr_reg(0x61,0x0001);
wr_reg(0x90,0x0119);
wr_reg(0x92,0x010A);
wr_reg(0x93,0x0004);
wr_reg(0xA0,0x0100);
delay(15);
wr_reg(0xA0,0x0000);
delay(20);
}
else if(driverCode == 0x9320) //3.2" TFT LCD Module,DriverIC is ILI9320
{
/* Start Initial Sequence --------------------------------------------------*/
wr_reg(0xE5, 0x8000); /* Set the internal vcore voltage */
wr_reg(0x00, 0x0001); /* Start internal OSC */
wr_reg(0x01, 0x0100); /* Set SS and SM bit */
wr_reg(0x02, 0x0700); /* Set 1 line inversion */
wr_reg(0x03, 0x1030); /* Set GRAM write direction and BGR=1 */
wr_reg(0x04, 0x0000); /* Resize register */
wr_reg(0x08, 0x0202); /* 2 lines each, back and front porch */
wr_reg(0x09, 0x0000); /* Set non-disp area refresh cyc ISC */
wr_reg(0x0A, 0x0000); /* FMARK function */
wr_reg(0x0C, 0x0000); /* RGB interface setting */
wr_reg(0x0D, 0x0000); /* Frame marker Position */
wr_reg(0x0F, 0x0000); /* RGB interface polarity */
/* Power On sequence -------------------------------------------------------*/
wr_reg(0x10, 0x0000); /* Reset Power Control 1 */
wr_reg(0x11, 0x0000); /* Reset Power Control 2 */
wr_reg(0x12, 0x0000); /* Reset Power Control 3 */
wr_reg(0x13, 0x0000); /* Reset Power Control 4 */
delay(20); /* Discharge cap power voltage (200ms)*/
wr_reg(0x10, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
wr_reg(0x11, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
delay(5); /* Delay 50 ms */
wr_reg(0x12, 0x0139); /* VREG1OUT voltage */
delay(5); /* Delay 50 ms */
wr_reg(0x13, 0x1D00); /* VDV[4:0] for VCOM amplitude */
wr_reg(0x29, 0x0013); /* VCM[4:0] for VCOMH */
delay(5); /* Delay 50 ms */
wr_reg(0x20, 0x0000); /* GRAM horizontal Address */
wr_reg(0x21, 0x0000); /* GRAM Vertical Address */
/* Adjust the Gamma Curve --------------------------------------------------*/
wr_reg(0x30, 0x0006);
wr_reg(0x31, 0x0101);
wr_reg(0x32, 0x0003);
wr_reg(0x35, 0x0106);
wr_reg(0x36, 0x0B02);
wr_reg(0x37, 0x0302);
wr_reg(0x38, 0x0707);
wr_reg(0x39, 0x0007);
wr_reg(0x3C, 0x0600);
wr_reg(0x3D, 0x020B);
/* Set GRAM area -----------------------------------------------------------*/
wr_reg(0x50, 0x0000); /* Horizontal GRAM Start Address */
wr_reg(0x51, (HEIGHT-1)); /* Horizontal GRAM End Address */
wr_reg(0x52, 0x0000); /* Vertical GRAM Start Address */
wr_reg(0x53, (WIDTH-1)); /* Vertical GRAM End Address */
wr_reg(0x60, 0x2700); /* Gate Scan Line */
wr_reg(0x61, 0x0001); /* NDL,VLE, REV */
wr_reg(0x6A, 0x0000); /* Set scrolling line */
/* Partial Display Control -------------------------------------------------*/
wr_reg(0x80, 0x0000);
wr_reg(0x81, 0x0000);
wr_reg(0x82, 0x0000);
wr_reg(0x83, 0x0000);
wr_reg(0x84, 0x0000);
wr_reg(0x85, 0x0000);
/* Panel Control -----------------------------------------------------------*/
wr_reg(0x90, 0x0010);
wr_reg(0x92, 0x0000);
wr_reg(0x93, 0x0003);
wr_reg(0x95, 0x0110);
wr_reg(0x97, 0x0000);
wr_reg(0x98, 0x0000);
}
/* Set GRAM write direction and BGR = 1
I/D=10 (Horizontal : increment, Vertical : increment)
AM=1 (address is updated in vertical writing direction) */
wr_reg(0x03, 0x1038);
wr_reg(0x07, 0x0173); /* 262K color and display ON */
}
/*********************************************************************
*
* _InitController
*
* Purpose:
* Initializes the display controller
*/
static void _InitController(void) {
#ifndef WIN32
U16 driverCode;
LCD_X_Init();
driverCode = rd_reg(0x00);
/* Start Initial Sequence ----------------------------------------*/
wr_reg(0x01, 0x0100); /* Set SS bit */
wr_reg(0x02, 0x0700); /* Set 1 line inversion */
wr_reg(0x04, 0x0000); /* Resize register */
wr_reg(0x08, 0x0207); /* 2 lines front, 7 back porch */
wr_reg(0x09, 0x0000); /* Set non-disp area refresh cyc ISC */
wr_reg(0x0A, 0x0000); /* FMARK function */
wr_reg(0x0C, 0x0000); /* RGB interface setting */
wr_reg(0x0D, 0x0000); /* Frame marker Position */
wr_reg(0x0F, 0x0000); /* RGB interface polarity */
/* Power On sequence ---------------------------------------------*/
wr_reg(0x10, 0x0000); /* Reset Power Control 1 */
wr_reg(0x11, 0x0000); /* Reset Power Control 2 */
wr_reg(0x12, 0x0000); /* Reset Power Control 3 */
wr_reg(0x13, 0x0000); /* Reset Power Control 4 */
GUI_Delay(200); /* Discharge cap power voltage (200ms)*/
wr_reg(0x10, 0x12B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
wr_reg(0x11, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
GUI_Delay(50); /* Delay 50 ms */
wr_reg(0x12, 0x01BD); /* VREG1OUT voltage */
GUI_Delay(50); /* Delay 50 ms */
wr_reg(0x13, 0x1400); /* VDV[4:0] for VCOM amplitude */
wr_reg(0x29, 0x000E); /* VCM[4:0] for VCOMH */
GUI_Delay(50); /* Delay 50 ms */
wr_reg(0x20, 0x0000); /* GRAM horizontal Address */
wr_reg(0x21, 0x0000); /* GRAM Vertical Address */
/* Adjust the Gamma Curve ----------------------------------------*/
switch (driverCode) {
case 0x5408: /* LCD with SPFD5408 LCD Controller */
wr_reg(0x30, 0x0B0D);
wr_reg(0x31, 0x1923);
wr_reg(0x32, 0x1C26);
wr_reg(0x33, 0x261C);
wr_reg(0x34, 0x2419);
wr_reg(0x35, 0x0D0B);
wr_reg(0x36, 0x1006);
wr_reg(0x37, 0x0610);
wr_reg(0x38, 0x0706);
wr_reg(0x39, 0x0304);
wr_reg(0x3A, 0x0E05);
wr_reg(0x3B, 0x0E01);
wr_reg(0x3C, 0x010E);
wr_reg(0x3D, 0x050E);
wr_reg(0x3E, 0x0403);
wr_reg(0x3F, 0x0607);
break;
case 0x9325: /* LCD with RM68050 LCD Controller */
wr_reg(0x30, 0x0000);
wr_reg(0x31, 0x0607);
wr_reg(0x32, 0x0305);
wr_reg(0x35, 0x0000);
wr_reg(0x36, 0x1604);
wr_reg(0x37, 0x0204);
wr_reg(0x38, 0x0001);
wr_reg(0x39, 0x0707);
wr_reg(0x3C, 0x0000);
wr_reg(0x3D, 0x000F);
break;
case 0x9320: /* LCD with ILI9320 LCD Controller */
default: /* LCD with other LCD Controller */
wr_reg(0x30, 0x0006);
wr_reg(0x31, 0x0101);
wr_reg(0x32, 0x0003);
wr_reg(0x35, 0x0106);
wr_reg(0x36, 0x0B02);
wr_reg(0x37, 0x0302);
wr_reg(0x38, 0x0707);
wr_reg(0x39, 0x0007);
wr_reg(0x3C, 0x0600);
wr_reg(0x3D, 0x020B);
break;
}
/* Set GRAM area -------------------------------------------------*/
wr_reg(0x50, 0x0000); /* Horizontal GRAM Start Address */
wr_reg(0x51, (HEIGHT-1)); /* Horizontal GRAM End Address */
wr_reg(0x52, 0x0000); /* Vertical GRAM Start Address */
wr_reg(0x53, (WIDTH-1)); /* Vertical GRAM End Address */
/* Set Gate Scan Line --------------------------------------------*/
switch (driverCode) {
case 0x5408: /* LCD with SPFD5408 LCD Controller */
case 0x9325: /* LCD with RM68050 LCD Controller */
wr_reg(0x60, 0xA700);
break;
case 0x9320: /* LCD with ILI9320 LCD Controller */
default: /* LCD with other LCD Controller */
wr_reg(0x60, 0x2700);
break;
}
wr_reg(0x61, 0x0001); /* NDL,VLE, REV */
wr_reg(0x6A, 0x0000); /* Set scrolling line */
/* Partial Display Control ---------------------------------------*/
wr_reg(0x80, 0x0000);
wr_reg(0x81, 0x0000);
wr_reg(0x82, 0x0000);
wr_reg(0x83, 0x0000);
wr_reg(0x84, 0x0000);
wr_reg(0x85, 0x0000);
/* Panel Control -------------------------------------------------*/
wr_reg(0x90, 0x0010);
wr_reg(0x92, 0x0000);
wr_reg(0x93, 0x0003);
wr_reg(0x95, 0x0110);
wr_reg(0x97, 0x0000);
wr_reg(0x98, 0x0000);
//wr_reg(0x03, 0x0000); /* Entry Mode (AM,ID0/1,ORG,BGR) */
wr_reg(0x07, 0x0137); /* 262K color and display ON */
#endif /* WIN32 */
}
void GLCD_init (void) {
static unsigned short driverCode;
/* Enable clock for GPIOB,C AFIO and SPI3. */
RCC->APB2ENR |= 0x00000019;
RCC->APB1ENR |= 0x00008000;
/* Set SPI3 remap (use PC10..PC12). */
AFIO->MAPR |= 0x10000000;
/* NCS is PB2, GPIO output set to high. */
GPIOB->CRL &= 0xFFFFF0FF;
GPIOB->CRL |= 0x00000300;
GPIOB->BSRR = 0x00000004;
/* SPI3_SCK, SPI3_MISO, SPI3_MOSI are SPI pins. */
GPIOC->CRH &= 0xFFF000FF;
GPIOC->CRH |= 0x000B8B00;
/* Enable SPI in Master Mode, CPOL=1, CPHA=1. */
/* Max. 18 MBit used for Data Transfer @ 72MHz. */
SPI3->CR1 = 0x0347;
SPI3->CR2 = 0x0000;
delay(5); /* Delay 50 ms */
driverCode = rd_reg(0x00);
/* Start Initial Sequence --------------------------------------------------*/
wr_reg(0xE5, 0x8000); /* Set the internal vcore voltage */
wr_reg(0x00, 0x0001); /* Start internal OSC */
wr_reg(0x01, 0x0100); /* Set SS and SM bit */
wr_reg(0x02, 0x0700); /* Set 1 line inversion */
wr_reg(0x03, 0x1030); /* Set GRAM write direction and BGR=1 */
wr_reg(0x04, 0x0000); /* Resize register */
wr_reg(0x08, 0x0202); /* 2 lines each, back and front porch */
wr_reg(0x09, 0x0000); /* Set non-disp area refresh cyc ISC */
wr_reg(0x0A, 0x0000); /* FMARK function */
wr_reg(0x0C, 0x0000); /* RGB interface setting */
wr_reg(0x0D, 0x0000); /* Frame marker Position */
wr_reg(0x0F, 0x0000); /* RGB interface polarity */
/* Power On sequence -------------------------------------------------------*/
wr_reg(0x10, 0x0000); /* Reset Power Control 1 */
wr_reg(0x11, 0x0000); /* Reset Power Control 2 */
wr_reg(0x12, 0x0000); /* Reset Power Control 3 */
wr_reg(0x13, 0x0000); /* Reset Power Control 4 */
delay(20); /* Discharge cap power voltage (200ms)*/
wr_reg(0x10, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
wr_reg(0x11, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
delay(5); /* Delay 50 ms */
wr_reg(0x12, 0x0139); /* VREG1OUT voltage */
delay(5); /* Delay 50 ms */
wr_reg(0x13, 0x1D00); /* VDV[4:0] for VCOM amplitude */
wr_reg(0x29, 0x0013); /* VCM[4:0] for VCOMH */
delay(5); /* Delay 50 ms */
wr_reg(0x20, 0x0000); /* GRAM horizontal Address */
wr_reg(0x21, 0x0000); /* GRAM Vertical Address */
/* Adjust the Gamma Curve --------------------------------------------------*/
wr_reg(0x30, 0x0006);
wr_reg(0x31, 0x0101);
wr_reg(0x32, 0x0003);
wr_reg(0x35, 0x0106);
wr_reg(0x36, 0x0B02);
wr_reg(0x37, 0x0302);
wr_reg(0x38, 0x0707);
wr_reg(0x39, 0x0007);
wr_reg(0x3C, 0x0600);
wr_reg(0x3D, 0x020B);
/* Set GRAM area -----------------------------------------------------------*/
wr_reg(0x50, 0x0000); /* Horizontal GRAM Start Address */
wr_reg(0x51, (HEIGHT-1)); /* Horizontal GRAM End Address */
wr_reg(0x52, 0x0000); /* Vertical GRAM Start Address */
wr_reg(0x53, (WIDTH-1)); /* Vertical GRAM End Address */
wr_reg(0x60, 0x2700); /* Gate Scan Line */
wr_reg(0x61, 0x0001); /* NDL,VLE, REV */
wr_reg(0x6A, 0x0000); /* Set scrolling line */
/* Partial Display Control -------------------------------------------------*/
wr_reg(0x80, 0x0000);
wr_reg(0x81, 0x0000);
wr_reg(0x82, 0x0000);
wr_reg(0x83, 0x0000);
wr_reg(0x84, 0x0000);
wr_reg(0x85, 0x0000);
/* Panel Control -----------------------------------------------------------*/
wr_reg(0x90, 0x0010);
wr_reg(0x92, 0x0000);
wr_reg(0x93, 0x0003);
wr_reg(0x95, 0x0110);
wr_reg(0x97, 0x0000);
wr_reg(0x98, 0x0000);
/* Set GRAM write direction and BGR = 1
I/D=10 (Horizontal : increment, Vertical : increment)
AM=1 (address is updated in vertical writing direction) */
wr_reg(0x03, 0x1038);
wr_reg(0x07, 0x0173); /* 262K color and display ON */
}
