/* Erratum 350 */
static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
{
u8 u8Channel;
u8 u8Receiver;
u32 u32Addr;
u8 u8Valid;
u32 u32DctDev;
// 1. dummy read for each installed DIMM */
for (u8Channel = 0; u8Channel < 2; u8Channel++) {
// This will be 0 for vaild DIMMS, eles 8
u8Receiver = mct_InitReceiver_D(pDCTstat, u8Channel);
for (; u8Receiver < 8; u8Receiver += 2) {
u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid);
if(!u8Valid) { /* Address not supported on current CS */
print_t("vErrata350: Address not supported on current CS\n");
continue;
}
print_t("vErrata350: dummy read \n");
read32_fs(u32Addr);
}
}
print_t("vErrata350: step 2a\n");
/* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */
u32DctDev = pDCTstat->dev_dct;
Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000);
/* ^--- value
^---F2x[1, 0]9C_x0D080F0C, No description in BKDG.
^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
if(!pDCTstat->GangedMode) {
print_t("vErrata350: step 2b\n");
Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00008000);
/* ^--- value
^---F2x[1, 0]9C_x0D080F0C, No description in BKDG
^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
}
print_t("vErrata350: step 3\n");
/* 3. Wait at least 300 nanoseconds. */
coreDelay(1);
print_t("vErrata350: step 4\n");
/* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */
Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00000000);
if(!pDCTstat->GangedMode) {
print_t("vErrata350: step 4b\n");
Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00000000);
}
print_t("vErrata350: step 5\n");
/* 5. Wait at least 2 microseconds. */
coreDelay(2);
}
static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr)
{
/* Compare only the first beat of data. Since target addrs are cache
* line aligned, the Channel parameter is used to determine which cache
* QW to compare.
*/
u32 *test_buf = (u32 *)pattern_buf;
u32 addr_lo;
u32 val, val_test;
int i;
u8 ret = DQS_PASS;
SetUpperFSbase(addr);
addr_lo = addr << 8;
_EXECFENCE;
for (i = 0; i < (16*3); i++) {
val = read32_fs(addr_lo);
val_test = test_buf[i];
print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", val_test, 5);
print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", val, 5);
if (val != val_test) {
ret = DQS_FAIL;
break;
}
addr_lo += 4;
}
return ret;
}
