void __init brcm_route_irq(void)
{
uint32 cp0Reg;
uint32 crossover;
if( ((unsigned int)read_c0_diag3() >> 31) == 0 )
{
return;
}
else
{
void __init prom_init(void)
{
#if 0
int argc = fw_arg0;
u32 *argv = (u32 *)CKSEG0ADDR(fw_arg1);
int i;
kerSysEarlyFlashInit();
// too early in bootup sequence to acquire spinlock, not needed anyways
// only the kernel is running at this point
kerSysNvRamGetBoardIdLocked(promBoardIdStr);
printk( "%s prom init\n", promBoardIdStr );
#if defined(CONFIG_BCM_KF_DSP) && defined(CONFIG_BCM_BCMDSP_MODULE)
main_tp_num = ((read_c0_diag3() & CP0_CMT_TPID) == CP0_CMT_TPID) ? 1 : 0;
printk("Linux TP ID = %u \n", (unsigned int)main_tp_num);
#endif
PERF->IrqControl[0].IrqMask=0;
arcs_cmdline[0] = '\0';
create_cmdline(arcs_cmdline);
strcat(arcs_cmdline, " ");
for (i = 1; i < argc; i++) {
strcat(arcs_cmdline, (char *)CKSEG0ADDR(argv[i]));
if (i < (argc - 1))
strcat(arcs_cmdline, " ");
}
/* Count register increments every other clock */
mips_hpt_frequency = calculateCpuSpeed() / 2;
retrieve_boot_loader_parameters();
#endif
}
void __init prom_init(void)
{
#ifdef CONFIG_MIPS_BRCM97XXX
int hasCfeParms = 0;
int res = -1;
char msg[COMMAND_LINE_SIZE];
extern void determineBootFromFlashOrRom(void);
#endif
uart_init(27000000);
/* jipeng - mask out UPG L2 interrupt here */
BDEV_WR(BCHP_IRQ0_IRQEN, 0);
#ifdef CONFIG_TIVO_KONTIKI
board_pinmux_setup();
#endif
/* Fill in platform information */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BRCM_STB;
#ifdef BRCM_SATA_SUPPORTED
brcm_sata_enabled = 1;
#endif
#ifdef BRCM_ENET_SUPPORTED
brcm_enet_enabled = 1;
#endif
#ifdef BRCM_EMAC_1_SUPPORTED
brcm_emac_1_enabled = 1;
#endif
#ifdef BRCM_PCI_SUPPORTED
brcm_pci_enabled = 1;
#endif
#ifdef CONFIG_SMP
brcm_smp_enabled = 1;
#endif
#ifdef CONFIG_MIPS_BCM7118
/* detect 7118RNG board */
if( BDEV_RD(BCHP_CLKGEN_REG_START) == 0x1c )
brcm_sata_enabled = 0;
/* onchip DOCSIS owns the ENET */
brcm_enet_enabled = 0;
#endif
#ifdef CONFIG_MIPS_BCM7405
/* detect 7406 */
if(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) &
BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_sata_disable_MASK)
brcm_sata_enabled = 0;
switch(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) & 0xf) {
case 0x0:
/* 7405/7406 */
break;
case 0x1:
/* 7466 */
brcm_pci_enabled = 0;
brcm_emac_1_enabled = 0;
break;
case 0x3:
/* 7106 */
brcm_emac_1_enabled = 0;
brcm_smp_enabled = 0;
break;
case 0x4:
/* 7205 */
brcm_emac_1_enabled = 0;
break;
}
#endif
#if defined( CONFIG_MIPS_BCM7118 ) || defined( CONFIG_MIPS_BCM7401C0 ) \
|| defined( CONFIG_MIPS_BCM7402C0 ) || defined( CONFIG_MIPS_BCM3563 ) \
|| defined (CONFIG_MIPS_BCM3563C0)
/*need set bus to async mode before enabling the following*/
if(!(read_c0_diag4() & 0x400000))
{
int val=read_c0_diag4();
write_c0_diag4(val | 0x400000);
sprintf(msg, "CP0 reg 22 sel 0 to 5: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", read_c0_diag(), read_c0_diag1(), read_c0_diag2(), read_c0_diag3(), read_c0_diag4(), read_c0_diag5());
uart_puts(msg);
write_c0_config(0x80008083);
sprintf(msg, "CP0 reg 16 sel 0 to 1: 0x%08x 0x%08x \n", read_c0_config(), read_c0_config1());
uart_puts(msg);
}
/* Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT) */
BDEV_WR(0x0000040c, 0x264);
/* Enable Split Mode (BCHP_MISB_BRIDGE_MISB_SPLIT_MODE) */
BDEV_WR(0x00000410, 0x1);
#elif defined( CONFIG_MIPS_BCM7440A0 )
if(!(read_c0_diag4() & 0x400000))
{
int val=read_c0_diag4();
write_c0_diag4(val | 0x400000);
sprintf(msg, "CP0 reg 22 sel 0 to 5: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", read_c0_diag(), read_c0_diag1(), read_c0_diag2(), read_c0_diag3(), read_c0_diag4(), read_c0_diag5());
uart_puts(msg);
write_c0_config(0x80008083);
sprintf(msg, "CP0 reg 16 sel 0 to 1: 0x%08x 0x%08x \n", read_c0_config(), read_c0_config1());
uart_puts(msg);
}
/* Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT) */
BDEV_WR(0x0000040c, 0x2803);
#endif
#ifdef CONFIG_TIVO_MOJAVE
if ( cfe_seal != CFE_SEAL ){
goto noncfe;
}
#endif
/* Kernel arguments */
#ifdef CONFIG_MIPS_BRCM97XXX
/* For the 97xxx series STB, process CFE boot parms */
{
int i;
for (i=0; i<MAX_HWADDR; i++) {
gHwAddrs[i] = &privHwAddrs[i][0];
}
}
#ifdef CONFIG_TIVO_KONTIKI
res = get_cfe_boot_parms();
hasCfeParms = (res == 0);
#if 1 /* ###JLF */
if (gNumHwAddrs > 0)
{
printk("%s(): Got CFE MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x\n",
__FUNCTION__,
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5]);
}
#endif
#ifdef BRCM_MEMORY_STRAPS
get_RAM_size();
#else
if(brcm_dram0_size == 0)
brcm_dram0_size = probe_memsize();
#ifndef CONFIG_DISCONTIGMEM
if(brcm_dram0_size > (256 << 20)) {
printk("Extra RAM beyond 256MB ignored. Please "
"use a kernel that supports DISCONTIG.\n");
brcm_dram0_size = 256 << 20;
}
#endif /* CONFIG_DISCONTIGMEM */
#endif /* BRCM_MEMORY_STRAPS */
// Make sure cfeBootParms is not empty or contains all white space
if (hasCfeParms) {
int i;
hasCfeParms = 0;
for (i=0; i < strlen(cfeBootParms); i++) {
if (isspace(cfeBootParms[i])) {
continue;
}
else if (cfeBootParms[i] == '\0') {
break; // and leave hasCfeParms false
}
else {
hasCfeParms = 1;
break;
}
}
}
#else /* if !defined(CONFIG_TIVO_KONTIKI) */
res = get_cfe_boot_parms(cfeBootParms, &gNumHwAddrs, gHwAddrs);
if(gNumHwAddrs <= 0) {
#if !defined(CONFIG_BRCM_PCI_SLAVE)
unsigned int i, mac = FLASH_MACADDR_ADDR, ok = 0;
for(i = 0; i < 3; i++) {
u16 word = readw((void *)mac);
if(word != 0x0000 && word != 0xffff)
ok = 1;
gHwAddrs[0][(i << 1)] = word & 0xff;
gHwAddrs[0][(i << 1) + 1] = word >> 8;
mac += 2;
}
/* display warning for all 00's, all ff's, or multicast */
if(! ok || (gHwAddrs[0][1] & 1)) {
printk(KERN_WARNING
"WARNING: read invalid MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x from flash @ 0x%08x\n",
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5],
FLASH_MACADDR_ADDR);
}
#else
/* PCI slave mode - no EBI/flash available */
u8 fixed_macaddr[] = { 0x00, 0xc0, 0xa8, 0x74, 0x3b, 0x51 };
memcpy(&gHwAddrs[0][0], fixed_macaddr, sizeof(fixed_macaddr));
#endif
gNumHwAddrs = 1;
}