void dump_timer_regs(void)
{
#if 0
unsigned int cntfrq = 0xFFFFFFFF;
unsigned int cntkctl = 0xFFFFFFFF;
#endif
unsigned int cntpct_lo = 0xFFFFFFFF;
unsigned int cntpct_hi = 0xFFFFFFFF;
#if 0
unsigned int cntvct_lo = 0xFFFFFFFF;
unsigned int cntvct_hi = 0xFFFFFFFF;
#endif
unsigned int cntp_ctl = 0xFFFFFFFF;
unsigned int cntp_cval_lo = 0xFFFFFFFF;
unsigned int cntp_cval_hi = 0xFFFFFFFF;
unsigned int cntp_tval = 0xFFFFFFFF;
#if 0
unsigned int cntv_ctl = 0xFFFFFFFF;
unsigned int cntv_cval_lo = 0xFFFFFFFF;
unsigned int cntv_cval_hi = 0xFFFFFFFF;
unsigned int cntv_tval = 0xFFFFFFFF;
#endif
#if 0
read_cntfrq(cntfrq);
read_cntkctl(cntkctl);
#endif
read_cntpct(cntpct_lo, cntpct_hi);
#if 0
read_cntvct(cntvct_lo, cntvct_hi);
#endif
read_cntp_ctl(cntp_ctl);
read_cntp_cval(cntp_cval_lo, cntp_cval_hi);
read_cntp_tval(cntp_tval);
#if 0
read_cntv_ctl(cntv_ctl);
read_cntv_cval(cntv_cval_lo, cntv_cval_hi);
read_cntv_tval(cntv_tval);
#endif
#if 0
printk("[ca7_timer]0. cntfrq = 0x%x\n", cntfrq);
printk("[ca7_timer]1. cntkctl = 0x%x\n", cntkctl);
#endif
printk("[ca7_timer]2. cntpct_lo = 0x%08x, cntpct_hi = 0x%08x\n", cntpct_lo, cntpct_hi);
#if 0
printk("[ca7_timer]3. cntvct_lo = 0x%08x, cntvct_hi = 0x%08x\n", cntvct_lo, cntvct_hi);
#endif
printk("[ca7_timer]4. cntp_ctl = 0x%x\n", cntp_ctl);
printk("[ca7_timer]5. cntp_cval_lo = 0x%08x, cntp_cval_hi = 0x%08x\n", cntp_cval_lo, cntp_cval_hi);
printk("[ca7_timer]6. cntp_tval = 0x%08x\n", cntp_tval);
#if 0
printk("[ca7_timer]7. cntv_ctl = 0x%x\n", cntv_ctl);
printk("[ca7_timer]8. cntv_cval_lo = 0x%08x, cntv_cval_hi = 0x%08x\n", cntv_cval_lo, cntv_cval_hi);
printk("[ca7_timer]9. cntv_tval = 0x%08x\n", cntv_tval);
#endif
}
int spm_wfi_for_sodi_test(void *sodi_data)
{
volatile u32 do_not_change_it;
volatile u32 lo, hi, core_id;
unsigned long flags;
//u32 temp_address;
preempt_disable();
do_not_change_it = 1;
MCDI_Test_Mode = 1;
while(do_not_change_it)
{
/* Mask ARM i bit */
local_irq_save(flags);
core_id = (u32)smp_processor_id();
// set local timer & GPT =========================================
switch (core_id)
{
case 0 :
read_cntp_cval(lo, hi);
hi+=0xffffffff; // very very long
write_cntp_cval(lo, hi);
write_cntp_ctl(0x1); // CNTP_CTL_ENABLE
break;
case 1 :
stop_gpt(GPT4); // disable GPT
break;
default : break;
}
spm_mcdi_wfi();
/* Un-Mask ARM i bit */
local_irq_restore(flags);
}
preempt_enable();
return 0;
}
int dump_localtimer_register(char* buffer, int size)
{
int i;
int len = 0;
#define LOCAL_LEN 256
char fmt[LOCAL_LEN];
unsigned int cntp_ctl;
unsigned int cntp_tval;
unsigned int cntp_cval_lo, cntp_cval_hi;
unsigned int cntpct_lo, cntpct_hi;
if (!buffer || size <= 1) {
return 0;
}
len += snprintf(fmt + len, LOCAL_LEN - len, "[localtimer]cpu evt ctl ext time\n");
for (i = 0; i < nr_cpu_ids; i++) {
len += snprintf(fmt + len, LOCAL_LEN - len, "%d %lx %x %d %llx\n",
i, save_data[i].evt, save_data[i].ctrl,
save_data[i].ext, save_data[i].timestamp);
}
read_cntp_ctl(cntp_ctl);
read_cntp_cval(cntp_cval_lo, cntp_cval_hi);
read_cntp_tval(cntp_tval);
read_cntpct(cntpct_lo, cntpct_hi);
len += snprintf(fmt + len, LOCAL_LEN - len, "cpu ctl tval cval pct\n");
len += snprintf(fmt + len, LOCAL_LEN - len,
"%d %x %x (%x,%x) (%x,%x)\n",
smp_processor_id(), cntp_ctl, cntp_tval,
cntp_cval_lo, cntp_cval_hi, cntpct_lo, cntpct_hi);
len = min(len, size - 1);
memcpy(buffer, fmt, len);
*(buffer + len) = '\0';
return len;
}
int spm_wfi_for_mcdi_test(void *mcdi_data)
{
volatile u32 do_not_change_it;
volatile u32 lo, hi, core_id;
unsigned long flags;
preempt_disable();
do_not_change_it = 1;
MCDI_Test_Mode = 1;
while(do_not_change_it)
{
/* Mask ARM i bit */
local_irq_save(flags);
core_id = (u32)smp_processor_id();
// set local timer & GPT =========================================
switch (core_id)
{
case 0 :
#if 0
/*trigger pcm timer*/
spm_write(SPM_POWER_ON_VAL1,(spm_read(SPM_POWER_ON_VAL1)&0xFFFFFFCF)|0x220);
spm_write(SPM_PCM_PWR_IO_EN,0x00800000);
spm_write(SPM_PCM_PWR_IO_EN,0x00000000);
#else
read_cntp_cval(lo, hi);
lo+=26000; // 100 ms, 13MHz
//lo+=5070000; // 390 ms, 13MHz
write_cntp_cval(lo, hi);
write_cntp_ctl(0x1); // CNTP_CTL_ENABLE
//printk("mcdi pdn cnt:%d\n",cpu_power_down_cnt);
#endif
break;
case 1 :
#if 0
//gpt_set_cmp(GPT4, 2470000); // 190ms, 13MHz
//printk("mcdi pdn cnt:%d\n",cpu_power_down_cnt);
gpt_set_cmp(GPT4, 130000); // 10ms, 13MHz
start_gpt(GPT4);
#endif
read_cntp_cval(lo, hi);
lo+=26000; // 100 ms, 13MHz
//lo+=5070000; // 390 ms, 13MHz
write_cntp_cval(lo, hi);
write_cntp_ctl(0x1); // CNTP_CTL_ENABLE
spm_mcdi_before_wfi(core_id);
break;
default : break;
}
spm_mcdi_wfi();
if(core_id==1)
spm_mcdi_after_wfi(core_id);
/* Un-Mask ARM i bit */
local_irq_restore(flags);
}
preempt_enable();
return 0;
}
