static void spi2_ios(void)
{
u32 val;
reg_set(RCC_APB2ENR, 0x08); /* Activate PortB */
/* Configure NSS pin (PB12) */
val = reg_rd(GPIOB + 0x04);
val &= 0xFFF0FFFF;
val |= 0x00030000; /* output, 50MHz, push-pull */
reg_wr(GPIOB+0x04, val);
reg_wr(GPIO_BSRR(GPIOB), (0x01 << 12)); /* Disable SS (nss=1) */
/* Configure SCK pin (PB13) */
val = reg_rd(GPIOB + 0x04);
val &= 0xFF0FFFFF;
val |= 0x00B00000; /* output, 50MHz, AF, push-pull */
reg_wr(GPIOB+0x04, val);
/* Configure MOSI pin (PB15) */
val = reg_rd(GPIOB + 0x04);
val &= 0x0FFFFFFF;
val |= 0xB0000000; /* output, 50MHz, AF, push-pull */
reg_wr(GPIOB+0x04, val);
/* Configure MISO pin (PB14) */
val = reg_rd(GPIOB + 0x04);
val &= 0xF0FFFFFF;
val |= 0x04000000; /* input, floating */
reg_wr(GPIOB + 0x04, val);
}
int main(void)
{
hw_init();
while(1)
{
/* Set LED on */
reg_wr((u32)GPIOI_BSRR, (0x1 << 1) );
/* Start Timer2 */
reg_set(TIM2_CR1, 1);
/* Wait Timer2 ends */
while(reg_rd(TIM2_CR1) & 1)
;
/* Set LED off */
reg_wr((u32)GPIOI_BSRR, (0x1 << 17) );
/* Start Timer2 */
reg_set(TIM2_CR1, 1);
/* Wait Timer2 ends */
while(reg_rd(TIM2_CR1) & 1)
;
}
}
static void spi1_ios(void)
{
u32 val;
reg_set(RCC_APB2ENR, 0x04); /* Activate GPIOA */
/* Configure NSS pin (PA4) */
val = reg_rd(GPIOA);
val &= 0xFFF0FFFF;
val |= 0x00030000; /* output, 50MHz, push-pull */
reg_wr(GPIOA, val);
reg_wr(GPIO_BSRR(GPIOA), (0x01 << 4)); /* Disable SS (nss=1) */
/* Configure SCK pin (PA5) */
val = reg_rd(GPIOA);
val &= 0xFF0FFFFF;
val |= 0x00B00000; /* output, 50MHz, AF, push-pull */
reg_wr(GPIOA, val);
/* Configure MOSI pin (PA7) */
val = reg_rd(GPIOA);
val &= 0x0FFFFFFF;
val |= 0xB0000000; /* output, 50MHz, AF, push-pull */
reg_wr(GPIOA, val);
/* Configure MISO pin (PA6) */
val = reg_rd(GPIOA);
val &= 0xF0FFFFFF;
val |= 0x04000000; /* input, floating */
reg_wr(GPIOA, val);
}
static void hw_init_timer(void)
{
reg_set(RCC_APB1ENR, 0x01); /* Activate Timer2 */
/* Configure Timer2 */
reg_wr (TIM2_CR1, 0x0200); /* Input clock divided by 4 */
reg_wr (TIM2_ARR, 0x8000); /* Value used when reloaded */
reg_wr (TIM2_PSC, 0x80); /* Prescaler */
reg_set(TIM2_CR1, 0x08); /* Set OPM (one-pulse-mode) */
}
void spi_init(void)
{
/* Configure SPI0 format */
reg_wr(SPI0_CR0, 0x07);
/* Enable SPI0 */
reg_wr(SPI0_CR1, 0x02);
return;
}
static void init_send_wr(struct rxe_qp *qp, struct rxe_send_wr *wr,
const struct ib_send_wr *ibwr)
{
wr->wr_id = ibwr->wr_id;
wr->num_sge = ibwr->num_sge;
wr->opcode = ibwr->opcode;
wr->send_flags = ibwr->send_flags;
if (qp_type(qp) == IB_QPT_UD ||
qp_type(qp) == IB_QPT_SMI ||
qp_type(qp) == IB_QPT_GSI) {
wr->wr.ud.remote_qpn = ud_wr(ibwr)->remote_qpn;
wr->wr.ud.remote_qkey = ud_wr(ibwr)->remote_qkey;
if (qp_type(qp) == IB_QPT_GSI)
wr->wr.ud.pkey_index = ud_wr(ibwr)->pkey_index;
if (wr->opcode == IB_WR_SEND_WITH_IMM)
wr->ex.imm_data = ibwr->ex.imm_data;
} else {
switch (wr->opcode) {
case IB_WR_RDMA_WRITE_WITH_IMM:
wr->ex.imm_data = ibwr->ex.imm_data;
/* fall through */
case IB_WR_RDMA_READ:
case IB_WR_RDMA_WRITE:
wr->wr.rdma.remote_addr = rdma_wr(ibwr)->remote_addr;
wr->wr.rdma.rkey = rdma_wr(ibwr)->rkey;
break;
case IB_WR_SEND_WITH_IMM:
wr->ex.imm_data = ibwr->ex.imm_data;
break;
case IB_WR_SEND_WITH_INV:
wr->ex.invalidate_rkey = ibwr->ex.invalidate_rkey;
break;
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_FETCH_AND_ADD:
wr->wr.atomic.remote_addr =
atomic_wr(ibwr)->remote_addr;
wr->wr.atomic.compare_add =
atomic_wr(ibwr)->compare_add;
wr->wr.atomic.swap = atomic_wr(ibwr)->swap;
wr->wr.atomic.rkey = atomic_wr(ibwr)->rkey;
break;
case IB_WR_LOCAL_INV:
wr->ex.invalidate_rkey = ibwr->ex.invalidate_rkey;
break;
case IB_WR_REG_MR:
wr->wr.reg.mr = reg_wr(ibwr)->mr;
wr->wr.reg.key = reg_wr(ibwr)->key;
wr->wr.reg.access = reg_wr(ibwr)->access;
break;
default:
break;
}
}
}
void spi0_init(void)
{
/* Configure SPI0 format */
reg_wr(SPI0_CR0, 0x07);
/* Configure main prescaler */
reg_wr(SPI0_CLK, 2);
/* Enable SPI0 */
reg_wr(SPI0_CR1, 0x02);
return;
}
static void hw_init_clock(void)
{
u32 val;
/* 1) Activate HSE, that will be used as PLL source */
/* Clear HSEON bit */
reg_clr(RCC_CR, 0x00010000);
/* Clear HSEBYP bit */
reg_clr(RCC_CR, 0x00040000);
/* Activate HSE (set HSEON) */
reg_set(RCC_CR, 0x00010000);
/* Wait until HSERDY bit set */
while( (reg_rd(RCC_CR) & 0x00020000) == 0)
;
/* 2) Configure and activate PLL */
/* Configure PLL */
val = (432 << 6); // set N (VCO multiplier)
val |= 25; // set M (VCO divisor)
val |= ( 0 << 16); // set P (output divisor
val |= ( 9 << 24); // set Q (peripheral divisor)
reg_wr(RCC_PLLCFGR, val);
/* Activate PLL */
reg_set(RCC_CR, 0x01000000);
while( (reg_rd(RCC_CR) & 0x02000000) == 0)
;
/* 3) Update flash latency, and peripheral bus prescaler */
/* Set Flash latency to 7 */
reg_set(FLASH_ACR, 0x07);
/* PCLK1 - Set APB1 clock divider to 4 (value 5) */
reg_set(RCC_CFGR, (5 << 10) );
/* PCLK2 - Set APB2 clock divider to 2 (value 4) */
reg_set(RCC_CFGR, (4 << 13) );
/* 4) Switch the current clock to PLL */
/* Change the clock source */
val = reg_rd(RCC_CFGR);
val &= ~0x03;
val |= 0x02;
reg_wr(RCC_CFGR, val);
/* Wait until, clock source is modified */
while( (reg_rd(RCC_CFGR) & 0x0C) != (0x02 << 2))
;
}
static void hw_init_gpio(void)
{
u32 val;
/* Activate GPIO-I controller */
val = reg_rd((u32)RCC_AHB1ENR);
val |= 0x0100;
reg_wr((u32)RCC_AHB1ENR, val);
/* Configure GPIOI-1 as output */
val = reg_rd((u32)GPIOI_MODER);
val |= (0x01 << 2);
reg_wr((u32)GPIOI_MODER, val);
}
void uart_init(void)
{
u32 baud;
u32 v;
v = hw_getfreq();
baud = (u32)(v / 115200);
/* Set the divider value for baud clock generator */
reg_wr(UART2_BASE + 0x10, baud);
/* Activate UART2 */
v = reg_rd(UART2_BASE + 0x08); /* Read CTRL reg */
v |= 0x03; /* Set RX enable and TX enable bits */
reg_wr(UART2_BASE + 0x08, v); /* Write back CTRL reg */
}
int jtag3ctrl_init(const void * rbf, int size)
{
int ret;
thinkos_escalate(jtag3ctrl_bus_init, NULL);
if ((ret = altera_configure(rbf, size)) < 0) {
DCC_LOG1(LOG_ERROR, "altera_configure() failed: %d!", ret);
INF(" # altera_configure() failed: %d!", ret);
return ret;
} else {
INF("- FPGA configuration done (%d bytes)", ret);
}
/* Enable clock output */
stm32f_mco2_enable();
/* wait for the FPGA initialize */
thinkos_sleep(20);
/* initial configuration */
reg_wr(REG_CFG, 0);
return 0;
}
void jtag3ctrl_loopback(bool enable)
{
unsigned int cfg;
cfg = reg_rd(REG_CFG);
cfg = (enable) ? cfg | CFG_LOOP : cfg & ~CFG_LOOP;
reg_wr(REG_CFG, cfg);
}
void jtag3ctrl_aux_uart(bool enable)
{
unsigned int cfg;
cfg = reg_rd(REG_CFG);
cfg = (enable) ? cfg | CFG_UART_EN : cfg & ~CFG_UART_EN;
reg_wr(REG_CFG, cfg);
}
void jtag3ctrl_rtck(bool enable)
{
int cfg = reg_rd(REG_CFG);
if (enable)
cfg |= CFG_RTCK_EN;
else
cfg &= ~CFG_RTCK_EN;
reg_wr(REG_CFG, cfg);
}
void jtag3ctrl_nrst(bool assert)
{
int cfg = reg_rd(REG_CFG);
if (assert)
cfg |= CFG_TAP_NRST;
else
cfg &= ~CFG_TAP_NRST;
reg_wr(REG_CFG, cfg);
}
static int iser_fast_reg_mr(struct iscsi_iser_task *iser_task,
struct iser_data_buf *mem,
struct iser_reg_resources *rsc,
struct iser_mem_reg *reg)
{
struct iser_tx_desc *tx_desc = &iser_task->desc;
struct ib_cqe *cqe = &iser_task->iser_conn->ib_conn.reg_cqe;
struct ib_mr *mr = rsc->mr;
struct ib_reg_wr *wr;
int n;
if (rsc->mr_valid)
iser_inv_rkey(iser_tx_next_wr(tx_desc), mr, cqe);
ib_update_fast_reg_key(mr, ib_inc_rkey(mr->rkey));
n = ib_map_mr_sg(mr, mem->sg, mem->size, NULL, SIZE_4K);
if (unlikely(n != mem->size)) {
iser_err("failed to map sg (%d/%d)\n",
n, mem->size);
return n < 0 ? n : -EINVAL;
}
wr = reg_wr(iser_tx_next_wr(tx_desc));
wr->wr.opcode = IB_WR_REG_MR;
wr->wr.wr_cqe = cqe;
wr->wr.send_flags = 0;
wr->wr.num_sge = 0;
wr->mr = mr;
wr->key = mr->rkey;
wr->access = IB_ACCESS_LOCAL_WRITE |
IB_ACCESS_REMOTE_WRITE |
IB_ACCESS_REMOTE_READ;
rsc->mr_valid = 1;
reg->sge.lkey = mr->lkey;
reg->rkey = mr->rkey;
reg->sge.addr = mr->iova;
reg->sge.length = mr->length;
iser_dbg("lkey=0x%x rkey=0x%x addr=0x%llx length=0x%x\n",
reg->sge.lkey, reg->rkey, reg->sge.addr, reg->sge.length);
return 0;
}
static void hw_init_clock(void)
{
u32 val;
/* Clear HSEON bit */
reg_clr(RCC_CR, 0x00010000);
/* Clear HSEBYP bit */
reg_clr(RCC_CR, 0x00040000);
/* Activate HSE (set HSEON) */
reg_set(RCC_CR, 0x00010000);
/* Wait until HSERDY bit set */
while( (reg_rd(RCC_CR) & 0x00020000) == 0)
;
/* Select HSE as new clock source */
val = reg_rd(RCC_CFGR);
val &= ~0x03;
val |= 0x01;
reg_wr(RCC_CFGR, val);
/* Wait until, clock source is modified */
while( (reg_rd(RCC_CFGR) & 0x0C) != (0x01 << 2))
;
}
bool jtag3ctrl_fpga_probe(void)
{
int cnt;
int j;
/* check whether the interrupts are working or not */
reg_wr(REG_TMR, 0);
/* enable timer interrupts */
reg_wr(REG_INT_EN, IRQ_TMR);
for (j = 0; j < 64; ++j) {
cnt = 100;
while (jtag3ctrl_irq_status()) {
/* clear interrupts */
reg_wr(REG_INT_ST, 0xffff);
if (--cnt == 0) {
DCC_LOG1(LOG_WARNING, "IRQ line stuck at high! %d", j);
INF("- FPGA IRQ probe failed. Stuck at high!");
return false;
}
}
reg_wr(REG_TMR, 4);
cnt = 100;
while (!jtag3ctrl_irq_status()) {
if (--cnt == 0) {
DCC_LOG(LOG_WARNING, "IRQ line stuck at low!");
INF("- FPGA IRQ probe failed. Stuck at low.");
return false;
}
}
/* clear interrupts */
reg_wr(REG_TMR, 0);
reg_wr(REG_INT_ST, 0xffff);
}
INF("- FPGA IRQ probe OK.");
return true;
}
static void hw_init_ltdc (void)
{
u32 val;
/* Activate GPIO controller */
val = reg_rd((u32)RCC_AHB1ENR);
val |= 0x0010; /* GPIO-E */
val |= 0x0040; /* GPIO-G */
val |= 0x0100; /* GPIO-I */
val |= 0x0200; /* GPIO-J */
val |= 0x0400; /* GPIO-K */
reg_wr((u32)RCC_AHB1ENR, val);
/* Configure GPIO-E pins mode */
val = reg_rd((u32)GPIOE_MODER);
val &= 0xFFFFFCFF; /* PE-4 : LCD_B0 */
val |= 0x00000200; /* PE-4 : use alternate function */
reg_wr((u32)GPIOE_MODER, val);
/* Configure GPIO-E alternate functions */
val = reg_rd((u32)GPIOE_AFRL);
val |= (0x0E << 16); /* PE-4 = AF14 : LTDC */
reg_wr((u32)GPIOE_AFRL, val);
/* Configure GPIO-G pins mode */
val = reg_rd((u32)GPIOG_MODER);
val |= (0x02 << 24); /* PG-12 : LCD_B4 */
reg_wr((u32)GPIOG_MODER, val);
/* Configure GPIO-G alternate functions */
val = reg_rd((u32)GPIOG_AFRH);
val |= (0x0E << 16); /* PG-12 = AF14 : LTDC */
reg_wr((u32)GPIOG_AFRH, val);
/* Configure GPIO-I pins mode */
val = reg_rd((u32)GPIOI_MODER);
val |= (0x02 << 18); /* PI-9 : LCD_VSYNC */
val |= (0x02 << 20); /* PI-10 : LCD_HSYNC */
val |= (0x02 << 28); /* PI-14 : LCD_CLK */
val |= (0x02 << 30); /* PI-15 : LCD_R0 */
val |= (0x01 << 24); /* PI-12 : LCD_DISP - manual output */
reg_wr((u32)GPIOI_MODER, val);
/* Configure GPIO-I alternate functions */
val = reg_rd((u32)GPIOI_AFRH);
val |= (0x0E << 4); /* PI-9 = AF14 : LTDC */
val |= (0x0E << 8); /* PI-10 = AF14 : LTDC */
val |= (0x0E << 24); /* PI-14 = AF14 : LTDC */
val |= (0x0E << 28); /* PI-15 = AF14 : LTDC */
reg_wr((u32)GPIOI_AFRH, val);
/* Configure GPIO-J pins mode */
val = reg_rd((u32)GPIOJ_MODER);
val &= 0x03000000; /* Reset all except PJ12 (used by USB) */
val |= 0xA8AAAAAA; /* Use alternate function for all lcd ios */
reg_wr((u32)GPIOJ_MODER, val);
/* Configure GPIO-J alternate functions */
val = 0xEEEEEEEE;
reg_wr((u32)GPIOJ_AFRL, val);
val = reg_rd((u32)GPIOJ_AFRH);
val &= 0x000F0000;
val |= 0xEEE0EEEE;
reg_wr((u32)GPIOJ_AFRH, val);
/* Configure GPIOK pins as alternate-function */
val = reg_rd((u32)GPIOK_MODER);
val |= (0x02 << 0); /* PK-0 : LCD_G5 */
val |= (0x02 << 2); /* PK-1 : LCD_G6 */
val |= (0x02 << 4); /* PK-2 : LCD_G7 */
val |= (0x01 << 6); /* PK-3 : LCD_BackLight - manual output */
val |= (0x02 << 8); /* PK-4 : LCD_B5 */
val |= (0x02 << 10); /* PK-5 : LCD_B6 */
val |= (0x02 << 12); /* PK-6 : LCD_B7 */
val |= (0x02 << 14); /* PK-7 : LCD_DE */
reg_wr((u32)GPIOK_MODER, val);
/* Configure GPIO-I alternate functions */
val = reg_rd((u32)GPIOK_AFRL);
val |= (0x0E << 0); /* PK-0 = AF14 : LTDC */
val |= (0x0E << 4); /* PK-1 = AF14 : LTDC */
val |= (0x0E << 8); /* PK-2 = AF14 : LTDC */
val |= (0x0E << 16); /* PK-4 = AF14 : LTDC */
val |= (0x0E << 20); /* PK-5 = AF14 : LTDC */
val |= (0x0E << 24); /* PK-6 = AF14 : LTDC */
val |= (0x0E << 28); /* PK-7 = AF14 : LTDC */
reg_wr((u32)GPIOK_AFRL, val);
/* 2) Configure Clocks */
val = reg_rd(RCC_PLLSAI);
/* Set VCO division factor (SAI "N") */
val &= ~(0x1FF << 6);
val |= (192 << 6);
/* Set LCD division factor (SAI "R") */
val &= ~(0x07 << 28);
val |= ( 5 << 28);
/* Update RCC PLLSAI */
reg_wr(RCC_PLLSAI, val);
/* Activate PLL-SAI */
reg_set(RCC_CR, 0x10000000);
while( (reg_rd(RCC_CR) & 0x20000000) == 0)
;
/* Update LCD dedicated clock prescaller */
val = reg_rd(RCC_DKCFGR1);
val &= ~(0x03 << 16);
val |= (0x01 << 16); /* div by 4 */
reg_wr(RCC_DKCFGR1, val);
}
/**
* Send one byte to the display
*
* @param c value to send
*/
void disp_putc(u8 c)
{
while ( (reg_rd(UART2_SR) & 0x80) != 0x80)
;
reg_wr(UART2_DR, c);
}
void spi_wr(u32 c)
{
while ( (reg_rd(SPI0_STATUS) & 0x02) == 0)
;
reg_wr(SPI0_DATA, c);
}
void uart_putc(u8 c)
{
while( reg_rd(UART2_STATE) & 0x01)
;
reg_wr(UART2_DATA, c);
}
void wr_byte(int dev, unsigned int addr, char data)
{
reg_wr(dev, XFL_BASE_ADDR + (addr << 2), data & 0x000000FF);
}
void jtag3ctrl_int_en(unsigned int mask)
{
reg_wr(REG_INT_EN, mask);
}
unsigned int jtag3ctrl_set_speed(unsigned int freq)
{
uint32_t brg_freq;
uint32_t brg_fmax;
uint32_t brg_fmin;
uint32_t tap_freq;
uint32_t cfg;
uint32_t clk;
int32_t div;
int sel;
int err;
int min = INT_MAX;
int best_sel;
brg_fmax = jtag_clk_tab[15] / 2;
brg_freq = freq * 2;
if (brg_freq > brg_fmax) {
brg_freq = brg_fmax;
}
brg_fmin = jtag_clk_tab[0] / 0x10000;
if (brg_freq < brg_fmin) {
brg_freq = brg_fmin;
}
DCC_LOG1(LOG_INFO, "brg freq=%d", brg_freq);
/* find the best matching frequency, but never bigger than
the desired frequency */
best_sel = -1;
for (sel = 0; sel <= 15; sel++) {
clk = jtag_clk_tab[sel];
div = ((clk + (brg_freq / 2)) / brg_freq) - 2;
/* range checking */
if (div < 0)
div = 0;
if (div >= 0xffff)
div = 0xfffe;
err = brg_freq - (clk / (div + 2));
DCC_LOG3(LOG_INFO, "clk=%d div=%d err=%d", clk, (div + 2),
brg_freq - (clk / (div + 2)));
if ((err >= 0) && (err < min)) {
min = err;
best_sel = sel;
if (err == 0)
break;
}
}
if (best_sel < 0)
best_sel = 0;
clk = jtag_clk_tab[best_sel];
div = ((clk + (brg_freq / 2)) / brg_freq) - 2;
/* range checking */
if (div < 0)
div = 0;
if (div >= 0xffff)
div = 0xfffe;
/* select the clock source */
cfg = reg_rd(REG_CFG) & ~CFG_CLK_SEL(0xf);
reg_wr(REG_CFG, cfg | CFG_CLK_SEL(best_sel));
/* configure the brg divisor */
reg_wr(REG_BRG_DIV, div);
brg_freq = clk / (div + 2);
tap_freq = brg_freq / 2;
DCC_LOG2(LOG_INFO, "sel: %d div: %d", best_sel, div + 2);
DCC_LOG4(LOG_TRACE, "clk=%d.%06d MHz, TAP freq: %d.%06d MHz",
clk / 1000000, clk % 1000000,
tap_freq / 1000000, tap_freq % 1000000);
return tap_freq;
}
void jtag3ctrl_sys_rst(void)
{
/* reset the controller */
reg_wr(REG_CFG, CFG_RST);
}
void jtag3ctrl_int_clr(unsigned int mask)
{
reg_wr(REG_INT_ST, mask);
}